From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Gwan-gyeong Mun" <gwan-gyeong.mun@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Do not allow DC3CO if PSR SF is enabled
Date: Mon, 22 Feb 2021 12:25:56 -0000 [thread overview]
Message-ID: <161399675687.19117.13892803343549246492@emeril.freedesktop.org> (raw)
In-Reply-To: <20210222112415.1523930-1-gwan-gyeong.mun@intel.com>
== Series Details ==
Series: drm/i915/display: Do not allow DC3CO if PSR SF is enabled
URL : https://patchwork.freedesktop.org/series/87283/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
64ad41f78f8f drm/i915/display: Do not allow DC3CO if PSR SF is enabled
-:12: WARNING:TYPO_SPELLING: 'wiil' may be misspelled - perhaps 'will'?
#12:
Selective Fetch wiil be enabled by default.
^^^^
-:35: CHECK:BRACES: braces {} should be used on all arms of this statement
#35: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:807:
+ if (INTEL_GEN(dev_priv) >= 12) {
[...]
+ } else if (IS_GEN(dev_priv, 11))
[...]
else if (IS_GEN9_LP(dev_priv))
[...]
total: 0 errors, 1 warnings, 1 checks, 33 lines checked
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next prev parent reply other threads:[~2021-02-22 12:25 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 11:24 [Intel-gfx] [PATCH] drm/i915/display: Do not allow DC3CO if PSR SF is enabled Gwan-gyeong Mun
2021-02-22 12:25 ` Patchwork [this message]
2021-02-22 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-02-22 14:05 ` [Intel-gfx] [PATCH] " Souza, Jose
2021-02-22 15:16 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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