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Sun, 28 Feb 2021 11:29:17 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 6890D13C09CF; Mon, 1 Mar 2021 01:04:01 +0530 (IST) From: Sai Pavan Boddu To: Markus Armbruster , Kevin Wolf , "Max Reitz" , Vladimir Sementsov-Ogievskiy , Eric Blake , Joel Stanley , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Vincent Palatin , "Dr. David Alan Gilbert" , Thomas Huth , Stefan Hajnoczi , Peter Maydell , "Alistair Francis" , "Edgar E. Iglesias" , Luc Michel , "Paolo Bonzini" Subject: [PATCH v3 05/21] sd: emmc: Add support for EXT_CSD & CSD for eMMC Date: Mon, 1 Mar 2021 01:03:11 +0530 Message-ID: <1614540807-30686-6-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614540807-30686-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1614540807-30686-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 162b0378-04a7-4fa0-b536-08d8dc1f2c8c X-MS-TrafficTypeDiagnostic: MWHPR0201MB3545: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:81; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: niBRxuejSM88lB0AndN1BsDbCwaM6MVzkxfPV5yqhk8UnFVXVpaG21u2oGVPAmbLDsBF+UGDr0ELJ3pE9tjRDF2HWUBq6qfDJiy4upDF76HwDaLDEMRqGo8K3iYaA9ltJ/TydPekRsIso+tf3xZC3OLlNOxDTHKhegMYG5qtv7BZgIvbbEikWA5UhEOB785E2JjPrPnnKjgwM9uO1Z2a7t7L2ON3rZ8Gj+HjBOWYLIRG2ANqJ00kXqVjowNyhvs4xziSi5b+md4HNIKS4cqCiGuSDeWeoAAUPGwqxIqO8WFSPibQkRm/nNe0sop4knVkE1pqD0gqXt7eHFeFZKtK72v63u1aPpVYk+ES69C63ySSwOh3AUZUA4AkNan05ZyPQLKVLsgp+jxkdmZooguGtCeQIomEeYHkbJ/u+FOf8U96rkwxEqGUMbVjaFs4jvqpEVoS77TyCSKvFbnIfvb8ybOE4lcMc59J2qRH8WVb9GUaAcpnLc2WLbJeCigaADmRuGSK2dlHM6qNcnGVA5jwzVmtNZDppke3msGdyhxapV7o0ry98WDcbRLty5vCDe7OUk/yP2DY0B+S9ercBOUpV10ZipCDjqpwo0Ok+Efxr8P+qUt240KpkbzWdkUTc+w+yFxz4u3E0AUo1VQ93xTgPzpj0UKTfdPMq9UXdtsGkhRfeaR4f7HyOG36xH/RiPEnX5cyjefsnFCl48AAKQBmkw== X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(396003)(136003)(346002)(39850400004)(376002)(46966006)(36840700001)(82740400003)(316002)(478600001)(186003)(7636003)(42186006)(26005)(356005)(6666004)(426003)(70206006)(36906005)(70586007)(36756003)(4326008)(110136005)(6266002)(36860700001)(8676002)(54906003)(7416002)(8936002)(921005)(107886003)(82310400003)(2906002)(66574015)(83380400001)(336012)(47076005)(2616005)(5660300002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2021 19:29:32.1021 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 162b0378-04a7-4fa0-b536-08d8dc1f2c8c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT032.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR0201MB3545 Received-SPF: pass client-ip=40.107.223.67; envelope-from=saipava@xilinx.com; helo=NAM11-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: saipava@xilinx.com, qemu-devel@nongnu.org, qemu-block@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Vincent Palatin eMMC CSD is similar to SD with an option to refer EXT_CSD for larger devices. Signed-off-by: Vincent Palatin [clg: Add user friendly macros for EXT_CSD register] Signed-off-by: Cédric Le Goater [spb: updated commit message] Signed-off-by: Sai Pavan Boddu --- hw/sd/sdmmc-internal.h | 97 ++++++++++++++++++++++++++++++++++++++++++++++++++ hw/sd/sd.c | 61 +++++++++++++++++++++++++++++-- 2 files changed, 156 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdmmc-internal.h b/hw/sd/sdmmc-internal.h index d8bf17d..7ab7b4d 100644 --- a/hw/sd/sdmmc-internal.h +++ b/hw/sd/sdmmc-internal.h @@ -37,4 +37,101 @@ const char *sd_cmd_name(uint8_t cmd); */ const char *sd_acmd_name(uint8_t cmd); +/* + * EXT_CSD fields + */ + +#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */ +#define EXT_CSD_FLUSH_CACHE 32 /* W */ +#define EXT_CSD_CACHE_CTRL 33 /* R/W */ +#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ +#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ +#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ +#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ +#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ +#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ +#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ +#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ +#define EXT_CSD_HPI_MGMT 161 /* R/W */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W */ +#define EXT_CSD_BKOPS_START 164 /* W */ +#define EXT_CSD_SANITIZE_START 165 /* W */ +#define EXT_CSD_WR_REL_PARAM 166 /* RO */ +#define EXT_CSD_RPMB_MULT 168 /* RO */ +#define EXT_CSD_FW_CONFIG 169 /* R/W */ +#define EXT_CSD_BOOT_WP 173 /* R/W */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ +#define EXT_CSD_PART_CONFIG 179 /* R/W */ +#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_POWER_CLASS 187 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_STRUCTURE 194 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ +#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ +#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ +#define EXT_CSD_PWR_CL_52_195 200 /* RO */ +#define EXT_CSD_PWR_CL_26_195 201 /* RO */ +#define EXT_CSD_PWR_CL_52_360 202 /* RO */ +#define EXT_CSD_PWR_CL_26_360 203 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ +#define EXT_CSD_S_A_TIMEOUT 217 /* RO */ +#define EXT_CSD_S_C_VCCQ 219 /* RO */ +#define EXT_CSD_S_C_VCC 220 /* RO */ +#define EXT_CSD_REL_WR_SEC_C 222 /* RO */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ +#define EXT_CSD_ACC_SIZE 225 /* RO */ +#define EXT_CSD_BOOT_MULT 226 /* RO */ +#define EXT_CSD_BOOT_INFO 228 /* RO */ +#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ +#define EXT_CSD_TRIM_MULT 232 /* RO */ +#define EXT_CSD_PWR_CL_200_195 236 /* RO */ +#define EXT_CSD_PWR_CL_200_360 237 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ +#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ +#define EXT_CSD_BKOPS_STATUS 246 /* RO */ +#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ +#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ +#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ +#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ +#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ +#define EXT_CSD_PRE_EOL_INFO 267 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ +#define EXT_CSD_CMDQ_DEPTH 307 /* RO */ +#define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ +#define EXT_CSD_SUPPORTED_MODE 493 /* RO */ +#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ +#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ +#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ +#define EXT_CSD_MAX_PACKED_READS 501 /* RO */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ +#define EXT_CSD_HPI_FEATURES 503 /* RO */ +#define EXT_CSD_S_CMD_SET 504 /* RO */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_WR_REL_PARAM_EN (1 << 2) +#define EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR (1 << 4) + +#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) +#define EXT_CSD_PART_CONFIG_ACC_DEFAULT (0x0) +#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) + +#define EXT_CSD_PART_CONFIG_EN_MASK (0x7 << 3) +#define EXT_CSD_PART_CONFIG_EN_BOOT0 (0x1 << 3) +#define EXT_CSD_PART_CONFIG_EN_USER (0x7 << 3) + #endif diff --git a/hw/sd/sd.c b/hw/sd/sd.c index bc9d913..a26695b 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -135,6 +135,7 @@ struct SDState { uint64_t data_start; uint32_t data_offset; uint8_t data[512]; + uint8_t ext_csd[512]; qemu_irq readonly_cb; qemu_irq inserted_cb; QEMUTimer *ocr_power_timer; @@ -393,6 +394,55 @@ static const uint8_t sd_csd_rw_mask[16] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xfe, }; +static void mmc_set_ext_csd(SDState *sd, uint64_t size) +{ + uint32_t sectcount = size >> HWBLOCK_SHIFT; + + memset(sd->ext_csd, 0, sizeof(sd->ext_csd)); + sd->ext_csd[EXT_CSD_S_CMD_SET] = 0x1; /* supported command sets */ + sd->ext_csd[EXT_CSD_HPI_FEATURES] = 0x3; /* HPI features */ + sd->ext_csd[EXT_CSD_BKOPS_SUPPORT] = 0x1; /* Background operations + support */ + sd->ext_csd[241] = 0xA; /* 1st initialization time after partitioning */ + sd->ext_csd[EXT_CSD_TRIM_MULT] = 0x1; /* Trim multiplier */ + sd->ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT] = 0x15; /* Secure feature + support */ + sd->ext_csd[EXT_CSD_SEC_ERASE_MULT] = 0x96; /* Secure erase support */ + sd->ext_csd[EXT_CSD_SEC_TRIM_MULT] = 0x96; /* Secure TRIM multiplier */ + sd->ext_csd[EXT_CSD_BOOT_INFO] = 0x7; /* Boot information */ + sd->ext_csd[EXT_CSD_BOOT_MULT] = 0x8; /* Boot partition size. 128KB unit */ + sd->ext_csd[EXT_CSD_ACC_SIZE] = 0x6; /* Access size */ + sd->ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] = 0x4; /* HC Erase unit size */ + sd->ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT] = 0x1; /* HC erase timeout */ + sd->ext_csd[EXT_CSD_REL_WR_SEC_C] = 0x1; /* Reliable write sector count */ + sd->ext_csd[EXT_CSD_HC_WP_GRP_SIZE] = 0x4; /* HC write protect group size */ + sd->ext_csd[EXT_CSD_S_C_VCC] = 0x8; /* Sleep current VCC */ + sd->ext_csd[EXT_CSD_S_C_VCCQ] = 0x7; /* Sleep current VCCQ */ + sd->ext_csd[EXT_CSD_S_A_TIMEOUT] = 0x11; /* Sleep/Awake timeout */ + sd->ext_csd[215] = (sectcount >> 24) & 0xff; /* Sector count */ + sd->ext_csd[214] = (sectcount >> 16) & 0xff; /* ... */ + sd->ext_csd[213] = (sectcount >> 8) & 0xff; /* ... */ + sd->ext_csd[EXT_CSD_SEC_CNT] = (sectcount & 0xff); /* ... */ + sd->ext_csd[210] = 0xa; /* Min write perf for 8bit@52Mhz */ + sd->ext_csd[209] = 0xa; /* Min read perf for 8bit@52Mhz */ + sd->ext_csd[208] = 0xa; /* Min write perf for 4bit@52Mhz */ + sd->ext_csd[207] = 0xa; /* Min read perf for 4bit@52Mhz */ + sd->ext_csd[206] = 0xa; /* Min write perf for 4bit@26Mhz */ + sd->ext_csd[205] = 0xa; /* Min read perf for 4bit@26Mhz */ + sd->ext_csd[EXT_CSD_PART_SWITCH_TIME] = 0x1; /* Partition switching + timing */ + sd->ext_csd[EXT_CSD_OUT_OF_INTERRUPT_TIME] = 0x1; /* Out-of-interrupt busy + timing */ + sd->ext_csd[EXT_CSD_CARD_TYPE] = 0xFF; /* Card type */ + sd->ext_csd[EXT_CSD_STRUCTURE] = 0x2; /* CSD Structure version */ + sd->ext_csd[EXT_CSD_REV] = 0x5; /* Extended CSD revision */ + sd->ext_csd[EXT_CSD_RPMB_MULT] = 0x1; /* RPMB size */ + sd->ext_csd[EXT_CSD_PARTITION_SUPPORT] = 0x3; /* Partinioning support */ + sd->ext_csd[159] = 0x00; /* Max enhanced area size */ + sd->ext_csd[158] = 0x00; /* ... */ + sd->ext_csd[157] = 0xEC; /* ... */ +} + static void sd_set_csd(SDState *sd, uint64_t size) { int hwblock_shift = HWBLOCK_SHIFT; @@ -406,8 +456,11 @@ static void sd_set_csd(SDState *sd, uint64_t size) } csize = (size >> (CMULT_SHIFT + hwblock_shift)) - 1; - if (size <= SDSC_MAX_CAPACITY) { /* Standard Capacity SD */ - sd->csd[0] = 0x00; /* CSD structure */ + if (size <= SDSC_MAX_CAPACITY || sd->emmc) { /* Standard Capacity SD */ + if (sd->emmc && size >= SDSC_MAX_CAPACITY) { + csize = 0xfff; + } + sd->csd[0] = sd->emmc ? 0xd0 : 0x00; /* CSD structure */ sd->csd[1] = 0x26; /* Data read access-time-1 */ sd->csd[2] = 0x00; /* Data read access-time-2 */ sd->csd[3] = 0x32; /* Max. data transfer rate: 25 MHz */ @@ -451,6 +504,10 @@ static void sd_set_csd(SDState *sd, uint64_t size) sd->csd[14] = 0x00; } sd->csd[15] = (sd_crc7(sd->csd, 15) << 1) | 1; + + if (sd->emmc) { + mmc_set_ext_csd(sd, size); + } } static void sd_set_rca(SDState *sd, uint16_t value) -- 2.7.4