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[58.6.239.121]) by smtp.gmail.com with ESMTPSA id o1sm1942262pjp.4.2021.03.16.00.36.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Mar 2021 00:36:10 -0700 (PDT) Date: Tue, 16 Mar 2021 17:36:04 +1000 From: Nicholas Piggin Subject: Re: [PATCH v3 28/32] powerpc/64s: interrupt implement exit logic in C To: Christophe Leroy , linuxppc-dev@lists.ozlabs.org References: <20200225173541.1549955-1-npiggin@gmail.com> <20200225173541.1549955-29-npiggin@gmail.com> <2d68d9ad-c3a2-2372-a5b2-1a1e3fdb41e4@csgroup.eu> In-Reply-To: <2d68d9ad-c3a2-2372-a5b2-1a1e3fdb41e4@csgroup.eu> MIME-Version: 1.0 Message-Id: <1615879834.64tfygznle.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Michal Suchanek Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" Excerpts from Christophe Leroy's message of March 15, 2021 11:41 pm: >=20 >=20 > Le 25/02/2020 =C3=A0 18:35, Nicholas Piggin a =C3=A9crit=C2=A0: >> Implement the bulk of interrupt return logic in C. The asm return code >> must handle a few cases: restoring full GPRs, and emulating stack store. >>=20 >> The stack store emulation is significantly simplfied, rather than creati= ng >> a new return frame and switching to that before performing the store, it >> uses the PACA to keep a scratch register around to perform thestore. >>=20 >> The asm return code is moved into 64e for now. The new logic has made >> allowance for 64e, but I don't have a full environment that works well >> to test it, and even booting in emulated qemu is not great for stress >> testing. 64e shouldn't be too far off working with this, given a bit >> more testing and auditing of the logic. >>=20 >> This is slightly faster on a POWER9 (page fault speed increases about >> 1.1%), probably due to reduced mtmsrd. >>=20 >> Signed-off-by: Nicholas Piggin >> Signed-off-by: Michal Suchanek >> --- >=20 > ... >=20 >> +notrace unsigned long interrupt_exit_user_prepare(struct pt_regs *regs,= unsigned long msr) >> +{ >=20 > ... >=20 >> + >> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM >> + local_paca->tm_scratch =3D regs->msr; >> +#endif >=20 > Could we define a helper for that in asm/tm.h, that voids when CONFIG_PPC= _TRANSACTIONAL_MEM is not=20 > selected ? Yeah I wanted to do something about that. I don't know what it's used=20 for here. I guess it saves the return MSR so if that causes a crash then=20 the next oops would see it, but I wonder if we can just get that from=20 SRR1 + program check error codes, or if there is something we can't reconstruct from there. Have to check with someone who knows TM better. Thanks, Nick