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From: Nicholas Piggin <npiggin@gmail.com>
To: "Cédric Le Goater" <clg@kaod.org>, linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors
Date: Fri, 02 Apr 2021 18:00:09 +1000	[thread overview]
Message-ID: <1617350337.h91a37wruo.astroid@bobo.none> (raw)
In-Reply-To: <0f41c067-7b9f-5b98-0993-c81cbaeea265@kaod.org>

Excerpts from Cédric Le Goater's message of April 2, 2021 4:10 pm:
> On 4/2/21 4:41 AM, Nicholas Piggin wrote:
>> Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt
>> mode for HV=1 interrupts. Instead, a new LPCR[HAIL] bit is defined
>> which behaves like AIL=3 for HV interrupts when set.
> 
> Will QEMU need an update ? 

Yes you're right it will, we need to do that.

Thanks,
Nick

  reply	other threads:[~2021-04-02  8:00 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02  2:41 [PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors Nicholas Piggin
2021-04-02  6:10 ` Cédric Le Goater
2021-04-02  8:00   ` Nicholas Piggin [this message]
2021-04-07 11:33 ` Michael Ellerman
2021-04-07 12:13   ` Nicholas Piggin
2021-04-19  4:00 ` Michael Ellerman

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