* [PULL 0/5] target-arm queue
@ 2021-04-12 10:31 Peter Maydell
2021-04-12 10:31 ` [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Peter Maydell
` (6 more replies)
0 siblings, 7 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
Handful of arm fixes for the rc.
The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412
for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
* hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
* accel/tcg: Preserve PAGE_ANON when changing page permissions
* target/arm: Check PAGE_WRITE_ORG for MTE writeability
* exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
----------------------------------------------------------------
Richard Henderson (3):
accel/tcg: Preserve PAGE_ANON when changing page permissions
target/arm: Check PAGE_WRITE_ORG for MTE writeability
exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
Zenghui Yu (2):
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
include/exec/cpu-all.h | 4 ++--
tests/tcg/aarch64/mte.h | 3 ++-
accel/tcg/translate-all.c | 9 ++++++--
hw/arm/smmuv3.c | 12 +++++++----
hw/arm/virt-acpi-build.c | 4 ++--
target/arm/mte_helper.c | 2 +-
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 2 +-
8 files changed, 66 insertions(+), 13 deletions(-)
create mode 100644 tests/tcg/aarch64/mte-6.c
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
@ 2021-04-12 10:31 ` Peter Maydell
2021-04-12 10:31 ` [PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs Peter Maydell
` (5 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
From: Zenghui Yu <yuzenghui@huawei.com>
The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.
Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f5a2b2d4cb5..60fe2e65a76 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
smmu->event_gsiv = cpu_to_le32(irq);
smmu->pri_gsiv = cpu_to_le32(irq + 1);
- smmu->gerr_gsiv = cpu_to_le32(irq + 2);
- smmu->sync_gsiv = cpu_to_le32(irq + 3);
+ smmu->sync_gsiv = cpu_to_le32(irq + 2);
+ smmu->gerr_gsiv = cpu_to_le32(irq + 3);
/* Identity RID mapping covering the whole input RID range */
idmap = &smmu->id_mapping_array[0];
--
2.20.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
2021-04-12 10:31 ` [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Peter Maydell
@ 2021-04-12 10:31 ` Peter Maydell
2021-04-12 10:31 ` [PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions Peter Maydell
` (4 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
From: Zenghui Yu <yuzenghui@huawei.com>
In emulation of the CFGI_STE_RANGE command, we now take StreamID as the
start of the invalidation range, regardless of whatever the Range is,
whilst the spec clearly states that
- "Invalidation is performed for an *aligned* range of 2^(Range+1)
StreamIDs."
- "The bottom Range+1 bits of the StreamID parameter are IGNORED,
aligning the range to its size."
Take CFGI_ALL (where Range == 31) as an example, if there are some random
bits in the StreamID field, we'll fail to perform the full invalidation but
get a strange range (e.g., SMMUSIDRange={.start=1, .end=0}) instead. Rework
the emulation a bit to get rid of the discrepancy with the spec.
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402100449.528-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 3b87324ce22..87056125357 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -980,16 +980,20 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
}
case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */
{
- uint32_t start = CMD_SID(&cmd);
+ uint32_t sid = CMD_SID(&cmd), mask;
uint8_t range = CMD_STE_RANGE(&cmd);
- uint64_t end = start + (1ULL << (range + 1)) - 1;
- SMMUSIDRange sid_range = {start, end};
+ SMMUSIDRange sid_range;
if (CMD_SSEC(&cmd)) {
cmd_error = SMMU_CERROR_ILL;
break;
}
- trace_smmuv3_cmdq_cfgi_ste_range(start, end);
+
+ mask = (1ULL << (range + 1)) - 1;
+ sid_range.start = sid & ~mask;
+ sid_range.end = sid_range.start + mask;
+
+ trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
&sid_range);
break;
--
2.20.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
2021-04-12 10:31 ` [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Peter Maydell
2021-04-12 10:31 ` [PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs Peter Maydell
@ 2021-04-12 10:31 ` Peter Maydell
2021-04-12 10:31 ` [PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability Peter Maydell
` (3 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Using mprotect() to change PROT_* does not change the MAP_ANON
previously set with mmap(). Our linux-user version of MTE only
works with MAP_ANON pages, so losing PAGE_ANON caused MTE to
stop working.
Reported-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/tcg/aarch64/mte.h | 3 ++-
accel/tcg/translate-all.c | 9 +++++--
tests/tcg/aarch64/mte-6.c | 43 +++++++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 2 +-
4 files changed, 53 insertions(+), 4 deletions(-)
create mode 100644 tests/tcg/aarch64/mte-6.c
diff --git a/tests/tcg/aarch64/mte.h b/tests/tcg/aarch64/mte.h
index 141cef522ce..0805676b116 100644
--- a/tests/tcg/aarch64/mte.h
+++ b/tests/tcg/aarch64/mte.h
@@ -48,7 +48,8 @@ static void enable_mte(int tcf)
}
}
-static void *alloc_mte_mem(size_t size)
+static void * alloc_mte_mem(size_t size) __attribute__((unused));
+static void * alloc_mte_mem(size_t size)
{
void *p = mmap(NULL, size, PROT_READ | PROT_WRITE | PROT_MTE,
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f32df8b2404..ba6ab09790e 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -2714,6 +2714,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
a missing call to h2g_valid. */
assert(end - 1 <= GUEST_ADDR_MAX);
assert(start < end);
+ /* Only set PAGE_ANON with new mappings. */
+ assert(!(flags & PAGE_ANON) || (flags & PAGE_RESET));
assert_memory_lock();
start = start & TARGET_PAGE_MASK;
@@ -2737,11 +2739,14 @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
p->first_tb) {
tb_invalidate_phys_page(addr, 0);
}
- if (reset_target_data && p->target_data) {
+ if (reset_target_data) {
g_free(p->target_data);
p->target_data = NULL;
+ p->flags = flags;
+ } else {
+ /* Using mprotect on a page does not change MAP_ANON. */
+ p->flags = (p->flags & PAGE_ANON) | flags;
}
- p->flags = flags;
}
}
diff --git a/tests/tcg/aarch64/mte-6.c b/tests/tcg/aarch64/mte-6.c
new file mode 100644
index 00000000000..60d51d18be5
--- /dev/null
+++ b/tests/tcg/aarch64/mte-6.c
@@ -0,0 +1,43 @@
+#include "mte.h"
+
+void pass(int sig, siginfo_t *info, void *uc)
+{
+ assert(info->si_code == SEGV_MTESERR);
+ exit(0);
+}
+
+int main(void)
+{
+ enable_mte(PR_MTE_TCF_SYNC);
+
+ void *brk = sbrk(16);
+ if (brk == (void *)-1) {
+ perror("sbrk");
+ return 2;
+ }
+
+ if (mprotect(brk, 16, PROT_READ | PROT_WRITE | PROT_MTE)) {
+ perror("mprotect");
+ return 2;
+ }
+
+ int *p1, *p2;
+ long excl = 1;
+
+ asm("irg %0,%1,%2" : "=r"(p1) : "r"(brk), "r"(excl));
+ asm("gmi %0,%1,%0" : "+r"(excl) : "r"(p1));
+ asm("irg %0,%1,%2" : "=r"(p2) : "r"(brk), "r"(excl));
+ asm("stg %0,[%0]" : : "r"(p1));
+
+ *p1 = 0;
+
+ struct sigaction sa;
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_sigaction = pass;
+ sa.sa_flags = SA_SIGINFO;
+ sigaction(SIGSEGV, &sa, NULL);
+
+ *p2 = 0;
+
+ abort();
+}
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
index 56e48f4b34f..05b2622bfc9 100644
--- a/tests/tcg/aarch64/Makefile.target
+++ b/tests/tcg/aarch64/Makefile.target
@@ -37,7 +37,7 @@ AARCH64_TESTS += bti-2
# MTE Tests
ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),)
-AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4
+AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-6
mte-%: CFLAGS += -march=armv8.5-a+memtag
endif
--
2.20.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2021-04-12 10:31 ` [PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions Peter Maydell
@ 2021-04-12 10:31 ` Peter Maydell
2021-04-12 10:31 ` [PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 Peter Maydell
` (2 subsequent siblings)
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
We can remove PAGE_WRITE when (internally) marking a page
read-only because it contains translated code.
This can be triggered by tests/tcg/aarch64/bti-2, after
having serviced SIGILL trampolines on the stack.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 0bbb9ec3463..8be17e1b707 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -83,7 +83,7 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
uint8_t *tags;
uintptr_t index;
- if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE : PAGE_READ))) {
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
/* SIGSEGV */
arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access,
ptr_mmu_idx, false, ra);
--
2.20.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* [PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2021-04-12 10:31 ` [PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability Peter Maydell
@ 2021-04-12 10:31 ` Peter Maydell
2021-04-12 10:42 ` [PULL 0/5] target-arm queue no-reply
2021-04-12 14:50 ` Peter Maydell
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 10:31 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Unfortuately, the elements of PAGE_* were not in numerical
order and so PAGE_ANON was added to an "unused" bit.
As an arbitrary choice, move PAGE_TARGET_{1,2} together.
Cc: Laurent Vivier <laurent@vivier.eu>
Fixes: 26bab757d41b ("linux-user: Introduce PAGE_ANON")
Buglink: https://bugs.launchpad.net/bugs/1922617
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Laurent Vivier <laurent@vivier.eu>
Tested-by: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/exec/cpu-all.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d76b0b9e02d..32cfb634c6a 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -268,8 +268,8 @@ extern intptr_t qemu_host_page_mask;
#define PAGE_RESERVED 0x0100
#endif
/* Target-specific bits that will be used via page_get_flags(). */
-#define PAGE_TARGET_1 0x0080
-#define PAGE_TARGET_2 0x0200
+#define PAGE_TARGET_1 0x0200
+#define PAGE_TARGET_2 0x0400
#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);
--
2.20.1
^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2021-04-12 10:31 ` [PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 Peter Maydell
@ 2021-04-12 10:42 ` no-reply
2021-04-12 14:50 ` Peter Maydell
6 siblings, 0 replies; 24+ messages in thread
From: no-reply @ 2021-04-12 10:42 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
Patchew URL: https://patchew.org/QEMU/20210412103152.28433-1-peter.maydell@linaro.org/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210412103152.28433-1-peter.maydell@linaro.org
Subject: [PULL 0/5] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210412103152.28433-1-peter.maydell@linaro.org -> patchew/20210412103152.28433-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b54ded2 exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
5f7d9e7 target/arm: Check PAGE_WRITE_ORG for MTE writeability
a3fb10e accel/tcg: Preserve PAGE_ANON when changing page permissions
435ceeb hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
21190f3 hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
=== OUTPUT BEGIN ===
1/5 Checking commit 21190f31d420 (hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts)
2/5 Checking commit 435ceeb0c89a (hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs)
3/5 Checking commit a3fb10ec0d23 (accel/tcg: Preserve PAGE_ANON when changing page permissions)
Use of uninitialized value $acpi_testexpected in string eq at ./scripts/checkpatch.pl line 1529.
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#69:
new file mode 100644
ERROR: "foo * bar" should be "foo *bar"
#126: FILE: tests/tcg/aarch64/mte.h:51:
+static void * alloc_mte_mem(size_t size) __attribute__((unused));
ERROR: "foo * bar" should be "foo *bar"
#127: FILE: tests/tcg/aarch64/mte.h:52:
+static void * alloc_mte_mem(size_t size)
total: 2 errors, 1 warnings, 84 lines checked
Patch 3/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/5 Checking commit 5f7d9e72dc1b (target/arm: Check PAGE_WRITE_ORG for MTE writeability)
WARNING: line over 80 characters
#30: FILE: target/arm/mte_helper.c:86:
+ if (!(flags & (ptr_access == MMU_DATA_STORE ? PAGE_WRITE_ORG : PAGE_READ))) {
total: 0 errors, 1 warnings, 8 lines checked
Patch 4/5 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/5 Checking commit b54ded2ab9fb (exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210412103152.28433-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2021-04-12 10:42 ` [PULL 0/5] target-arm queue no-reply
@ 2021-04-12 14:50 ` Peter Maydell
6 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-04-12 14:50 UTC (permalink / raw)
To: QEMU Developers
On Mon, 12 Apr 2021 at 11:31, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Handful of arm fixes for the rc.
>
> The following changes since commit 555249a59e9cdd6b58da103aba5cf3a2d45c899f:
>
> Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-04-10 16:58:56 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210412
>
> for you to fetch changes up to 52c01ada86611136e3122dd139788dbcbc292d86:
>
> exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 (2021-04-12 11:06:24 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
> * hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs
> * accel/tcg: Preserve PAGE_ANON when changing page permissions
> * target/arm: Check PAGE_WRITE_ORG for MTE writeability
> * exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2024-04-02 10:29 Peter Maydell
@ 2024-04-02 11:58 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2024-04-02 11:58 UTC (permalink / raw)
To: qemu-devel
On Tue, 2 Apr 2024 at 11:29, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Nothing exciting here: two minor bug fixes, some fixes for
> running on a 32-bit host, and a docs tweak.
>
> thanks
> -- PMM
>
> The following changes since commit 6af9d12c88b9720f209912f6e4b01fefe5906d59:
>
> Merge tag 'migration-20240331-pull-request' of https://gitlab.com/peterx/qemu into staging (2024-04-01 13:12:40 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240402
>
> for you to fetch changes up to 393770d7a02135e7468018f52da610712f151ec0:
>
> raspi4b: Reduce RAM to 1Gb on 32-bit hosts (2024-04-02 10:13:48 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * take HSTR traps of cp15 accesses to EL2, not EL1
> * docs: sbsa: update specs, add dt note
> * hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
> * tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
> * raspi4b: Reduce RAM to 1Gb on 32-bit hosts
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2024-04-02 10:29 Peter Maydell
2024-04-02 11:58 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2024-04-02 10:29 UTC (permalink / raw)
To: qemu-devel
Nothing exciting here: two minor bug fixes, some fixes for
running on a 32-bit host, and a docs tweak.
thanks
-- PMM
The following changes since commit 6af9d12c88b9720f209912f6e4b01fefe5906d59:
Merge tag 'migration-20240331-pull-request' of https://gitlab.com/peterx/qemu into staging (2024-04-01 13:12:40 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240402
for you to fetch changes up to 393770d7a02135e7468018f52da610712f151ec0:
raspi4b: Reduce RAM to 1Gb on 32-bit hosts (2024-04-02 10:13:48 +0100)
----------------------------------------------------------------
target-arm queue:
* take HSTR traps of cp15 accesses to EL2, not EL1
* docs: sbsa: update specs, add dt note
* hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
* tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
* raspi4b: Reduce RAM to 1Gb on 32-bit hosts
----------------------------------------------------------------
Cédric Le Goater (2):
tests/qtest: Fix STM32L4x5 GPIO test on 32-bit
raspi4b: Reduce RAM to 1Gb on 32-bit hosts
Marcin Juszkiewicz (1):
docs: sbsa: update specs, add dt note
Peter Maydell (2):
target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled
docs/system/arm/sbsa.rst | 35 +++++++++++++++++------
hw/arm/raspi4b.c | 4 +++
hw/intc/arm_gicv3_cpuif.c | 4 +--
target/arm/tcg/translate.c | 2 +-
tests/qtest/stm32l4x5_gpio-test.c | 59 +++++++++++++++++++++++----------------
5 files changed, 68 insertions(+), 36 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2023-07-25 10:24 Peter Maydell
@ 2023-07-25 14:49 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2023-07-25 14:49 UTC (permalink / raw)
To: qemu-devel
On Tue, 25 Jul 2023 at 11:25, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> target-arm queue: just bugfixes, mostly mine.
>
> thanks
> -- PMM
>
> The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
>
> Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
>
> for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
>
> tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * tests/decode: Suppress "error: " string for expected-failure tests
> * ui/curses: For curses display, recognize a few more control keys
> * target/arm: Special case M-profile in debug_helper.c code
> * scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
> * hw/arm/smmu: Handle big-endian hosts correctly
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.1
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2023-07-25 10:24 Peter Maydell
2023-07-25 14:49 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2023-07-25 10:24 UTC (permalink / raw)
To: qemu-devel
target-arm queue: just bugfixes, mostly mine.
thanks
-- PMM
The following changes since commit 885fc169f09f5915ce037263d20a59eb226d473d:
Merge tag 'pull-riscv-to-apply-20230723-3' of https://github.com/alistair23/qemu into staging (2023-07-24 11:34:35 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230725
for you to fetch changes up to 78cc90346ec680a7f1bb9f138bf7c9654cf526d5:
tests/decode: Suppress "error: " string for expected-failure tests (2023-07-25 10:56:52 +0100)
----------------------------------------------------------------
target-arm queue:
* tests/decode: Suppress "error: " string for expected-failure tests
* ui/curses: For curses display, recognize a few more control keys
* target/arm: Special case M-profile in debug_helper.c code
* scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
* hw/arm/smmu: Handle big-endian hosts correctly
----------------------------------------------------------------
Peter Maydell (4):
hw/arm/smmu: Handle big-endian hosts correctly
scripts/git-submodule.sh: Don't rely on non-POSIX 'read' behaviour
target/arm: Special case M-profile in debug_helper.c code
tests/decode: Suppress "error: " string for expected-failure tests
Sean Estabrooks (1):
For curses display, recognize a few more control keys
ui/curses_keys.h | 6 ++++++
hw/arm/smmu-common.c | 3 +--
hw/arm/smmuv3.c | 39 +++++++++++++++++++++++++++++++--------
target/arm/debug_helper.c | 18 ++++++++++++------
scripts/decodetree.py | 6 +++++-
scripts/git-submodule.sh | 2 +-
6 files changed, 56 insertions(+), 18 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2022-11-21 21:10 ` Peter Maydell
@ 2022-11-21 21:23 ` Stefan Hajnoczi
0 siblings, 0 replies; 24+ messages in thread
From: Stefan Hajnoczi @ 2022-11-21 21:23 UTC (permalink / raw)
To: Peter Maydell; +Cc: Stefan Hajnoczi, qemu-devel
On Mon, 21 Nov 2022 at 16:11, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Mon, 21 Nov 2022 at 15:54, Stefan Hajnoczi <stefanha@redhat.com> wrote:
> >
> > Applied, thanks.
>
> This doesn't seem to have reached https://gitlab.com/qemu-project/qemu.git:
> did something go wrong?
I forgot to push staging to master. Thanks for letting me know!
Stefan
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2022-11-21 15:54 ` Stefan Hajnoczi
@ 2022-11-21 21:10 ` Peter Maydell
2022-11-21 21:23 ` Stefan Hajnoczi
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2022-11-21 21:10 UTC (permalink / raw)
To: Stefan Hajnoczi; +Cc: qemu-devel
On Mon, 21 Nov 2022 at 15:54, Stefan Hajnoczi <stefanha@redhat.com> wrote:
>
> Applied, thanks.
This doesn't seem to have reached https://gitlab.com/qemu-project/qemu.git:
did something go wrong?
thanks
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2022-11-21 13:02 Peter Maydell
@ 2022-11-21 15:54 ` Stefan Hajnoczi
2022-11-21 21:10 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Stefan Hajnoczi @ 2022-11-21 15:54 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 115 bytes --]
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2022-11-21 13:02 Peter Maydell
2022-11-21 15:54 ` Stefan Hajnoczi
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2022-11-21 13:02 UTC (permalink / raw)
To: qemu-devel
Hi; here's a collection of Arm bug fixes for rc2.
thanks
-- PMM
The following changes since commit a082fab9d259473a9d5d53307cf83b1223301181:
Merge tag 'pull-ppc-20221117' of https://gitlab.com/danielhb/qemu into staging (2022-11-17 12:39:38 -0500)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221121
for you to fetch changes up to 312b71abce3005ca7294dc0db7d548dc7cc41fbf:
target/arm: Limit LPA2 effective output address when TCR.DS == 0 (2022-11-21 11:46:46 +0000)
----------------------------------------------------------------
target-arm queue:
* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
* hw/intc: add implementation of GICD_IIDR to Arm GIC
* tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
* target/arm: Limit LPA2 effective output address when TCR.DS == 0
----------------------------------------------------------------
Alex Bennée (2):
hw/intc: clean-up access to GIC multi-byte registers
hw/intc: add implementation of GICD_IIDR to Arm GIC
Ard Biesheuvel (1):
target/arm: Limit LPA2 effective output address when TCR.DS == 0
Peter Maydell (1):
tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
Strahinja Jankovic (1):
hw/sd: Fix sun4i allwinner-sdhost for U-Boot
include/hw/sd/allwinner-sdhost.h | 1 +
hw/intc/arm_gic.c | 28 ++++++++++++-----
hw/sd/allwinner-sdhost.c | 67 +++++++++++++++++++++++++++-------------
target/arm/ptw.c | 8 +++++
tests/avocado/boot_linux.py | 2 +-
5 files changed, 77 insertions(+), 29 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2022-08-12 11:45 Peter Maydell
@ 2022-08-12 21:02 ` Richard Henderson
0 siblings, 0 replies; 24+ messages in thread
From: Richard Henderson @ 2022-08-12 21:02 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 8/12/22 04:45, Peter Maydell wrote:
> This pullreq has:
> * two arm bug fixes which fix some "Linux fails to boot" bugs
> * a docs typo-fixing patch
> * a couple of compile failure/warning issues
>
> I think they're all pretty safe and worth having in rc3.
>
> thanks
> -- PMM
>
> The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:
>
> Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812
>
> for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
>
> cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Don't report Statistical Profiling Extension in ID registers
> * virt ACPI tables: Present the GICR structure properly for GICv4
> * Fix some typos in documentation
> * tests/unit: fix a -Wformat-truncation warning
> * cutils: Add missing dyld(3) include on macOS
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
r~
>
> ----------------------------------------------------------------
> Marc-André Lureau (1):
> tests/unit: fix a -Wformat-truncation warning
>
> Peter Maydell (1):
> target/arm: Don't report Statistical Profiling Extension in ID registers
>
> Philippe Mathieu-Daudé (1):
> cutils: Add missing dyld(3) include on macOS
>
> Stefan Weil (1):
> Fix some typos in documentation (most of them found by codespell)
>
> Zenghui Yu (1):
> hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
>
> docs/about/deprecated.rst | 2 +-
> docs/specs/acpi_erst.rst | 4 ++--
> docs/system/devices/canokey.rst | 8 ++++----
> docs/system/devices/cxl.rst | 12 ++++++------
> hw/arm/virt-acpi-build.c | 4 ++--
> target/arm/cpu.c | 11 +++++++++++
> tests/unit/test-qobject-input-visitor.c | 3 +--
> util/cutils.c | 4 ++++
> util/oslib-posix.c | 4 ----
> 9 files changed, 31 insertions(+), 21 deletions(-)
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2022-08-12 11:45 Peter Maydell
2022-08-12 21:02 ` Richard Henderson
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2022-08-12 11:45 UTC (permalink / raw)
To: qemu-devel
This pullreq has:
* two arm bug fixes which fix some "Linux fails to boot" bugs
* a docs typo-fixing patch
* a couple of compile failure/warning issues
I think they're all pretty safe and worth having in rc3.
thanks
-- PMM
The following changes since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:
Merge tag 'linux-user-for-7.1-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220812
for you to fetch changes up to 4311682ea8293f720730f260e8a7601117d79e65:
cutils: Add missing dyld(3) include on macOS (2022-08-12 11:33:52 +0100)
----------------------------------------------------------------
target-arm queue:
* Don't report Statistical Profiling Extension in ID registers
* virt ACPI tables: Present the GICR structure properly for GICv4
* Fix some typos in documentation
* tests/unit: fix a -Wformat-truncation warning
* cutils: Add missing dyld(3) include on macOS
----------------------------------------------------------------
Marc-André Lureau (1):
tests/unit: fix a -Wformat-truncation warning
Peter Maydell (1):
target/arm: Don't report Statistical Profiling Extension in ID registers
Philippe Mathieu-Daudé (1):
cutils: Add missing dyld(3) include on macOS
Stefan Weil (1):
Fix some typos in documentation (most of them found by codespell)
Zenghui Yu (1):
hw/arm/virt-acpi-build: Present the GICR structure properly for GICv4
docs/about/deprecated.rst | 2 +-
docs/specs/acpi_erst.rst | 4 ++--
docs/system/devices/canokey.rst | 8 ++++----
docs/system/devices/cxl.rst | 12 ++++++------
hw/arm/virt-acpi-build.c | 4 ++--
target/arm/cpu.c | 11 +++++++++++
tests/unit/test-qobject-input-visitor.c | 3 +--
util/cutils.c | 4 ++++
util/oslib-posix.c | 4 ----
9 files changed, 31 insertions(+), 21 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2021-11-29 10:39 Peter Maydell
@ 2021-11-29 12:53 ` Richard Henderson
0 siblings, 0 replies; 24+ messages in thread
From: Richard Henderson @ 2021-11-29 12:53 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 11/29/21 11:39 AM, Peter Maydell wrote:
> Hi; this is a collection of mostly GIC related patches for rc3.
> The "Update cached state after LPI state changes" fix is important
> and fixes what would otherwise be a regression since we enable the
> ITS by default in the virt board now. The others are not regressions
> but I think are OK for rc3 as they're fairly self contained (and two
> of them are fixes to new-in-6.2 functionality).
>
> thanks
> -- PMM
>
> The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
>
> Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129
>
> for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
>
> hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
> * GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
> * GICv3: Update cached state after LPI state changes
> * GICv3: Fix handling of LPIs in list registers
>
> ----------------------------------------------------------------
> Alexander Graf (1):
> hw/arm/virt: Extend nested and mte checks to hvf
>
> Peter Maydell (3):
> hw/intc/arm_gicv3: Update cached state after LPI state changes
> hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
> hw/intc/arm_gicv3: fix handling of LPIs in list registers
>
> Shashi Mallela (1):
> hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
>
> hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++
> hw/arm/virt.c | 15 +++++++++------
> hw/intc/arm_gicv3.c | 6 ++++--
> hw/intc/arm_gicv3_cpuif.c | 9 ++++-----
> hw/intc/arm_gicv3_its.c | 7 ++++---
> hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
> 6 files changed, 61 insertions(+), 20 deletions(-)
Applied, thanks.
r~
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2021-11-29 10:39 Peter Maydell
2021-11-29 12:53 ` Richard Henderson
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2021-11-29 10:39 UTC (permalink / raw)
To: qemu-devel
Hi; this is a collection of mostly GIC related patches for rc3.
The "Update cached state after LPI state changes" fix is important
and fixes what would otherwise be a regression since we enable the
ITS by default in the virt board now. The others are not regressions
but I think are OK for rc3 as they're fairly self contained (and two
of them are fixes to new-in-6.2 functionality).
thanks
-- PMM
The following changes since commit dd4b0de45965538f19bb40c7ddaaba384a8c613a:
Fix version for v6.2.0-rc2 release (2021-11-26 11:58:54 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20211129
for you to fetch changes up to 90feffad2aafe856ed2af75313b2c1669ba671e9:
hw/intc/arm_gicv3: fix handling of LPIs in list registers (2021-11-29 10:10:21 +0000)
----------------------------------------------------------------
target-arm queue:
* virt: Diagnose attempts to enable MTE or virt when using HVF accelerator
* GICv3 ITS: Allow clearing of ITS CTLR Enabled bit
* GICv3: Update cached state after LPI state changes
* GICv3: Fix handling of LPIs in list registers
----------------------------------------------------------------
Alexander Graf (1):
hw/arm/virt: Extend nested and mte checks to hvf
Peter Maydell (3):
hw/intc/arm_gicv3: Update cached state after LPI state changes
hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function
hw/intc/arm_gicv3: fix handling of LPIs in list registers
Shashi Mallela (1):
hw/intc: cannot clear GICv3 ITS CTLR[Enabled] bit
hw/intc/gicv3_internal.h | 30 ++++++++++++++++++++++++++++++
hw/arm/virt.c | 15 +++++++++------
hw/intc/arm_gicv3.c | 6 ++++--
hw/intc/arm_gicv3_cpuif.c | 9 ++++-----
hw/intc/arm_gicv3_its.c | 7 ++++---
hw/intc/arm_gicv3_redist.c | 14 ++++++++++----
6 files changed, 61 insertions(+), 20 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2021-03-30 13:25 Peter Maydell
@ 2021-03-30 17:13 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2021-03-30 17:13 UTC (permalink / raw)
To: QEMU Developers
On Tue, 30 Mar 2021 at 14:25, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The following changes since commit 7993b0f83fe5c3f8555e79781d5d098f99751a94:
>
> Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-03-29 18:45:12 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330
>
> for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:
>
> hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() (2021-03-30 14:05:34 +0100)
>
> ----------------------------------------------------------------
> * net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
> * hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
> * hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
> * target/arm: Make number of counters in PMCR follow the CPU
> * hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2021-03-30 13:25 Peter Maydell
2021-03-30 17:13 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2021-03-30 13:25 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 7993b0f83fe5c3f8555e79781d5d098f99751a94:
Merge remote-tracking branch 'remotes/nvme/tags/nvme-fixes-for-6.0-pull-request' into staging (2021-03-29 18:45:12 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git pull-target-arm-20210330
for you to fetch changes up to b9e3f1579a4b06fc63dfa8cdb68df1c58eeb0cf1:
hw/timer/renesas_tmr: Add default-case asserts in read_tcnt() (2021-03-30 14:05:34 +0100)
----------------------------------------------------------------
* net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
* hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
* hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
* target/arm: Make number of counters in PMCR follow the CPU
* hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
----------------------------------------------------------------
Doug Evans (1):
net/npcm7xx_emc.c: Fix handling of receiving packets when RSDR not set
Peter Maydell (2):
target/arm: Make number of counters in PMCR follow the CPU
hw/timer/renesas_tmr: Add default-case asserts in read_tcnt()
Philippe Mathieu-Daudé (1):
hw/display/xlnx_dp: Free FIFOs adding xlnx_dp_finalize()
Zenghui Yu (1):
hw/arm/smmuv3: Drop unused CDM_VALID() and is_cd_valid()
hw/arm/smmuv3-internal.h | 7 -------
target/arm/cpu.h | 1 +
hw/display/xlnx_dp.c | 9 +++++++++
hw/net/npcm7xx_emc.c | 4 +++-
hw/timer/renesas_tmr.c | 4 ++++
target/arm/cpu64.c | 3 +++
target/arm/cpu_tcg.c | 5 +++++
target/arm/helper.c | 29 +++++++++++++++++------------
target/arm/kvm64.c | 2 ++
tests/qtest/npcm7xx_emc-test.c | 30 +++++++++++++++++++++---------
10 files changed, 65 insertions(+), 29 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PULL 0/5] target-arm queue
2020-03-23 17:40 Peter Maydell
@ 2020-03-23 20:54 ` Peter Maydell
0 siblings, 0 replies; 24+ messages in thread
From: Peter Maydell @ 2020-03-23 20:54 UTC (permalink / raw)
To: QEMU Developers
On Mon, 23 Mar 2020 at 17:40, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Just a few minor bugfixes, but we might as well get them in
> for rc0 tomorrow.
>
> -- PMM
>
> The following changes since commit 787f82407c5056a8b1097e39e53d01dd1abe406b:
>
> Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200323' into staging (2020-03-23 15:38:30 +0000)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200323
>
> for you to fetch changes up to 550a04893c2bd4442211b353680b9a6408d94dba:
>
> target/arm: Move computation of index in handle_simd_dupe (2020-03-23 17:22:30 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
> * target/arm: avoid undefined behaviour shift in watchpoint code
> * target/arm: avoid undefined behaviour shift in handle_simd_dupe()
> * target/arm: add assert that immh != 0 in disas_simd_shift_imm()
> * aspeed/smc: Fix DMA support for AST2600
> * hw/arm/bcm283x: Correct the license text ('and' vs 'or')
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PULL 0/5] target-arm queue
@ 2020-03-23 17:40 Peter Maydell
2020-03-23 20:54 ` Peter Maydell
0 siblings, 1 reply; 24+ messages in thread
From: Peter Maydell @ 2020-03-23 17:40 UTC (permalink / raw)
To: qemu-devel
Just a few minor bugfixes, but we might as well get them in
for rc0 tomorrow.
-- PMM
The following changes since commit 787f82407c5056a8b1097e39e53d01dd1abe406b:
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200323' into staging (2020-03-23 15:38:30 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200323
for you to fetch changes up to 550a04893c2bd4442211b353680b9a6408d94dba:
target/arm: Move computation of index in handle_simd_dupe (2020-03-23 17:22:30 +0000)
----------------------------------------------------------------
target-arm queue:
* target/arm: avoid undefined behaviour shift in watchpoint code
* target/arm: avoid undefined behaviour shift in handle_simd_dupe()
* target/arm: add assert that immh != 0 in disas_simd_shift_imm()
* aspeed/smc: Fix DMA support for AST2600
* hw/arm/bcm283x: Correct the license text ('and' vs 'or')
----------------------------------------------------------------
Cédric Le Goater (1):
aspeed/smc: Fix DMA support for AST2600
Philippe Mathieu-Daudé (1):
hw/arm/bcm283x: Correct the license text
Richard Henderson (3):
target/arm: Rearrange disabled check for watchpoints
target/arm: Assert immh != 0 in disas_simd_shift_imm
target/arm: Move computation of index in handle_simd_dupe
include/hw/arm/bcm2835_peripherals.h | 3 ++-
include/hw/arm/bcm2836.h | 3 ++-
include/hw/char/bcm2835_aux.h | 3 ++-
include/hw/display/bcm2835_fb.h | 3 ++-
include/hw/dma/bcm2835_dma.h | 4 +++-
include/hw/intc/bcm2835_ic.h | 4 +++-
include/hw/intc/bcm2836_control.h | 3 ++-
include/hw/misc/bcm2835_mbox.h | 4 +++-
include/hw/misc/bcm2835_mbox_defs.h | 4 +++-
include/hw/misc/bcm2835_property.h | 4 +++-
hw/arm/aspeed_ast2600.c | 6 ++++++
hw/arm/bcm2835_peripherals.c | 3 ++-
hw/arm/bcm2836.c | 3 ++-
hw/arm/raspi.c | 3 ++-
hw/display/bcm2835_fb.c | 1 -
hw/dma/bcm2835_dma.c | 4 +++-
hw/intc/bcm2835_ic.c | 4 ++--
hw/intc/bcm2836_control.c | 4 +++-
hw/misc/bcm2835_mbox.c | 4 +++-
hw/misc/bcm2835_property.c | 4 +++-
hw/ssi/aspeed_smc.c | 15 +++++++++++++--
target/arm/helper.c | 11 ++++++-----
target/arm/translate-a64.c | 6 +++++-
hw/ssi/trace-events | 1 +
24 files changed, 76 insertions(+), 28 deletions(-)
^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2024-04-02 12:01 UTC | newest]
Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-12 10:31 [PULL 0/5] target-arm queue Peter Maydell
2021-04-12 10:31 ` [PULL 1/5] hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts Peter Maydell
2021-04-12 10:31 ` [PULL 2/5] hw/arm/smmuv3: Emulate CFGI_STE_RANGE for an aligned range of StreamIDs Peter Maydell
2021-04-12 10:31 ` [PULL 3/5] accel/tcg: Preserve PAGE_ANON when changing page permissions Peter Maydell
2021-04-12 10:31 ` [PULL 4/5] target/arm: Check PAGE_WRITE_ORG for MTE writeability Peter Maydell
2021-04-12 10:31 ` [PULL 5/5] exec: Fix overlap of PAGE_ANON and PAGE_TARGET_1 Peter Maydell
2021-04-12 10:42 ` [PULL 0/5] target-arm queue no-reply
2021-04-12 14:50 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2024-04-02 10:29 Peter Maydell
2024-04-02 11:58 ` Peter Maydell
2023-07-25 10:24 Peter Maydell
2023-07-25 14:49 ` Peter Maydell
2022-11-21 13:02 Peter Maydell
2022-11-21 15:54 ` Stefan Hajnoczi
2022-11-21 21:10 ` Peter Maydell
2022-11-21 21:23 ` Stefan Hajnoczi
2022-08-12 11:45 Peter Maydell
2022-08-12 21:02 ` Richard Henderson
2021-11-29 10:39 Peter Maydell
2021-11-29 12:53 ` Richard Henderson
2021-03-30 13:25 Peter Maydell
2021-03-30 17:13 ` Peter Maydell
2020-03-23 17:40 Peter Maydell
2020-03-23 20:54 ` Peter Maydell
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