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From: Nicholas Piggin <npiggin@gmail.com>
To: Fabiano Rosas <farosas@linux.ibm.com>, qemu-ppc@nongnu.org
Cc: "Cédric Le Goater" <clg@fr.ibm.com>,
	qemu-devel@nongnu.org,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: Re: [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour
Date: Wed, 14 Apr 2021 13:26:40 +1000	[thread overview]
Message-ID: <1618370656.ss5qyaukyq.astroid@bobo.none> (raw)
In-Reply-To: <87y2dm47nb.fsf@linux.ibm.com>

Excerpts from Fabiano Rosas's message of April 13, 2021 11:48 pm:
> Nicholas Piggin <npiggin@gmail.com> writes:
> 
>> ISA v3.0 radix guest execution has a quirk in AIL behaviour such that
>> the LPCR[AIL] value can apply to hypervisor interrupts.
>>
>> This affects machines that emulate HV=1 mode (i.e., powernv9).
>>
> 
> Ah ok, so we actually want to replicate the quirk in the pnv
> machine. Took me a while.

Yes. Quirk is probably the wrong word for me to use. It's architected 
behaviour so it must be implemented, it's just slightly surprising /
easy to miss.

> 
> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>

Thanks,
Nick

> 
>> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
>> ---
>>  target/ppc/excp_helper.c | 17 +++++++++++++----
>>  1 file changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
>> index 85de7e6c90..b8881c0f85 100644
>> --- a/target/ppc/excp_helper.c
>> +++ b/target/ppc/excp_helper.c
>> @@ -791,14 +791,23 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
>>  #endif
>>  
>>      /*
>> -     * AIL only works if there is no HV transition and we are running
>> -     * with translations enabled
>> +     * AIL only works if MSR[IR] and MSR[DR] are both enabled.
>>       */
>> -    if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1) ||
>> -        ((new_msr & MSR_HVB) && !(msr & MSR_HVB))) {
>> +    if (!((msr >> MSR_IR) & 1) || !((msr >> MSR_DR) & 1)) {
>>          ail = 0;
>>      }
>>  
>> +    /*
>> +     * AIL does not work if there is a MSR[HV] 0->1 transition and the
>> +     * partition is in HPT mode. For radix guests, such interrupts are
>> +     * allowed to be delivered to the hypervisor in ail mode.
>> +     */
>> +    if ((new_msr & MSR_HVB) && !(msr & MSR_HVB)) {
>> +        if (!(env->spr[SPR_LPCR] & LPCR_HR)) {
>> +            ail = 0;
>> +        }
>> +    }
>> +
>>      vector = env->excp_vectors[excp];
>>      if (vector == (target_ulong)-1ULL) {
>>          cpu_abort(cs, "Raised an exception without defined vector %d\n",
> 


  reply	other threads:[~2021-04-14  3:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13 12:54 [PATCH v1 0/3] POWER9/POWER10 exception model fixes Nicholas Piggin
2021-04-13 12:54 ` [PATCH v1 1/3] target/ppc: Fix POWER9 radix guest HV interrupt AIL behaviour Nicholas Piggin
2021-04-13 13:48   ` Fabiano Rosas
2021-04-14  3:26     ` Nicholas Piggin [this message]
2021-04-13 14:31   ` [EXTERNAL] " Cédric Le Goater
2021-04-13 12:54 ` [PATCH v1 2/3] target/ppc: POWER10 supports scv Nicholas Piggin
2021-04-13 14:18   ` [EXTERNAL] " Cédric Le Goater
2021-04-13 15:54   ` Fabiano Rosas
2021-04-13 12:54 ` [PATCH v1 3/3] target/ppc: Add POWER10 exception model Nicholas Piggin
2021-04-13 15:53   ` Fabiano Rosas
2021-04-13 17:09     ` Cédric Le Goater
2021-04-14  1:56       ` Nicholas Piggin
2021-04-14  3:28     ` Nicholas Piggin

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