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* [PATCH net v2 0/2] Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
@ 2021-04-22 17:31 ` Kunihiko Hayashi
  0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier PXs2, LD20, and PXs3 boards have RTL8211E ethernet phy, and the
phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY
and TXDLY pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Changes since v1:
- Fix the commit message

Kunihiko Hayashi (2):
  ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins
    for RTL8211E
  arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins
    for RTL8211E

 arch/arm/boot/dts/uniphier-pxs2.dtsi             | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH net v2 0/2] Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
@ 2021-04-22 17:31 ` Kunihiko Hayashi
  0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier PXs2, LD20, and PXs3 boards have RTL8211E ethernet phy, and the
phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY
and TXDLY pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Changes since v1:
- Fix the commit message

Kunihiko Hayashi (2):
  ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins
    for RTL8211E
  arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins
    for RTL8211E

 arch/arm/boot/dts/uniphier-pxs2.dtsi             | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH net v2 1/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
  2021-04-22 17:31 ` Kunihiko Hayashi
@ 2021-04-22 17:31   ` Kunihiko Hayashi
  -1 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier PXs2 boards have RTL8211E ethernet phy, and the phy have the RX/TX
delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Fixes: e3cc931921d2 ("ARM: dts: uniphier: add AVE ethernet node")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 4d9f69a..5ba831e 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -583,7 +583,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH net v2 1/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
@ 2021-04-22 17:31   ` Kunihiko Hayashi
  0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier PXs2 boards have RTL8211E ethernet phy, and the phy have the RX/TX
delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Fixes: e3cc931921d2 ("ARM: dts: uniphier: add AVE ethernet node")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm/boot/dts/uniphier-pxs2.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 4d9f69a..5ba831e 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -583,7 +583,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH net v2 2/2] arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
  2021-04-22 17:31 ` Kunihiko Hayashi
@ 2021-04-22 17:31   ` Kunihiko Hayashi
  -1 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier LD20 and PXs3 boards have RTL8211E ethernet phy, and the phy have
the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY
pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Fixes: c73730ee4c9a ("arm64: dts: uniphier: add AVE ethernet node")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 52dee61..bd9959f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -806,7 +806,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 80e2597..2038f51 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -564,7 +564,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
@@ -585,7 +585,7 @@
 			clocks = <&sys_clk 7>;
 			reset-names = "ether";
 			resets = <&sys_rst 7>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 1>;
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 8+ messages in thread
* [PATCH net v2 2/2] arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
@ 2021-04-22 17:31   ` Kunihiko Hayashi
  0 siblings, 0 replies; 8+ messages in thread
From: Kunihiko Hayashi @ 2021-04-22 17:31 UTC (permalink / raw)
  To: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
	Jakub Kicinski
  Cc: netdev, devicetree, linux-arm-kernel, Masami Hiramatsu,
	Jassi Brar, Kunihiko Hayashi

UniPhier LD20 and PXs3 boards have RTL8211E ethernet phy, and the phy have
the RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY
pins.

After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
delay config"), the delays are working correctly, however, "rgmii" means
no delay and the phy doesn't work. So need to set the phy-mode to
"rgmii-id" to show that RX/TX delays are enabled.

Fixes: c73730ee4c9a ("arm64: dts: uniphier: add AVE ethernet node")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
 arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 52dee61..bd9959f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -806,7 +806,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 80e2597..2038f51 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -564,7 +564,7 @@
 			clocks = <&sys_clk 6>;
 			reset-names = "ether";
 			resets = <&sys_rst 6>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 0>;
 
@@ -585,7 +585,7 @@
 			clocks = <&sys_clk 7>;
 			reset-names = "ether";
 			resets = <&sys_rst 7>;
-			phy-mode = "rgmii";
+			phy-mode = "rgmii-id";
 			local-mac-address = [00 00 00 00 00 00];
 			socionext,syscon-phy-mode = <&soc_glue 1>;
 
-- 
2.7.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 8+ messages in thread
* Re: [PATCH net v2 0/2] Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
  2021-04-22 17:31 ` Kunihiko Hayashi
@ 2021-04-22 22:10   ` patchwork-bot+netdevbpf
  -1 siblings, 0 replies; 8+ messages in thread
From: patchwork-bot+netdevbpf @ 2021-04-22 22:10 UTC (permalink / raw)
  To: Kunihiko Hayashi
  Cc: robh+dt, andrew, hkallweit1, davem, kuba, netdev, devicetree,
	linux-arm-kernel, masami.hiramatsu, jaswinder.singh

Hello:

This series was applied to netdev/net.git (refs/heads/master):

On Fri, 23 Apr 2021 02:31:47 +0900 you wrote:
> UniPhier PXs2, LD20, and PXs3 boards have RTL8211E ethernet phy, and the
> phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY
> and TXDLY pins.
> 
> After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
> delay config"), the delays are working correctly, however, "rgmii" means
> no delay and the phy doesn't work. So need to set the phy-mode to
> "rgmii-id" to show that RX/TX delays are enabled.
> 
> [...]

Here is the summary with links:
  - [net,v2,1/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
    https://git.kernel.org/netdev/net/c/9ba585cc5b56
  - [net,v2,2/2] arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
    https://git.kernel.org/netdev/net/c/dcabb06bf127

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



^ permalink raw reply	[flat|nested] 8+ messages in thread
* Re: [PATCH net v2 0/2] Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
@ 2021-04-22 22:10   ` patchwork-bot+netdevbpf
  0 siblings, 0 replies; 8+ messages in thread
From: patchwork-bot+netdevbpf @ 2021-04-22 22:10 UTC (permalink / raw)
  To: Kunihiko Hayashi
  Cc: robh+dt, andrew, hkallweit1, davem, kuba, netdev, devicetree,
	linux-arm-kernel, masami.hiramatsu, jaswinder.singh

Hello:

This series was applied to netdev/net.git (refs/heads/master):

On Fri, 23 Apr 2021 02:31:47 +0900 you wrote:
> UniPhier PXs2, LD20, and PXs3 boards have RTL8211E ethernet phy, and the
> phy have the RX/TX delays of RGMII interface using pull-ups on the RXDLY
> and TXDLY pins.
> 
> After the commit bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx
> delay config"), the delays are working correctly, however, "rgmii" means
> no delay and the phy doesn't work. So need to set the phy-mode to
> "rgmii-id" to show that RX/TX delays are enabled.
> 
> [...]

Here is the summary with links:
  - [net,v2,1/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
    https://git.kernel.org/netdev/net/c/9ba585cc5b56
  - [net,v2,2/2] arm64: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins for RTL8211E
    https://git.kernel.org/netdev/net/c/dcabb06bf127

You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-04-22 22:13 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-22 17:31 [PATCH net v2 0/2] Change phy-mode to RGMII-ID to enable delay pins for RTL8211E Kunihiko Hayashi
2021-04-22 17:31 ` Kunihiko Hayashi
2021-04-22 17:31 ` [PATCH net v2 1/2] ARM: dts: uniphier: " Kunihiko Hayashi
2021-04-22 17:31   ` Kunihiko Hayashi
2021-04-22 17:31 ` [PATCH net v2 2/2] arm64: " Kunihiko Hayashi
2021-04-22 17:31   ` Kunihiko Hayashi
2021-04-22 22:10 ` [PATCH net v2 0/2] " patchwork-bot+netdevbpf
2021-04-22 22:10   ` patchwork-bot+netdevbpf

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