* [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches
@ 2021-04-28 21:12 Anusha Srivatsa
2021-04-28 21:12 ` [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err Anusha Srivatsa
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2021-04-28 21:12 UTC (permalink / raw)
To: intel-gfx
This series adds the prep work needed before the
actual Pipe DMC implementation.
Anusha Srivatsa (3):
drm/i915/csr: s/DRM_ERROR/drm_err
drm/i915/csr: Add intel_csr_has_dmc_payload() helper
drm/i915/csr: Introduce DMC_FW_MAIN
drivers/gpu/drm/i915/display/intel_csr.c | 94 +++++++++----------
drivers/gpu/drm/i915/display/intel_csr.h | 33 +++++++
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../drm/i915/display/intel_display_power.c | 16 ++--
drivers/gpu/drm/i915/i915_drv.h | 18 +---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
6 files changed, 92 insertions(+), 75 deletions(-)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
@ 2021-04-28 21:12 ` Anusha Srivatsa
2021-05-03 18:03 ` Jani Nikula
2021-04-28 21:12 ` [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper Anusha Srivatsa
` (6 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2021-04-28 21:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
Use new format of debug messages across intel_csr.
While at it, change some function definitions which now
need dev_priv for drm_err and drm_info etc.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 44 +++++++++++++-----------
1 file changed, 23 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 26a922d34263..bf60c3ffdf5d 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -392,10 +392,11 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
return dmc_offset;
}
-static u32 parse_csr_fw_dmc(struct intel_csr *csr,
+static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size)
{
+ struct intel_csr *csr = &dev_priv->csr;
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
@@ -440,27 +441,27 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
header_len_bytes = dmc_header->header_len;
dmc_header_size = sizeof(*v1);
} else {
- DRM_ERROR("Unknown DMC fw header version: %u\n",
+ drm_err(&dev_priv->drm, "Unknown DMC fw header version: %u\n",
dmc_header->header_ver);
return 0;
}
if (header_len_bytes != dmc_header_size) {
- DRM_ERROR("DMC firmware has wrong dmc header length "
+ drm_err(&dev_priv->drm, "DMC firmware has wrong dmc header length "
"(%u bytes)\n", header_len_bytes);
return 0;
}
/* Cache the dmc header info. */
if (mmio_count > mmio_count_max) {
- DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
+ drm_err(&dev_priv->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
return 0;
}
for (i = 0; i < mmio_count; i++) {
if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
mmioaddr[i] > CSR_MMIO_END_RANGE) {
- DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
+ drm_err(&dev_priv->drm, "DMC firmware has wrong mmio address 0x%x\n",
mmioaddr[i]);
return 0;
}
@@ -477,14 +478,14 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
goto error_truncated;
if (payload_size > csr->max_fw_size) {
- DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
+ drm_err(&dev_priv->drm, "DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
csr->dmc_fw_size = dmc_header->fw_size;
csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
if (!csr->dmc_payload) {
- DRM_ERROR("Memory allocation failed for dmc payload\n");
+ drm_err(&dev_priv->drm, "Memory allocation failed for dmc payload\n");
return 0;
}
@@ -494,12 +495,12 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
return header_len_bytes + payload_size;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
static u32
-parse_csr_fw_package(struct intel_csr *csr,
+parse_csr_fw_package(struct drm_i915_private *dev_priv,
const struct intel_package_header *package_header,
const struct stepping_info *si,
size_t rem_size)
@@ -516,7 +517,7 @@ parse_csr_fw_package(struct intel_csr *csr,
} else if (package_header->header_ver == 2) {
max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
} else {
- DRM_ERROR("DMC firmware has unknown header version %u\n",
+ drm_err(&dev_priv->drm, "DMC firmware has unknown header version %u\n",
package_header->header_ver);
return 0;
}
@@ -530,7 +531,7 @@ parse_csr_fw_package(struct intel_csr *csr,
goto error_truncated;
if (package_header->header_len * 4 != package_size) {
- DRM_ERROR("DMC firmware has wrong package header length "
+ drm_err(&dev_priv->drm, "DMC firmware has wrong package header length "
"(%u bytes)\n", package_size);
return 0;
}
@@ -544,7 +545,7 @@ parse_csr_fw_package(struct intel_csr *csr,
dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
package_header->header_ver);
if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
- DRM_ERROR("DMC firmware not supported for %c stepping\n",
+ drm_err(&dev_priv->drm, "DMC firmware not supported for %c stepping\n",
si->stepping);
return 0;
}
@@ -553,23 +554,25 @@ parse_csr_fw_package(struct intel_csr *csr,
return package_size + dmc_offset * 4;
error_truncated:
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
/* Return number of bytes parsed or 0 on error */
-static u32 parse_csr_fw_css(struct intel_csr *csr,
+static u32 parse_csr_fw_css(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header,
size_t rem_size)
{
+ struct intel_csr *csr = &dev_priv->csr;
+
if (rem_size < sizeof(struct intel_css_header)) {
- DRM_ERROR("Truncated DMC firmware, refusing.\n");
+ drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
return 0;
}
if (sizeof(struct intel_css_header) !=
(css_header->header_len * 4)) {
- DRM_ERROR("DMC firmware has wrong CSS header length "
+ drm_err(&dev_priv->drm, "DMC firmware has wrong CSS header length "
"(%u bytes)\n",
(css_header->header_len * 4));
return 0;
@@ -577,7 +580,7 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
if (csr->required_version &&
css_header->version != csr->required_version) {
- DRM_INFO("Refusing to load DMC firmware v%u.%u,"
+ drm_info(&dev_priv->drm, "Refusing to load DMC firmware v%u.%u,"
" please use v%u.%u\n",
CSR_VERSION_MAJOR(css_header->version),
CSR_VERSION_MINOR(css_header->version),
@@ -597,7 +600,6 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_csr *csr = &dev_priv->csr;
const struct stepping_info *si = intel_get_stepping_info(dev_priv);
u32 readcount = 0;
u32 r;
@@ -607,7 +609,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract CSS Header information */
css_header = (struct intel_css_header *)fw->data;
- r = parse_csr_fw_css(csr, css_header, fw->size);
+ r = parse_csr_fw_css(dev_priv, css_header, fw->size);
if (!r)
return;
@@ -615,7 +617,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract Package Header information */
package_header = (struct intel_package_header *)&fw->data[readcount];
- r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
+ r = parse_csr_fw_package(dev_priv, package_header, si, fw->size - readcount);
if (!r)
return;
@@ -623,7 +625,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
/* Extract dmc_header information */
dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
- parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
+ parse_csr_fw_dmc(dev_priv, dmc_header, fw->size - readcount);
}
static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
2021-04-28 21:12 ` [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err Anusha Srivatsa
@ 2021-04-28 21:12 ` Anusha Srivatsa
2021-05-03 18:07 ` Jani Nikula
2021-04-28 21:12 ` [Intel-gfx] [PATCH 3/3] drm/i915/csr: Introduce DMC_FW_MAIN Anusha Srivatsa
` (5 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Anusha Srivatsa @ 2021-04-28 21:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
We check for dmc_payload being there at various points in the driver.
Replace it with the helper.
While at it moving bits related to CSR to intel_csr.h
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 13 +++++++----
drivers/gpu/drm/i915/display/intel_csr.h | 23 +++++++++++++++++++
.../drm/i915/display/intel_display_debugfs.c | 4 ++--
.../drm/i915/display/intel_display_power.c | 16 ++++++-------
drivers/gpu/drm/i915/i915_drv.h | 18 +--------------
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
6 files changed, 44 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index bf60c3ffdf5d..66d369ec4f02 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -238,6 +238,11 @@ struct stepping_info {
char substepping;
};
+bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv)
+{
+ return dev_priv->csr.dmc_payload;
+}
+
static const struct stepping_info skl_stepping_info[] = {
{'A', '0'}, {'B', '0'}, {'C', '0'},
{'D', '0'}, {'E', '0'}, {'F', '0'},
@@ -321,7 +326,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!dev_priv->csr.dmc_payload) {
+ if (!intel_csr_has_dmc_payload(dev_priv)) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
@@ -655,7 +660,7 @@ static void csr_load_work_fn(struct work_struct *work)
request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
parse_csr_fw(dev_priv, fw);
- if (dev_priv->csr.dmc_payload) {
+ if (intel_csr_has_dmc_payload(dev_priv)) {
intel_csr_load_program(dev_priv);
intel_csr_runtime_pm_put(dev_priv);
@@ -784,7 +789,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
flush_work(&dev_priv->csr.work);
/* Drop the reference held in case DMC isn't loaded. */
- if (!dev_priv->csr.dmc_payload)
+ if (!intel_csr_has_dmc_payload(dev_priv))
intel_csr_runtime_pm_put(dev_priv);
}
@@ -804,7 +809,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
* Reacquire the reference to keep RPM disabled in case DMC isn't
* loaded.
*/
- if (!dev_priv->csr.dmc_payload)
+ if (!intel_csr_has_dmc_payload(dev_priv))
intel_csr_runtime_pm_get(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
index 03c64f8af7ab..9cab82dfb1ed 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.h
+++ b/drivers/gpu/drm/i915/display/intel_csr.h
@@ -6,6 +6,10 @@
#ifndef __INTEL_CSR_H__
#define __INTEL_CSR_H__
+#include <drm/drm_util.h>
+#include "intel_wakeref.h"
+#include "i915_reg.h"
+
struct drm_i915_private;
#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
@@ -18,4 +22,23 @@ void intel_csr_ucode_fini(struct drm_i915_private *i915);
void intel_csr_ucode_suspend(struct drm_i915_private *i915);
void intel_csr_ucode_resume(struct drm_i915_private *i915);
+struct intel_csr {
+ struct work_struct work;
+ const char *fw_path;
+ u32 required_version;
+ u32 max_fw_size; /* bytes */
+ u32 *dmc_payload;
+ u32 dmc_fw_size; /* dwords */
+ u32 version;
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dc_state;
+ u32 target_dc_state;
+ u32 allowed_dc_mask;
+ intel_wakeref_t wakeref;
+};
+
+bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv);
+
#endif /* __INTEL_CSR_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 183c414d554a..a10c9d4c2536 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -541,10 +541,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
+ seq_printf(m, "fw loaded: %s\n", yesno(intel_csr_has_dmc_payload(dev_priv)));
seq_printf(m, "path: %s\n", csr->fw_path);
- if (!csr->dmc_payload)
+ if (!intel_csr_has_dmc_payload(dev_priv))
goto out;
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index d48dd15a4f6e..6a9d99b80755 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1219,7 +1219,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if (!dev_priv->csr.dmc_payload)
+ if (!intel_csr_has_dmc_payload(dev_priv))
return;
switch (dev_priv->csr.target_dc_state) {
@@ -5150,7 +5150,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && intel_csr_has_dmc_payload(dev_priv))
intel_csr_load_program(dev_priv);
}
@@ -5217,7 +5217,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && intel_csr_has_dmc_payload(dev_priv))
intel_csr_load_program(dev_priv);
}
@@ -5283,7 +5283,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && intel_csr_has_dmc_payload(dev_priv))
intel_csr_load_program(dev_priv);
}
@@ -5440,7 +5440,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12)
tgl_bw_buddy_init(dev_priv);
- if (resume && dev_priv->csr.dmc_payload)
+ if (resume && intel_csr_has_dmc_payload(dev_priv))
intel_csr_load_program(dev_priv);
/* Wa_14011508470 */
@@ -5797,7 +5797,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
- i915->csr.dmc_payload) {
+ intel_csr_has_dmc_payload(i915)) {
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
return;
@@ -5987,7 +5987,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) >= 11) {
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
- if (i915->csr.dmc_payload) {
+ if (intel_csr_has_dmc_payload(i915)) {
if (i915->csr.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
@@ -5998,7 +5998,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
- if (i915->csr.dmc_payload &&
+ if (intel_csr_has_dmc_payload(i915) &&
(i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 336b09f38aad..50f32d89e175 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -74,6 +74,7 @@
#include "display/intel_global_state.h"
#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
+#include "display/intel_csr.h"
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_shrinker.h"
@@ -329,23 +330,6 @@ struct drm_i915_display_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
-struct intel_csr {
- struct work_struct work;
- const char *fw_path;
- u32 required_version;
- u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
- u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
- u32 dc_state;
- u32 target_dc_state;
- u32 allowed_dc_mask;
- intel_wakeref_t wakeref;
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index bb181fe5d47e..cbf485e8510a 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -793,7 +793,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
struct intel_csr *csr = &m->i915->csr;
err_printf(m, "DMC loaded: %s\n",
- yesno(csr->dmc_payload != NULL));
+ yesno(intel_csr_has_dmc_payload(m->i915) != 0));
err_printf(m, "DMC fw version: %d.%d\n",
CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/csr: Introduce DMC_FW_MAIN
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
2021-04-28 21:12 ` [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err Anusha Srivatsa
2021-04-28 21:12 ` [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper Anusha Srivatsa
@ 2021-04-28 21:12 ` Anusha Srivatsa
2021-04-28 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Prep patches Patchwork
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Anusha Srivatsa @ 2021-04-28 21:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi
This is a prep patch for Pipe DMC plugging.
Add dmc_info struct in intel_csr, to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/intel_csr.c | 43 ++++++++++--------------
drivers/gpu/drm/i915/display/intel_csr.h | 20 ++++++++---
2 files changed, 33 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index 66d369ec4f02..10cf7fb955d8 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -240,7 +240,7 @@ struct stepping_info {
bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv)
{
- return dev_priv->csr.dmc_payload;
+ return dev_priv->csr.dmc_info[DMC_FW_MAIN].payload;
}
static const struct stepping_info skl_stepping_info[] = {
@@ -317,7 +317,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
*/
void intel_csr_load_program(struct drm_i915_private *dev_priv)
{
- u32 *payload = dev_priv->csr.dmc_payload;
+ struct intel_csr *csr = &dev_priv->csr;
+ struct dmc_fw_info *dmc_info = &csr->dmc_info[DMC_FW_MAIN];
u32 i, fw_size;
if (!HAS_CSR(dev_priv)) {
@@ -326,26 +327,26 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
return;
}
- if (!intel_csr_has_dmc_payload(dev_priv)) {
+ if (!dev_priv->csr.dmc_info[DMC_FW_MAIN].payload) {
drm_err(&dev_priv->drm,
"Tried to program CSR with empty payload\n");
return;
}
- fw_size = dev_priv->csr.dmc_fw_size;
+ fw_size = dmc_info->dmc_fw_size;
assert_rpm_wakelock_held(&dev_priv->runtime_pm);
preempt_disable();
for (i = 0; i < fw_size; i++)
intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
- payload[i]);
+ dmc_info->payload[i]);
preempt_enable();
- for (i = 0; i < dev_priv->csr.mmio_count; i++) {
- intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
- dev_priv->csr.mmiodata[i]);
+ for (i = 0; i < dmc_info->mmio_count; i++) {
+ intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+ dmc_info->mmiodata[i]);
}
dev_priv->csr.dc_state = 0;
@@ -402,14 +403,12 @@ static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
size_t rem_size)
{
struct intel_csr *csr = &dev_priv->csr;
+ struct dmc_fw_info *dmc_info = &csr->dmc_info[DMC_FW_MAIN];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
u32 mmio_count, mmio_count_max;
u8 *payload;
- BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
- ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
-
/*
* Check if we can access common fields, we will checkc again below
* after we have read the version
@@ -464,16 +463,10 @@ static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
}
for (i = 0; i < mmio_count; i++) {
- if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
- mmioaddr[i] > CSR_MMIO_END_RANGE) {
- drm_err(&dev_priv->drm, "DMC firmware has wrong mmio address 0x%x\n",
- mmioaddr[i]);
- return 0;
- }
- csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
- csr->mmiodata[i] = mmiodata[i];
+ dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+ dmc_info->mmiodata[i] = mmiodata[i];
}
- csr->mmio_count = mmio_count;
+ dmc_info->mmio_count = mmio_count;
rem_size -= header_len_bytes;
@@ -486,16 +479,16 @@ static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
drm_err(&dev_priv->drm, "DMC FW too big (%u bytes)\n", payload_size);
return 0;
}
- csr->dmc_fw_size = dmc_header->fw_size;
+ dmc_info->dmc_fw_size = dmc_header->fw_size;
- csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
- if (!csr->dmc_payload) {
+ dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+ if (!dmc_info->payload) {
drm_err(&dev_priv->drm, "Memory allocation failed for dmc payload\n");
return 0;
}
payload = (u8 *)(dmc_header) + header_len_bytes;
- memcpy(csr->dmc_payload, payload, payload_size);
+ memcpy(dmc_info->payload, payload, payload_size);
return header_len_bytes + payload_size;
@@ -828,5 +821,5 @@ void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
intel_csr_ucode_suspend(dev_priv);
drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
- kfree(dev_priv->csr.dmc_payload);
+ kfree(dev_priv->csr.dmc_info[DMC_FW_MAIN].payload);
}
diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
index 9cab82dfb1ed..2a03e7de0db0 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.h
+++ b/drivers/gpu/drm/i915/display/intel_csr.h
@@ -22,17 +22,27 @@ void intel_csr_ucode_fini(struct drm_i915_private *i915);
void intel_csr_ucode_suspend(struct drm_i915_private *i915);
void intel_csr_ucode_resume(struct drm_i915_private *i915);
+enum {
+ DMC_FW_MAIN = 0,
+ DMC_FW_MAX
+};
+
struct intel_csr {
struct work_struct work;
const char *fw_path;
u32 required_version;
u32 max_fw_size; /* bytes */
- u32 *dmc_payload;
- u32 dmc_fw_size; /* dwords */
u32 version;
- u32 mmio_count;
- i915_reg_t mmioaddr[20];
- u32 mmiodata[20];
+ struct dmc_fw_info {
+ u32 mmio_count;
+ i915_reg_t mmioaddr[20];
+ u32 mmiodata[20];
+ u32 dmc_offset;
+ u32 start_mmioaddr;
+ u32 dmc_fw_size; /*dwords */
+ u32 *payload;
+ } dmc_info[DMC_FW_MAX];
+
u32 dc_state;
u32 target_dc_state;
u32 allowed_dc_mask;
--
2.25.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Prep patches
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
` (2 preceding siblings ...)
2021-04-28 21:12 ` [Intel-gfx] [PATCH 3/3] drm/i915/csr: Introduce DMC_FW_MAIN Anusha Srivatsa
@ 2021-04-28 21:44 ` Patchwork
2021-04-28 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-04-28 21:44 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Pipe DMC Prep patches
URL : https://patchwork.freedesktop.org/series/89602/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
32def90ad84d drm/i915/csr: s/DRM_ERROR/drm_err
-:38: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#38: FILE: drivers/gpu/drm/i915/display/intel_csr.c:445:
+ drm_err(&dev_priv->drm, "Unknown DMC fw header version: %u\n",
dmc_header->header_ver);
-:61: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#61: FILE: drivers/gpu/drm/i915/display/intel_csr.c:465:
+ drm_err(&dev_priv->drm, "DMC firmware has wrong mmio address 0x%x\n",
mmioaddr[i]);
-:77: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#77: FILE: drivers/gpu/drm/i915/display/intel_csr.c:488:
if (!csr->dmc_payload) {
+ drm_err(&dev_priv->drm, "Memory allocation failed for dmc payload\n");
-:102: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#102: FILE: drivers/gpu/drm/i915/display/intel_csr.c:521:
+ drm_err(&dev_priv->drm, "DMC firmware has unknown header version %u\n",
package_header->header_ver);
-:120: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#120: FILE: drivers/gpu/drm/i915/display/intel_csr.c:549:
+ drm_err(&dev_priv->drm, "DMC firmware not supported for %c stepping\n",
si->stepping);
total: 0 errors, 1 warnings, 4 checks, 165 lines checked
07e44e7c8997 drm/i915/csr: Add intel_csr_has_dmc_payload() helper
b18fa946a9e4 drm/i915/csr: Introduce DMC_FW_MAIN
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Pipe DMC Prep patches
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
` (3 preceding siblings ...)
2021-04-28 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Prep patches Patchwork
@ 2021-04-28 21:46 ` Patchwork
2021-04-28 22:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-04-28 21:46 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: Pipe DMC Prep patches
URL : https://patchwork.freedesktop.org/series/89602/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/gvt/mmio.c:295:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Pipe DMC Prep patches
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
` (4 preceding siblings ...)
2021-04-28 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-04-28 22:15 ` Patchwork
2021-04-28 23:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-03 18:12 ` [Intel-gfx] [PATCH 0/3] " Jani Nikula
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-04-28 22:15 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 2449 bytes --]
== Series Details ==
Series: Pipe DMC Prep patches
URL : https://patchwork.freedesktop.org/series/89602/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10023 -> Patchwork_20020
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/index.html
Known issues
------------
Here are the changes found in Patchwork_20020 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-u2: [PASS][1] -> [FAIL][2] ([i915#1888])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/fi-tgl-u2/igt@gem_exec_suspend@basic-s3.html
#### Possible fixes ####
* igt@kms_frontbuffer_tracking@basic:
- {fi-rkl-11500t}: [SKIP][3] ([i915#1849] / [i915#3180]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/fi-rkl-11500t/igt@kms_frontbuffer_tracking@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#3180]: https://gitlab.freedesktop.org/drm/intel/issues/3180
Participating hosts (44 -> 39)
------------------------------
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10023 -> Patchwork_20020
CI-20190529: 20190529
CI_DRM_10023: a8bf9e284933fa5c1cb821b48ba95821e5d1cc3f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6076: 9ab0820dbd07781161c1ace6973ea222fd24e53a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20020: b18fa946a9e4a19fdeb77189cf1c9d8c18db50bc @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b18fa946a9e4 drm/i915/csr: Introduce DMC_FW_MAIN
07e44e7c8997 drm/i915/csr: Add intel_csr_has_dmc_payload() helper
32def90ad84d drm/i915/csr: s/DRM_ERROR/drm_err
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/index.html
[-- Attachment #1.2: Type: text/html, Size: 3086 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Pipe DMC Prep patches
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
` (5 preceding siblings ...)
2021-04-28 22:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-04-28 23:34 ` Patchwork
2021-05-03 18:12 ` [Intel-gfx] [PATCH 0/3] " Jani Nikula
7 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-04-28 23:34 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30244 bytes --]
== Series Details ==
Series: Pipe DMC Prep patches
URL : https://patchwork.freedesktop.org/series/89602/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10023_full -> Patchwork_20020_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_20020_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_mm@all@insert:
- shard-skl: [PASS][1] -> [INCOMPLETE][2] ([i915#2485] / [i915#2502])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl7/igt@drm_mm@all@insert.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl2/igt@drm_mm@all@insert.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb2/igt@gem_create@create-massive.html
- shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#3002])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@gem_create@create-massive.html
- shard-skl: NOTRUN -> [DMESG-WARN][5] ([i915#3002])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@clone:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb2/igt@gem_ctx_persistence@clone.html
* igt@gem_ctx_shared@q-in-order:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271]) +272 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb7/igt@gem_ctx_shared@q-in-order.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#2481] / [i915#3070])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb8/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@vecs0:
- shard-skl: NOTRUN -> [INCOMPLETE][10] ([i915#198] / [i915#2624])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl6/igt@gem_exec_capture@pi@vecs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][11] ([i915#2846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][12] -> [FAIL][13] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-glk2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][14] ([i915#2842]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#2842]) +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_mmap_gtt@cpuset-big-copy:
- shard-glk: [PASS][17] -> [FAIL][18] ([i915#307])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-glk4/igt@gem_mmap_gtt@cpuset-big-copy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-glk4/igt@gem_mmap_gtt@cpuset-big-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-snb: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][21] ([i915#3318])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl2/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@bb-large:
- shard-apl: NOTRUN -> [FAIL][22] ([i915#3296])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@gen9_exec_parse@bb-large.html
* igt@i915_module_load@reload:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1982]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl8/igt@i915_module_load@reload.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl8/igt@i915_module_load@reload.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][25] ([i915#1886] / [i915#2291])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_joiner@basic:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#2705])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl2/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_chamelium@dp-mode-timings:
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +28 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl2/igt@kms_chamelium@dp-mode-timings.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-snb: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +16 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb7/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-d-degamma:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_color_chamelium@pipe-d-degamma.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][31] ([i915#2105])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl4/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][32] -> [DMESG-WARN][33] ([i915#180]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#79])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][36] ([i915#180]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-skl: [PASS][37] -> [INCOMPLETE][38] ([i915#198] / [i915#1982])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl2/igt@kms_flip@flip-vs-suspend@a-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl5/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][39] -> [FAIL][40] ([i915#2122])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#2642])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#2672])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#2672])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271]) +97 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271]) +62 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#49])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][48] -> [FAIL][49] ([i915#1188])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl7/igt@kms_hdr@bpc-switch.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl2/igt@kms_hdr@bpc-switch.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: NOTRUN -> [FAIL][50] ([i915#1188])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl4/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#533]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +3 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
- shard-kbl: NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][56] ([i915#265])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +7 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][59] -> [SKIP][60] ([fdo#109642] / [fdo#111068] / [i915#658])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb7/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr2_su@page_flip:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl6/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][62] -> [SKIP][63] ([fdo#109441]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271]) +311 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl8/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@kms_writeback@writeback-fb-id:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2437])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl2/igt@kms_writeback@writeback-fb-id.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2437])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_writeback@writeback-invalid-parameters.html
- shard-kbl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@kms_writeback@writeback-invalid-parameters.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2994]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl1/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2994]) +4 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl7/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_create@create-clear:
- shard-iclb: [FAIL][71] ([i915#3160]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb1/igt@gem_create@create-clear.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb5/igt@gem_create@create-clear.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][73] ([i915#2842]) -> [PASS][74] +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][75] ([i915#2842]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][79] ([i915#2849]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-glk: [FAIL][81] ([i915#307]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-glk4/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-glk6/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][83] ([i915#2782]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-snb6/igt@i915_selftest@live@hangcheck.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][85] ([i915#180]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][87] ([i915#79]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][89] ([i915#180]) -> [PASS][90] +8 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][91] ([i915#2122]) -> [PASS][92] +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][93] ([i915#1188]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][95] ([fdo#108145] / [i915#265]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [SKIP][97] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb8/igt@kms_psr2_su@page_flip.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb2/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_blt:
- shard-iclb: [SKIP][99] ([fdo#109441]) -> [PASS][100] +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb8/igt@kms_psr@psr2_primary_blt.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-a:
- shard-skl: [DMESG-WARN][101] ([i915#1982]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl3/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl10/igt@kms_universal_plane@universal-plane-gen9-features-pipe-a.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][103] ([i915#2684]) -> [WARN][104] ([i915#1804] / [i915#2684])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][105] ([i915#2684]) -> [WARN][106] ([i915#2681] / [i915#2684])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-iclb: [SKIP][107] ([i915#658]) -> [SKIP][108] ([i915#2920])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb4/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-iclb: [SKIP][109] ([i915#2920]) -> [SKIP][110] ([i915#658]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-iclb1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][111], [FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#602] / [i915#92]) -> ([FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2292] / [i915#2505] / [i915#3002] / [i915#92])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl3/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl3/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl7/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl1/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl6/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl4/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-kbl4/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl7/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl6/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl7/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-kbl3/igt@runner@aborted.html
- shard-skl: ([FAIL][131], [FAIL][132]) ([i915#2029] / [i915#3002]) -> ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1814] / [i915#2029] / [i915#2485] / [i915#3002])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl3/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10023/shard-skl3/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl8/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl2/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl2/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl4/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl5/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/shard-skl3/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2105]: https://gitlab.freedesktop.org/drm/intel/issues/2105
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2369]: https://gitlab.freedesktop.org/drm/intel/issues/2369
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2481]: https://gitlab.freedesktop.org/drm/intel/issues/2481
[i915#2485]: https://gitlab.freedesktop.org/drm/intel/issues/2485
[i915#2502]: https://gitlab.freedesktop.org/drm/intel/issues/2502
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2624]: https://gitlab.freedesktop.org/drm/intel/issues/2624
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3160]: https://gitlab.freedesktop.org/drm/intel/issues/3160
[i915#3296]: https://gitlab.freedesktop.org/drm/intel/issues/3296
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
---
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20020/index.html
[-- Attachment #1.2: Type: text/html, Size: 38690 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err
2021-04-28 21:12 ` [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err Anusha Srivatsa
@ 2021-05-03 18:03 ` Jani Nikula
2021-05-03 21:45 ` Srivatsa, Anusha
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2021-05-03 18:03 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Lucas De Marchi
On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> Use new format of debug messages across intel_csr.
>
> While at it, change some function definitions which now
> need dev_priv for drm_err and drm_info etc.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_csr.c | 44 +++++++++++++-----------
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
> index 26a922d34263..bf60c3ffdf5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -392,10 +392,11 @@ static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
> return dmc_offset;
> }
>
> -static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> +static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
All new struct drm_i915_private * should be named i915, not dev_priv.
> const struct intel_dmc_header_base *dmc_header,
> size_t rem_size)
> {
> + struct intel_csr *csr = &dev_priv->csr;
You could also use container_of() to get from the csr to the i915
pointer. No need to add or change params.
> unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> const u32 *mmioaddr, *mmiodata;
> u32 mmio_count, mmio_count_max;
> @@ -440,27 +441,27 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> header_len_bytes = dmc_header->header_len;
> dmc_header_size = sizeof(*v1);
> } else {
> - DRM_ERROR("Unknown DMC fw header version: %u\n",
> + drm_err(&dev_priv->drm, "Unknown DMC fw header version: %u\n",
> dmc_header->header_ver);
Please fix indentation. Same for all changes below.
> return 0;
> }
>
> if (header_len_bytes != dmc_header_size) {
> - DRM_ERROR("DMC firmware has wrong dmc header length "
> + drm_err(&dev_priv->drm, "DMC firmware has wrong dmc header length "
> "(%u bytes)\n", header_len_bytes);
> return 0;
> }
>
> /* Cache the dmc header info. */
> if (mmio_count > mmio_count_max) {
> - DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
> + drm_err(&dev_priv->drm, "DMC firmware has wrong mmio count %u\n", mmio_count);
> return 0;
> }
>
> for (i = 0; i < mmio_count; i++) {
> if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
> mmioaddr[i] > CSR_MMIO_END_RANGE) {
> - DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
> + drm_err(&dev_priv->drm, "DMC firmware has wrong mmio address 0x%x\n",
> mmioaddr[i]);
> return 0;
> }
> @@ -477,14 +478,14 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> goto error_truncated;
>
> if (payload_size > csr->max_fw_size) {
> - DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
> + drm_err(&dev_priv->drm, "DMC FW too big (%u bytes)\n", payload_size);
> return 0;
> }
> csr->dmc_fw_size = dmc_header->fw_size;
>
> csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
> if (!csr->dmc_payload) {
> - DRM_ERROR("Memory allocation failed for dmc payload\n");
> + drm_err(&dev_priv->drm, "Memory allocation failed for dmc payload\n");
> return 0;
> }
>
> @@ -494,12 +495,12 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> return header_len_bytes + payload_size;
>
> error_truncated:
> - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> + drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> static u32
> -parse_csr_fw_package(struct intel_csr *csr,
> +parse_csr_fw_package(struct drm_i915_private *dev_priv,
> const struct intel_package_header *package_header,
> const struct stepping_info *si,
> size_t rem_size)
> @@ -516,7 +517,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> } else if (package_header->header_ver == 2) {
> max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
> } else {
> - DRM_ERROR("DMC firmware has unknown header version %u\n",
> + drm_err(&dev_priv->drm, "DMC firmware has unknown header version %u\n",
> package_header->header_ver);
> return 0;
> }
> @@ -530,7 +531,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> goto error_truncated;
>
> if (package_header->header_len * 4 != package_size) {
> - DRM_ERROR("DMC firmware has wrong package header length "
> + drm_err(&dev_priv->drm, "DMC firmware has wrong package header length "
> "(%u bytes)\n", package_size);
> return 0;
> }
> @@ -544,7 +545,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
> package_header->header_ver);
> if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
> - DRM_ERROR("DMC firmware not supported for %c stepping\n",
> + drm_err(&dev_priv->drm, "DMC firmware not supported for %c stepping\n",
> si->stepping);
> return 0;
> }
> @@ -553,23 +554,25 @@ parse_csr_fw_package(struct intel_csr *csr,
> return package_size + dmc_offset * 4;
>
> error_truncated:
> - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> + drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> /* Return number of bytes parsed or 0 on error */
> -static u32 parse_csr_fw_css(struct intel_csr *csr,
> +static u32 parse_csr_fw_css(struct drm_i915_private *dev_priv,
> struct intel_css_header *css_header,
> size_t rem_size)
> {
> + struct intel_csr *csr = &dev_priv->csr;
> +
> if (rem_size < sizeof(struct intel_css_header)) {
> - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> + drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
> return 0;
> }
>
> if (sizeof(struct intel_css_header) !=
> (css_header->header_len * 4)) {
> - DRM_ERROR("DMC firmware has wrong CSS header length "
> + drm_err(&dev_priv->drm, "DMC firmware has wrong CSS header length "
> "(%u bytes)\n",
> (css_header->header_len * 4));
> return 0;
> @@ -577,7 +580,7 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
>
> if (csr->required_version &&
> css_header->version != csr->required_version) {
> - DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> + drm_info(&dev_priv->drm, "Refusing to load DMC firmware v%u.%u,"
> " please use v%u.%u\n",
> CSR_VERSION_MAJOR(css_header->version),
> CSR_VERSION_MINOR(css_header->version),
> @@ -597,7 +600,6 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
> struct intel_css_header *css_header;
> struct intel_package_header *package_header;
> struct intel_dmc_header_base *dmc_header;
> - struct intel_csr *csr = &dev_priv->csr;
> const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> u32 readcount = 0;
> u32 r;
> @@ -607,7 +609,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract CSS Header information */
> css_header = (struct intel_css_header *)fw->data;
> - r = parse_csr_fw_css(csr, css_header, fw->size);
> + r = parse_csr_fw_css(dev_priv, css_header, fw->size);
> if (!r)
> return;
>
> @@ -615,7 +617,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract Package Header information */
> package_header = (struct intel_package_header *)&fw->data[readcount];
> - r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
> + r = parse_csr_fw_package(dev_priv, package_header, si, fw->size - readcount);
> if (!r)
> return;
>
> @@ -623,7 +625,7 @@ static void parse_csr_fw(struct drm_i915_private *dev_priv,
>
> /* Extract dmc_header information */
> dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
> - parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
> + parse_csr_fw_dmc(dev_priv, dmc_header, fw->size - readcount);
> }
>
> static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper
2021-04-28 21:12 ` [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper Anusha Srivatsa
@ 2021-05-03 18:07 ` Jani Nikula
2021-05-03 21:50 ` Srivatsa, Anusha
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2021-05-03 18:07 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Lucas De Marchi
On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> We check for dmc_payload being there at various points in the driver.
> Replace it with the helper.
Yes please!
>
> While at it moving bits related to CSR to intel_csr.h
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_csr.c | 13 +++++++----
> drivers/gpu/drm/i915/display/intel_csr.h | 23 +++++++++++++++++++
> .../drm/i915/display/intel_display_debugfs.c | 4 ++--
> .../drm/i915/display/intel_display_power.c | 16 ++++++-------
> drivers/gpu/drm/i915/i915_drv.h | 18 +--------------
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> 6 files changed, 44 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
> index bf60c3ffdf5d..66d369ec4f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -238,6 +238,11 @@ struct stepping_info {
> char substepping;
> };
>
> +bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv)
s/dev_priv/i915/g
> +{
> + return dev_priv->csr.dmc_payload;
> +}
> +
> static const struct stepping_info skl_stepping_info[] = {
> {'A', '0'}, {'B', '0'}, {'C', '0'},
> {'D', '0'}, {'E', '0'}, {'F', '0'},
> @@ -321,7 +326,7 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
> return;
> }
>
> - if (!dev_priv->csr.dmc_payload) {
> + if (!intel_csr_has_dmc_payload(dev_priv)) {
> drm_err(&dev_priv->drm,
> "Tried to program CSR with empty payload\n");
> return;
> @@ -655,7 +660,7 @@ static void csr_load_work_fn(struct work_struct *work)
> request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
> parse_csr_fw(dev_priv, fw);
>
> - if (dev_priv->csr.dmc_payload) {
> + if (intel_csr_has_dmc_payload(dev_priv)) {
> intel_csr_load_program(dev_priv);
> intel_csr_runtime_pm_put(dev_priv);
>
> @@ -784,7 +789,7 @@ void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
> flush_work(&dev_priv->csr.work);
>
> /* Drop the reference held in case DMC isn't loaded. */
> - if (!dev_priv->csr.dmc_payload)
> + if (!intel_csr_has_dmc_payload(dev_priv))
> intel_csr_runtime_pm_put(dev_priv);
> }
>
> @@ -804,7 +809,7 @@ void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
> * Reacquire the reference to keep RPM disabled in case DMC isn't
> * loaded.
> */
> - if (!dev_priv->csr.dmc_payload)
> + if (!intel_csr_has_dmc_payload(dev_priv))
> intel_csr_runtime_pm_get(dev_priv);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h
> index 03c64f8af7ab..9cab82dfb1ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.h
> +++ b/drivers/gpu/drm/i915/display/intel_csr.h
> @@ -6,6 +6,10 @@
> #ifndef __INTEL_CSR_H__
> #define __INTEL_CSR_H__
>
> +#include <drm/drm_util.h>
What for?
You'll need <linux/types.h>.
We may want to consider having split interface and types headers... but
maybe later.
> +#include "intel_wakeref.h"
> +#include "i915_reg.h"
> +
> struct drm_i915_private;
>
> #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
> @@ -18,4 +22,23 @@ void intel_csr_ucode_fini(struct drm_i915_private *i915);
> void intel_csr_ucode_suspend(struct drm_i915_private *i915);
> void intel_csr_ucode_resume(struct drm_i915_private *i915);
>
> +struct intel_csr {
> + struct work_struct work;
> + const char *fw_path;
> + u32 required_version;
> + u32 max_fw_size; /* bytes */
> + u32 *dmc_payload;
> + u32 dmc_fw_size; /* dwords */
> + u32 version;
> + u32 mmio_count;
> + i915_reg_t mmioaddr[20];
> + u32 mmiodata[20];
> + u32 dc_state;
> + u32 target_dc_state;
> + u32 allowed_dc_mask;
> + intel_wakeref_t wakeref;
> +};
> +
> +bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv);
> +
> #endif /* __INTEL_CSR_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 183c414d554a..a10c9d4c2536 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -541,10 +541,10 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>
> - seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
> + seq_printf(m, "fw loaded: %s\n", yesno(intel_csr_has_dmc_payload(dev_priv)));
> seq_printf(m, "path: %s\n", csr->fw_path);
>
> - if (!csr->dmc_payload)
> + if (!intel_csr_has_dmc_payload(dev_priv))
> goto out;
>
> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index d48dd15a4f6e..6a9d99b80755 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1219,7 +1219,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
> static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if (!dev_priv->csr.dmc_payload)
> + if (!intel_csr_has_dmc_payload(dev_priv))
> return;
>
> switch (dev_priv->csr.target_dc_state) {
> @@ -5150,7 +5150,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
>
> gen9_dbuf_enable(dev_priv);
>
> - if (resume && dev_priv->csr.dmc_payload)
> + if (resume && intel_csr_has_dmc_payload(dev_priv))
> intel_csr_load_program(dev_priv);
> }
>
> @@ -5217,7 +5217,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> gen9_dbuf_enable(dev_priv);
>
> - if (resume && dev_priv->csr.dmc_payload)
> + if (resume && intel_csr_has_dmc_payload(dev_priv))
> intel_csr_load_program(dev_priv);
> }
>
> @@ -5283,7 +5283,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
>
> - if (resume && dev_priv->csr.dmc_payload)
> + if (resume && intel_csr_has_dmc_payload(dev_priv))
> intel_csr_load_program(dev_priv);
> }
>
> @@ -5440,7 +5440,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> if (DISPLAY_VER(dev_priv) >= 12)
> tgl_bw_buddy_init(dev_priv);
>
> - if (resume && dev_priv->csr.dmc_payload)
> + if (resume && intel_csr_has_dmc_payload(dev_priv))
> intel_csr_load_program(dev_priv);
>
> /* Wa_14011508470 */
> @@ -5797,7 +5797,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
> */
> if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
> suspend_mode == I915_DRM_SUSPEND_IDLE &&
> - i915->csr.dmc_payload) {
> + intel_csr_has_dmc_payload(i915)) {
> intel_display_power_flush_work(i915);
> intel_power_domains_verify_state(i915);
> return;
> @@ -5987,7 +5987,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
> if (DISPLAY_VER(i915) >= 11) {
> bxt_disable_dc9(i915);
> icl_display_core_init(i915, true);
> - if (i915->csr.dmc_payload) {
> + if (intel_csr_has_dmc_payload(i915)) {
> if (i915->csr.allowed_dc_mask &
> DC_STATE_EN_UPTO_DC6)
> skl_enable_dc6(i915);
> @@ -5998,7 +5998,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> bxt_disable_dc9(i915);
> bxt_display_core_init(i915, true);
> - if (i915->csr.dmc_payload &&
> + if (intel_csr_has_dmc_payload(i915) &&
> (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> gen9_enable_dc5(i915);
> } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 336b09f38aad..50f32d89e175 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -74,6 +74,7 @@
> #include "display/intel_global_state.h"
> #include "display/intel_gmbus.h"
> #include "display/intel_opregion.h"
> +#include "display/intel_csr.h"
>
> #include "gem/i915_gem_context_types.h"
> #include "gem/i915_gem_shrinker.h"
> @@ -329,23 +330,6 @@ struct drm_i915_display_funcs {
> void (*read_luts)(struct intel_crtc_state *crtc_state);
> };
>
> -struct intel_csr {
> - struct work_struct work;
> - const char *fw_path;
> - u32 required_version;
> - u32 max_fw_size; /* bytes */
> - u32 *dmc_payload;
> - u32 dmc_fw_size; /* dwords */
> - u32 version;
> - u32 mmio_count;
> - i915_reg_t mmioaddr[20];
> - u32 mmiodata[20];
> - u32 dc_state;
> - u32 target_dc_state;
> - u32 allowed_dc_mask;
> - intel_wakeref_t wakeref;
> -};
> -
> enum i915_cache_level {
> I915_CACHE_NONE = 0,
> I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index bb181fe5d47e..cbf485e8510a 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -793,7 +793,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
> struct intel_csr *csr = &m->i915->csr;
>
> err_printf(m, "DMC loaded: %s\n",
> - yesno(csr->dmc_payload != NULL));
> + yesno(intel_csr_has_dmc_payload(m->i915) != 0));
> err_printf(m, "DMC fw version: %d.%d\n",
> CSR_VERSION_MAJOR(csr->version),
> CSR_VERSION_MINOR(csr->version));
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
` (6 preceding siblings ...)
2021-04-28 23:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2021-05-03 18:12 ` Jani Nikula
2021-05-05 6:40 ` Jani Nikula
7 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2021-05-03 18:12 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> This series adds the prep work needed before the
> actual Pipe DMC implementation.
When should we rename csr to dmc all over the place?
BR,
Jani.
>
> Anusha Srivatsa (3):
> drm/i915/csr: s/DRM_ERROR/drm_err
> drm/i915/csr: Add intel_csr_has_dmc_payload() helper
> drm/i915/csr: Introduce DMC_FW_MAIN
>
> drivers/gpu/drm/i915/display/intel_csr.c | 94 +++++++++----------
> drivers/gpu/drm/i915/display/intel_csr.h | 33 +++++++
> .../drm/i915/display/intel_display_debugfs.c | 4 +-
> .../drm/i915/display/intel_display_power.c | 16 ++--
> drivers/gpu/drm/i915/i915_drv.h | 18 +---
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> 6 files changed, 92 insertions(+), 75 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err
2021-05-03 18:03 ` Jani Nikula
@ 2021-05-03 21:45 ` Srivatsa, Anusha
0 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2021-05-03 21:45 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, May 3, 2021 11:04 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err
>
> On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > Use new format of debug messages across intel_csr.
> >
> > While at it, change some function definitions which now need dev_priv
> > for drm_err and drm_info etc.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Suggested-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_csr.c | 44
> > +++++++++++++-----------
> > 1 file changed, 23 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
> > b/drivers/gpu/drm/i915/display/intel_csr.c
> > index 26a922d34263..bf60c3ffdf5d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> > @@ -392,10 +392,11 @@ static u32 find_dmc_fw_offset(const struct
> intel_fw_info *fw_info,
> > return dmc_offset;
> > }
> >
> > -static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> > +static u32 parse_csr_fw_dmc(struct drm_i915_private *dev_priv,
>
> All new struct drm_i915_private * should be named i915, not dev_priv.
I will change it.
>
> > const struct intel_dmc_header_base
> *dmc_header,
> > size_t rem_size)
> > {
> > + struct intel_csr *csr = &dev_priv->csr;
>
> You could also use container_of() to get from the csr to the i915 pointer. No
> need to add or change params.
Makes sense. I will add the changes in the next version.
> > unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> > const u32 *mmioaddr, *mmiodata;
> > u32 mmio_count, mmio_count_max;
> > @@ -440,27 +441,27 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> > header_len_bytes = dmc_header->header_len;
> > dmc_header_size = sizeof(*v1);
> > } else {
> > - DRM_ERROR("Unknown DMC fw header version: %u\n",
> > + drm_err(&dev_priv->drm, "Unknown DMC fw header
> version: %u\n",
> > dmc_header->header_ver);
>
> Please fix indentation. Same for all changes below.
I will take a look at the indentation.
Thanks,
Anusha
> > return 0;
> > }
> >
> > if (header_len_bytes != dmc_header_size) {
> > - DRM_ERROR("DMC firmware has wrong dmc header length "
> > + drm_err(&dev_priv->drm, "DMC firmware has wrong dmc
> header length "
> > "(%u bytes)\n", header_len_bytes);
> > return 0;
> > }
> >
> > /* Cache the dmc header info. */
> > if (mmio_count > mmio_count_max) {
> > - DRM_ERROR("DMC firmware has wrong mmio count %u\n",
> mmio_count);
> > + drm_err(&dev_priv->drm, "DMC firmware has wrong mmio
> count %u\n",
> > +mmio_count);
> > return 0;
> > }
> >
> > for (i = 0; i < mmio_count; i++) {
> > if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
> > mmioaddr[i] > CSR_MMIO_END_RANGE) {
> > - DRM_ERROR("DMC firmware has wrong mmio
> address 0x%x\n",
> > + drm_err(&dev_priv->drm, "DMC firmware has wrong
> mmio address
> > +0x%x\n",
> > mmioaddr[i]);
> > return 0;
> > }
> > @@ -477,14 +478,14 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> > goto error_truncated;
> >
> > if (payload_size > csr->max_fw_size) {
> > - DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
> > + drm_err(&dev_priv->drm, "DMC FW too big (%u bytes)\n",
> > +payload_size);
> > return 0;
> > }
> > csr->dmc_fw_size = dmc_header->fw_size;
> >
> > csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
> > if (!csr->dmc_payload) {
> > - DRM_ERROR("Memory allocation failed for dmc payload\n");
> > + drm_err(&dev_priv->drm, "Memory allocation failed for dmc
> > +payload\n");
> > return 0;
> > }
> >
> > @@ -494,12 +495,12 @@ static u32 parse_csr_fw_dmc(struct intel_csr *csr,
> > return header_len_bytes + payload_size;
> >
> > error_truncated:
> > - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> > + drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
> > return 0;
> > }
> >
> > static u32
> > -parse_csr_fw_package(struct intel_csr *csr,
> > +parse_csr_fw_package(struct drm_i915_private *dev_priv,
> > const struct intel_package_header *package_header,
> > const struct stepping_info *si,
> > size_t rem_size)
> > @@ -516,7 +517,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> > } else if (package_header->header_ver == 2) {
> > max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
> > } else {
> > - DRM_ERROR("DMC firmware has unknown header version
> %u\n",
> > + drm_err(&dev_priv->drm, "DMC firmware has unknown
> header version
> > +%u\n",
> > package_header->header_ver);
> > return 0;
> > }
> > @@ -530,7 +531,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> > goto error_truncated;
> >
> > if (package_header->header_len * 4 != package_size) {
> > - DRM_ERROR("DMC firmware has wrong package header
> length "
> > + drm_err(&dev_priv->drm, "DMC firmware has wrong
> package header length "
> > "(%u bytes)\n", package_size);
> > return 0;
> > }
> > @@ -544,7 +545,7 @@ parse_csr_fw_package(struct intel_csr *csr,
> > dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
> > package_header->header_ver);
> > if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
> > - DRM_ERROR("DMC firmware not supported for %c
> stepping\n",
> > + drm_err(&dev_priv->drm, "DMC firmware not supported for
> %c
> > +stepping\n",
> > si->stepping);
> > return 0;
> > }
> > @@ -553,23 +554,25 @@ parse_csr_fw_package(struct intel_csr *csr,
> > return package_size + dmc_offset * 4;
> >
> > error_truncated:
> > - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> > + drm_err(&dev_priv->drm, "Truncated DMC firmware, refusing.\n");
> > return 0;
> > }
> >
> > /* Return number of bytes parsed or 0 on error */ -static u32
> > parse_csr_fw_css(struct intel_csr *csr,
> > +static u32 parse_csr_fw_css(struct drm_i915_private *dev_priv,
> > struct intel_css_header *css_header,
> > size_t rem_size)
> > {
> > + struct intel_csr *csr = &dev_priv->csr;
> > +
> > if (rem_size < sizeof(struct intel_css_header)) {
> > - DRM_ERROR("Truncated DMC firmware, refusing.\n");
> > + drm_err(&dev_priv->drm, "Truncated DMC firmware,
> refusing.\n");
> > return 0;
> > }
> >
> > if (sizeof(struct intel_css_header) !=
> > (css_header->header_len * 4)) {
> > - DRM_ERROR("DMC firmware has wrong CSS header length "
> > + drm_err(&dev_priv->drm, "DMC firmware has wrong CSS
> header length "
> > "(%u bytes)\n",
> > (css_header->header_len * 4));
> > return 0;
> > @@ -577,7 +580,7 @@ static u32 parse_csr_fw_css(struct intel_csr *csr,
> >
> > if (csr->required_version &&
> > css_header->version != csr->required_version) {
> > - DRM_INFO("Refusing to load DMC firmware v%u.%u,"
> > + drm_info(&dev_priv->drm, "Refusing to load DMC firmware
> v%u.%u,"
> > " please use v%u.%u\n",
> > CSR_VERSION_MAJOR(css_header->version),
> > CSR_VERSION_MINOR(css_header->version),
> > @@ -597,7 +600,6 @@ static void parse_csr_fw(struct drm_i915_private
> *dev_priv,
> > struct intel_css_header *css_header;
> > struct intel_package_header *package_header;
> > struct intel_dmc_header_base *dmc_header;
> > - struct intel_csr *csr = &dev_priv->csr;
> > const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> > u32 readcount = 0;
> > u32 r;
> > @@ -607,7 +609,7 @@ static void parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> >
> > /* Extract CSS Header information */
> > css_header = (struct intel_css_header *)fw->data;
> > - r = parse_csr_fw_css(csr, css_header, fw->size);
> > + r = parse_csr_fw_css(dev_priv, css_header, fw->size);
> > if (!r)
> > return;
> >
> > @@ -615,7 +617,7 @@ static void parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> >
> > /* Extract Package Header information */
> > package_header = (struct intel_package_header *)&fw-
> >data[readcount];
> > - r = parse_csr_fw_package(csr, package_header, si, fw->size -
> readcount);
> > + r = parse_csr_fw_package(dev_priv, package_header, si, fw->size -
> > +readcount);
> > if (!r)
> > return;
> >
> > @@ -623,7 +625,7 @@ static void parse_csr_fw(struct drm_i915_private
> > *dev_priv,
> >
> > /* Extract dmc_header information */
> > dmc_header = (struct intel_dmc_header_base *)&fw-
> >data[readcount];
> > - parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
> > + parse_csr_fw_dmc(dev_priv, dmc_header, fw->size - readcount);
> > }
> >
> > static void intel_csr_runtime_pm_get(struct drm_i915_private
> > *dev_priv)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper
2021-05-03 18:07 ` Jani Nikula
@ 2021-05-03 21:50 ` Srivatsa, Anusha
0 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2021-05-03 21:50 UTC (permalink / raw)
To: Jani Nikula, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Monday, May 3, 2021 11:07 AM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add
> intel_csr_has_dmc_payload() helper
>
> On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
> > We check for dmc_payload being there at various points in the driver.
> > Replace it with the helper.
>
> Yes please!
>
> >
> > While at it moving bits related to CSR to intel_csr.h
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_csr.c | 13 +++++++----
> > drivers/gpu/drm/i915/display/intel_csr.h | 23 +++++++++++++++++++
> > .../drm/i915/display/intel_display_debugfs.c | 4 ++--
> > .../drm/i915/display/intel_display_power.c | 16 ++++++-------
> > drivers/gpu/drm/i915/i915_drv.h | 18 +--------------
> > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> > 6 files changed, 44 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_csr.c
> > b/drivers/gpu/drm/i915/display/intel_csr.c
> > index bf60c3ffdf5d..66d369ec4f02 100644
> > --- a/drivers/gpu/drm/i915/display/intel_csr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> > @@ -238,6 +238,11 @@ struct stepping_info {
> > char substepping;
> > };
> >
> > +bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv)
>
> s/dev_priv/i915/g
>
> > +{
> > + return dev_priv->csr.dmc_payload;
> > +}
> > +
> > static const struct stepping_info skl_stepping_info[] = {
> > {'A', '0'}, {'B', '0'}, {'C', '0'},
> > {'D', '0'}, {'E', '0'}, {'F', '0'},
> > @@ -321,7 +326,7 @@ void intel_csr_load_program(struct
> drm_i915_private *dev_priv)
> > return;
> > }
> >
> > - if (!dev_priv->csr.dmc_payload) {
> > + if (!intel_csr_has_dmc_payload(dev_priv)) {
> > drm_err(&dev_priv->drm,
> > "Tried to program CSR with empty payload\n");
> > return;
> > @@ -655,7 +660,7 @@ static void csr_load_work_fn(struct work_struct
> *work)
> > request_firmware(&fw, dev_priv->csr.fw_path, dev_priv-
> >drm.dev);
> > parse_csr_fw(dev_priv, fw);
> >
> > - if (dev_priv->csr.dmc_payload) {
> > + if (intel_csr_has_dmc_payload(dev_priv)) {
> > intel_csr_load_program(dev_priv);
> > intel_csr_runtime_pm_put(dev_priv);
> >
> > @@ -784,7 +789,7 @@ void intel_csr_ucode_suspend(struct
> drm_i915_private *dev_priv)
> > flush_work(&dev_priv->csr.work);
> >
> > /* Drop the reference held in case DMC isn't loaded. */
> > - if (!dev_priv->csr.dmc_payload)
> > + if (!intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_runtime_pm_put(dev_priv);
> > }
> >
> > @@ -804,7 +809,7 @@ void intel_csr_ucode_resume(struct
> drm_i915_private *dev_priv)
> > * Reacquire the reference to keep RPM disabled in case DMC isn't
> > * loaded.
> > */
> > - if (!dev_priv->csr.dmc_payload)
> > + if (!intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_runtime_pm_get(dev_priv);
> > }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_csr.h
> > b/drivers/gpu/drm/i915/display/intel_csr.h
> > index 03c64f8af7ab..9cab82dfb1ed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_csr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_csr.h
> > @@ -6,6 +6,10 @@
> > #ifndef __INTEL_CSR_H__
> > #define __INTEL_CSR_H__
> >
> > +#include <drm/drm_util.h>
>
> What for?
Let me check with removing the above header.
> You'll need <linux/types.h>.
Sure.
> We may want to consider having split interface and types headers... but
> maybe later.
Sounds good.
Thanks for the feedback Jani.
Anusha
>
> > +#include "intel_wakeref.h"
> > +#include "i915_reg.h"
> > +
> > struct drm_i915_private;
> >
> > #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
> > @@ -18,4 +22,23 @@ void intel_csr_ucode_fini(struct drm_i915_private
> > *i915); void intel_csr_ucode_suspend(struct drm_i915_private *i915);
> > void intel_csr_ucode_resume(struct drm_i915_private *i915);
> >
> > +struct intel_csr {
> > + struct work_struct work;
> > + const char *fw_path;
> > + u32 required_version;
> > + u32 max_fw_size; /* bytes */
> > + u32 *dmc_payload;
> > + u32 dmc_fw_size; /* dwords */
> > + u32 version;
> > + u32 mmio_count;
> > + i915_reg_t mmioaddr[20];
> > + u32 mmiodata[20];
> > + u32 dc_state;
> > + u32 target_dc_state;
> > + u32 allowed_dc_mask;
> > + intel_wakeref_t wakeref;
> > +};
> > +
> > +bool intel_csr_has_dmc_payload(struct drm_i915_private *dev_priv);
> > +
> > #endif /* __INTEL_CSR_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 183c414d554a..a10c9d4c2536 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -541,10 +541,10 @@ static int i915_dmc_info(struct seq_file *m,
> > void *unused)
> >
> > wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> >
> > - seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload !=
> NULL));
> > + seq_printf(m, "fw loaded: %s\n",
> > +yesno(intel_csr_has_dmc_payload(dev_priv)));
> > seq_printf(m, "path: %s\n", csr->fw_path);
> >
> > - if (!csr->dmc_payload)
> > + if (!intel_csr_has_dmc_payload(dev_priv))
> > goto out;
> >
> > seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr-
> >version),
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index d48dd15a4f6e..6a9d99b80755 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -1219,7 +1219,7 @@ static void
> gen9_dc_off_power_well_enable(struct
> > drm_i915_private *dev_priv, static void
> gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
> > struct i915_power_well
> *power_well) {
> > - if (!dev_priv->csr.dmc_payload)
> > + if (!intel_csr_has_dmc_payload(dev_priv))
> > return;
> >
> > switch (dev_priv->csr.target_dc_state) { @@ -5150,7 +5150,7 @@
> > static void skl_display_core_init(struct drm_i915_private *dev_priv,
> >
> > gen9_dbuf_enable(dev_priv);
> >
> > - if (resume && dev_priv->csr.dmc_payload)
> > + if (resume && intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_load_program(dev_priv);
> > }
> >
> > @@ -5217,7 +5217,7 @@ static void bxt_display_core_init(struct
> > drm_i915_private *dev_priv, bool resume
> >
> > gen9_dbuf_enable(dev_priv);
> >
> > - if (resume && dev_priv->csr.dmc_payload)
> > + if (resume && intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_load_program(dev_priv);
> > }
> >
> > @@ -5283,7 +5283,7 @@ static void cnl_display_core_init(struct
> drm_i915_private *dev_priv, bool resume
> > /* 6. Enable DBUF */
> > gen9_dbuf_enable(dev_priv);
> >
> > - if (resume && dev_priv->csr.dmc_payload)
> > + if (resume && intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_load_program(dev_priv);
> > }
> >
> > @@ -5440,7 +5440,7 @@ static void icl_display_core_init(struct
> drm_i915_private *dev_priv,
> > if (DISPLAY_VER(dev_priv) >= 12)
> > tgl_bw_buddy_init(dev_priv);
> >
> > - if (resume && dev_priv->csr.dmc_payload)
> > + if (resume && intel_csr_has_dmc_payload(dev_priv))
> > intel_csr_load_program(dev_priv);
> >
> > /* Wa_14011508470 */
> > @@ -5797,7 +5797,7 @@ void intel_power_domains_suspend(struct
> drm_i915_private *i915,
> > */
> > if (!(i915->csr.allowed_dc_mask & DC_STATE_EN_DC9) &&
> > suspend_mode == I915_DRM_SUSPEND_IDLE &&
> > - i915->csr.dmc_payload) {
> > + intel_csr_has_dmc_payload(i915)) {
> > intel_display_power_flush_work(i915);
> > intel_power_domains_verify_state(i915);
> > return;
> > @@ -5987,7 +5987,7 @@ void intel_display_power_resume(struct
> drm_i915_private *i915)
> > if (DISPLAY_VER(i915) >= 11) {
> > bxt_disable_dc9(i915);
> > icl_display_core_init(i915, true);
> > - if (i915->csr.dmc_payload) {
> > + if (intel_csr_has_dmc_payload(i915)) {
> > if (i915->csr.allowed_dc_mask &
> > DC_STATE_EN_UPTO_DC6)
> > skl_enable_dc6(i915);
> > @@ -5998,7 +5998,7 @@ void intel_display_power_resume(struct
> drm_i915_private *i915)
> > } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> > bxt_disable_dc9(i915);
> > bxt_display_core_init(i915, true);
> > - if (i915->csr.dmc_payload &&
> > + if (intel_csr_has_dmc_payload(i915) &&
> > (i915->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> > gen9_enable_dc5(i915);
> > } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { diff --git
> > a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 336b09f38aad..50f32d89e175 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -74,6 +74,7 @@
> > #include "display/intel_global_state.h"
> > #include "display/intel_gmbus.h"
> > #include "display/intel_opregion.h"
> > +#include "display/intel_csr.h"
> >
> > #include "gem/i915_gem_context_types.h"
> > #include "gem/i915_gem_shrinker.h"
> > @@ -329,23 +330,6 @@ struct drm_i915_display_funcs {
> > void (*read_luts)(struct intel_crtc_state *crtc_state); };
> >
> > -struct intel_csr {
> > - struct work_struct work;
> > - const char *fw_path;
> > - u32 required_version;
> > - u32 max_fw_size; /* bytes */
> > - u32 *dmc_payload;
> > - u32 dmc_fw_size; /* dwords */
> > - u32 version;
> > - u32 mmio_count;
> > - i915_reg_t mmioaddr[20];
> > - u32 mmiodata[20];
> > - u32 dc_state;
> > - u32 target_dc_state;
> > - u32 allowed_dc_mask;
> > - intel_wakeref_t wakeref;
> > -};
> > -
> > enum i915_cache_level {
> > I915_CACHE_NONE = 0,
> > I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
> diff
> > --git a/drivers/gpu/drm/i915/i915_gpu_error.c
> > b/drivers/gpu/drm/i915/i915_gpu_error.c
> > index bb181fe5d47e..cbf485e8510a 100644
> > --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> > @@ -793,7 +793,7 @@ static void __err_print_to_sgl(struct
> drm_i915_error_state_buf *m,
> > struct intel_csr *csr = &m->i915->csr;
> >
> > err_printf(m, "DMC loaded: %s\n",
> > - yesno(csr->dmc_payload != NULL));
> > + yesno(intel_csr_has_dmc_payload(m->i915) != 0));
> > err_printf(m, "DMC fw version: %d.%d\n",
> > CSR_VERSION_MAJOR(csr->version),
> > CSR_VERSION_MINOR(csr->version));
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches
2021-05-03 18:12 ` [Intel-gfx] [PATCH 0/3] " Jani Nikula
@ 2021-05-05 6:40 ` Jani Nikula
2021-05-05 17:36 ` Srivatsa, Anusha
0 siblings, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2021-05-05 6:40 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx
On Mon, 03 May 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com> wrote:
>> This series adds the prep work needed before the
>> actual Pipe DMC implementation.
>
> When should we rename csr to dmc all over the place?
To elaborate, I think it's pretty confusing that we use both CSR and DMC
acronyms in code. There may be a distinction, but we don't respect that
in the usage. Sure, the spec mentions both, but I don't think we follow
the naming there either.
I think we should just rename all CSR references to DMC, including the
file name and the function and struct names.
I wonder if it would be better to do the renames first before starting
to build a lot of changes on top.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches
2021-05-05 6:40 ` Jani Nikula
@ 2021-05-05 17:36 ` Srivatsa, Anusha
0 siblings, 0 replies; 15+ messages in thread
From: Srivatsa, Anusha @ 2021-05-05 17:36 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Tuesday, May 4, 2021 11:41 PM
> To: Srivatsa, Anusha <anusha.srivatsa@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches
>
> On Mon, 03 May 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Wed, 28 Apr 2021, Anusha Srivatsa <anusha.srivatsa@intel.com>
> wrote:
> >> This series adds the prep work needed before the actual Pipe DMC
> >> implementation.
> >
> > When should we rename csr to dmc all over the place?
>
> To elaborate, I think it's pretty confusing that we use both CSR and DMC
> acronyms in code. There may be a distinction, but we don't respect that in
> the usage. Sure, the spec mentions both, but I don't think we follow the
> naming there either.
>
> I think we should just rename all CSR references to DMC, including the file
> name and the function and struct names.
>
Just eyeballing the source file, it looks like it is a good way to go. We have function names like parse_csr_fw_dmc which can be changed to just parse_dmc_fw_header or something on those lines...
> I wonder if it would be better to do the renames first before starting to build
> a lot of changes on top.
Yes. The renames will affect some things that this series touches as well.
Anusha
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2021-05-05 17:37 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-04-28 21:12 [Intel-gfx] [PATCH 0/3] Pipe DMC Prep patches Anusha Srivatsa
2021-04-28 21:12 ` [Intel-gfx] [PATCH 1/3] drm/i915/csr: s/DRM_ERROR/drm_err Anusha Srivatsa
2021-05-03 18:03 ` Jani Nikula
2021-05-03 21:45 ` Srivatsa, Anusha
2021-04-28 21:12 ` [Intel-gfx] [PATCH 2/3] drm/i915/csr: Add intel_csr_has_dmc_payload() helper Anusha Srivatsa
2021-05-03 18:07 ` Jani Nikula
2021-05-03 21:50 ` Srivatsa, Anusha
2021-04-28 21:12 ` [Intel-gfx] [PATCH 3/3] drm/i915/csr: Introduce DMC_FW_MAIN Anusha Srivatsa
2021-04-28 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Prep patches Patchwork
2021-04-28 21:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-04-28 22:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-04-28 23:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-05-03 18:12 ` [Intel-gfx] [PATCH 0/3] " Jani Nikula
2021-05-05 6:40 ` Jani Nikula
2021-05-05 17:36 ` Srivatsa, Anusha
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