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[14.201.155.8]) by smtp.gmail.com with ESMTPSA id q9sm4636370pjm.23.2021.05.17.00.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 00:19:11 -0700 (PDT) Date: Mon, 17 May 2021 17:19:06 +1000 From: Nicholas Piggin Subject: Re: [PATCH] target/ppc: Implement ISA v3.1 wait variants To: David Gibson References: <20210517024651.2200837-1-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1621234864.zkbj7ifbxd.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=npiggin@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Excerpts from David Gibson's message of May 17, 2021 3:39 pm: > On Mon, May 17, 2021 at 12:46:51PM +1000, Nicholas Piggin wrote: >> ISA v3.1 adds new variations of wait, specified by the WC field. These >> are not compatible with the wait 0 implementation, because they add >> additional conditions that cause the processor to resume, which can >> cause software to hang or run very slowly. >>=20 >> Add the new wait variants with a trivial no-op implementation, which is >> allowed, as explained in comments: software must not depend on any >> particular architected WC condition having caused resumption of >> execution, therefore a no-op implementation is architecturally correct. >>=20 >> Signed-off-by: Nicholas Piggin >=20 > Logic looks fine. There is no test on the CPU's features or model > here, though, so this will change behaviour for pre-3.1 CPUs as well. Huh. 2.06-2.07 has very similar WC bits as 3.1, but 3.0 removed them and made them reserved. I should have looked back but I'd assumed they weren't there either. Existing code treats WC !=3D 0 as invalid on pre-3.0 processors AFAIKS, so that's not quite right for 2.06-7 (they should look more like 3.1). But before that it looks like it was just wait with no WC field. > What would invoking these wait variants (presumably reserved) on > earlier CPUs do? Prior to 2.06, it looks like there is no WC field, and so they should=20 generate a program check. So that just leaves the incorrect program checks for 2.06-7, something like this should do it: -GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), +GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA206), 2.06-3.1 should all be fine with this patch, AFAIKS they all have words=20 to the effect that WC !=3D 0 is subject to implementation defined=20 behaviour and may be treated as a no-op or not implemented. Thanks, Nick