From: Yang Weijiang <weijiang.yang@intel.com>
To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com,
seanjc@google.com, richard.henderson@linaro.org,
qemu-devel@nongnu.org, kvm@vger.kernel.org
Cc: Yang Weijiang <weijiang.yang@intel.com>
Subject: [PATCH v8 0/6] Enable CET support for guest
Date: Thu, 20 May 2021 13:57:05 +0800 [thread overview]
Message-ID: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> (raw)
Control-flow Enforcement Technology (CET) provides protection against
Return/Jump-Oriented Programming (ROP/JOP). It includes two features:
Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT).
This patch series is to enable CET related CPUID report, XSAVES/XRSTORS
support and MSR access etc. for guest.
Change in v8:
- Extended xsave_area_size() to accommodate compacted format size calculation.
- Added CPUID(0xD,1).EBX assigment per maintain's feedback.
- Changed XSS field check and added more comments to make things clearer.
- Other ajustment per maintainer's review feedback.
- Rebased to 6.0.0.
v7 patch:
https://lore.kernel.org/kvm/20210226022058.24562-1-weijiang.yang@intel.com
CET KVM patches:
https://git.kernel.org/pub/scm/virt/kvm/kvm.git/log/?h=intel
CET kernel patches:
https://lkml.kernel.org/r/20210427204315.24153-1-yu-cheng.yu@intel.com
Yang Weijiang (6):
target/i386: Change XSAVE related feature-word names
target/i386: Enable XSS feature CPUID enumeration
target/i386: Enable XSAVES support for CET states
target/i386: Add user-space MSR access interface for CET
target/i386: Add CET state support for guest migration
target/i386: Advise CET bits in CPU/MSR feature words
target/i386/cpu.c | 138 +++++++++++++++++++++++++++++-------
target/i386/cpu.h | 52 +++++++++++++-
target/i386/kvm/kvm.c | 72 +++++++++++++++++++
target/i386/machine.c | 161 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 395 insertions(+), 28 deletions(-)
--
2.26.2
next reply other threads:[~2021-05-20 5:43 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 5:57 Yang Weijiang [this message]
2021-05-20 5:57 ` [PATCH v8 1/6] target/i386: Change XSAVE related feature-word names Yang Weijiang
2021-05-20 5:57 ` [PATCH v8 2/6] target/i386: Enable XSS feature CPUID enumeration Yang Weijiang
2021-05-20 5:57 ` [PATCH v8 3/6] target/i386: Enable XSAVES support for CET states Yang Weijiang
2021-05-20 5:57 ` [PATCH v8 4/6] target/i386: Add user-space MSR access interface for CET Yang Weijiang
2021-05-20 5:57 ` [PATCH v8 5/6] target/i386: Add CET state support for guest migration Yang Weijiang
2021-05-20 5:57 ` [PATCH v8 6/6] target/i386: Advise CET bits in CPU/MSR feature words Yang Weijiang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1621490231-4765-1-git-send-email-weijiang.yang@intel.com \
--to=weijiang.yang@intel.com \
--cc=ehabkost@redhat.com \
--cc=kvm@vger.kernel.org \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=seanjc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.