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From: Stephen Boyd <sboyd@kernel.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>,
	phone-devel@vger.kernel.org
Cc: ~postmarketos/upstreaming@lists.sr.ht,
	martin.botka@somainline.org,
	angelogioacchino.delregno@somainline.org,
	marijn.suijten@somainline.org,
	Konrad Dybcio <konrad.dybcio@somainline.org>,
	Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Taniya Das <tdas@codeaurora.org>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/2] clk: qcom: Add MDM9607 GCC driver
Date: Tue, 01 Jun 2021 23:50:11 -0700	[thread overview]
Message-ID: <162261661130.4130789.14150099315161377490@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210313020310.386152-2-konrad.dybcio@somainline.org>

Quoting Konrad Dybcio (2021-03-12 18:03:08)
> Add Global Clock Controller (GCC) support for MDM9607 SoC.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---

Applied to clk-next

>  drivers/clk/qcom/Kconfig       |    7 +
>  drivers/clk/qcom/Makefile      |    1 +
>  drivers/clk/qcom/gcc-mdm9607.c | 1656 ++++++++++++++++++++++++++++++++
>  3 files changed, 1664 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-mdm9607.c
> 
> diff --git a/drivers/clk/qcom/gcc-mdm9607.c b/drivers/clk/qcom/gcc-mdm9607.c
> new file mode 100644
> index 000000000000..a4b3cff7e98f
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-mdm9607.c
> @@ -0,0 +1,1656 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk.h>

I dropped this.

> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-mdm9607.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
[...]
> +
> +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
> +       F(19200000, P_XO, 1, 0, 0),
> +       F(50000000, P_GPLL0, 16, 0, 0),
> +       F(100000000, P_GPLL0, 8, 0, 0),
> +       { }
> +};
> +
> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> +       .cmd_rcgr = 0x27000,
> +       .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
> +       .hid_width = 5,
> +       .parent_map = gcc_xo_gpll0_bimc_map,
> +       .clkr.hw.init = &(struct clk_init_data){
> +               .name = "pcnoc_bfdcd_clk_src",
> +               .parent_data = gcc_xo_gpll0_bimc,
> +               .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
> +               .ops = &clk_rcg2_ops,
> +               .flags = CLK_IS_CRITICAL,

Is this how it is downstream? Because it looks like this will mean that
xo shutdown can never be achieved.

> +       },
> +};
> +

  reply	other threads:[~2021-06-02  6:50 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-13  2:03 [PATCH 1/2] dt-bindings: clock: Add MDM9607 GCC clock bindings Konrad Dybcio
2021-03-13  2:03 ` [PATCH 2/2] clk: qcom: Add MDM9607 GCC driver Konrad Dybcio
2021-06-02  6:50   ` Stephen Boyd [this message]
2021-03-24 17:08 ` [PATCH 1/2] dt-bindings: clock: Add MDM9607 GCC clock bindings Rob Herring
2021-06-02  6:50 ` Stephen Boyd

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