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From: Stephen Boyd <>
To: Luca Ceresoli <>,
Cc: Luca Ceresoli <>,
	Michael Turquette <>,, Adam Ford <>
Subject: Re: [PATCH RESEND] clk: vc5: fix output disabling when enabling a FOD
Date: Wed, 02 Jun 2021 01:00:45 -0700	[thread overview]
Message-ID: <> (raw)
In-Reply-To: <>

Quoting Luca Ceresoli (2021-05-27 14:16:47)
> On 5P49V6965, when an output is enabled we enable the corresponding
> FOD. When this happens for the first time, and specifically when writing
> register VC5_OUT_DIV_CONTROL in vc5_clk_out_prepare(), all other outputs
> are stopped for a short time and then restarted.
> According to Renesas support this is intended: "The reason for that is VC6E
> has synced up all output function".
> This behaviour can be disabled at least on VersaClock 6E devices, of which
> only the 5P49V6965 is currently implemented by this driver. This requires
> writing bit 7 (bypass_sync{1..4}) in register 0x20..0x50.  Those registers
> are named "Unused Factory Reserved Register", and the bits are documented
> as "Skip VDDO<N> verification", which does not clearly explain the relation
> to FOD sync. However according to Renesas support as well as my testing
> setting this bit does prevent disabling of all clock outputs when enabling
> a FOD.
> See "VersaClock ® 6E Family Register Descriptions and Programming Guide"
> (August 30, 2018), Table 116 "Power Up VDD check", page 58:
> Signed-off-by: Luca Ceresoli <>
> Reviewed-by: Adam Ford <>
> ---

Any Fixes tag for this patch?

  reply	other threads:[~2021-06-02  8:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-27 21:16 Luca Ceresoli
2021-06-02  8:00 ` Stephen Boyd [this message]
2021-06-03  8:44   ` Luca Ceresoli
2021-06-03 20:07     ` Stephen Boyd
2021-06-03 21:06       ` Luca Ceresoli
2021-06-09  0:53 ` Stephen Boyd

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