* [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs in place before performing the
actual blit.
Some ww utilities mainly for the accompanying selftests added by Thomas,
as well as modified the above patches for ww locking- and lmem support.
The actual hook up to the i915 ttm backend is being worked on and not
included yet, so this is considered to be an early review opportunity.
v2:
- A couple of minor style fixes pointed out by Matthew Auld
- Export and use intel_engine_destroy_pinned_context() to address a
CI warning / failure.
Chris Wilson (6):
drm/i915/gt: Add an insert_entry for gen8_ppgtt
drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
drm/i915/gt: Export the pinned context constructor and destructor
drm/i915/gt: Pipelined page migration
drm/i915/gt: Pipelined clear
drm/i915/gt: Setup a default migration context on the GT
Thomas Hellström (3):
drm/i915: Reference objects on the ww object list
drm/i915: Break out dma_resv ww locking utilities to separate files
drm/i915: Introduce a ww transaction helper
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
drivers/gpu/drm/i915/i915_gem.c | 52 --
drivers/gpu/drm/i915/i915_gem.h | 12 -
drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
21 files changed, 1675 insertions(+), 76 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
--
2.31.1
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
A couple of patches from Chris which implement pipelined migration and
clears by atomically writing the PTEs in place before performing the
actual blit.
Some ww utilities mainly for the accompanying selftests added by Thomas,
as well as modified the above patches for ww locking- and lmem support.
The actual hook up to the i915 ttm backend is being worked on and not
included yet, so this is considered to be an early review opportunity.
v2:
- A couple of minor style fixes pointed out by Matthew Auld
- Export and use intel_engine_destroy_pinned_context() to address a
CI warning / failure.
Chris Wilson (6):
drm/i915/gt: Add an insert_entry for gen8_ppgtt
drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
drm/i915/gt: Export the pinned context constructor and destructor
drm/i915/gt: Pipelined page migration
drm/i915/gt: Pipelined clear
drm/i915/gt: Setup a default migration context on the GT
Thomas Hellström (3):
drm/i915: Reference objects on the ww object list
drm/i915: Break out dma_resv ww locking utilities to separate files
drm/i915: Introduce a ww transaction helper
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
drivers/gpu/drm/i915/i915_gem.c | 52 --
drivers/gpu/drm/i915/i915_gem.h | 12 -
drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
21 files changed, 1675 insertions(+), 76 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [PATCH v2 1/9] drm/i915: Reference objects on the ww object list
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
Since the ww transaction endpoint easily end up far out-of-scope of
the objects on the ww object list, particularly for contending lock
objects, make sure we reference objects on the list so they don't
disappear under us.
This comes with a performance penalty so it's been debated whether this
is really needed. But I think this is motivated by the fact that locking
is typically difficult to get right, and whatever we can do to make it
simpler for developers moving forward should be done, unless the
performance impact is far too high.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 ++++++--
drivers/gpu/drm/i915/i915_gem.c | 4 ++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 7c0eb425cb3b..1fafcc89ecee 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -169,13 +169,17 @@ static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj,
else
ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL);
- if (!ret && ww)
+ if (!ret && ww) {
+ i915_gem_object_get(obj);
list_add_tail(&obj->obj_link, &ww->obj_list);
+ }
if (ret == -EALREADY)
ret = 0;
- if (ret == -EDEADLK)
+ if (ret == -EDEADLK) {
+ i915_gem_object_get(obj);
ww->contended = obj;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 589388dec48a..3f060ab58c5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1219,6 +1219,7 @@ static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
list_del(&obj->obj_link);
i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
}
}
@@ -1226,6 +1227,7 @@ void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
{
list_del(&obj->obj_link);
i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
}
void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
@@ -1250,6 +1252,8 @@ int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
if (!ret)
list_add_tail(&ww->contended->obj_link, &ww->obj_list);
+ else
+ i915_gem_object_put(ww->contended);
ww->contended = NULL;
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 1/9] drm/i915: Reference objects on the ww object list
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
Since the ww transaction endpoint easily end up far out-of-scope of
the objects on the ww object list, particularly for contending lock
objects, make sure we reference objects on the list so they don't
disappear under us.
This comes with a performance penalty so it's been debated whether this
is really needed. But I think this is motivated by the fact that locking
is typically difficult to get right, and whatever we can do to make it
simpler for developers moving forward should be done, unless the
performance impact is far too high.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_object.h | 8 ++++++--
drivers/gpu/drm/i915/i915_gem.c | 4 ++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 7c0eb425cb3b..1fafcc89ecee 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -169,13 +169,17 @@ static inline int __i915_gem_object_lock(struct drm_i915_gem_object *obj,
else
ret = dma_resv_lock(obj->base.resv, ww ? &ww->ctx : NULL);
- if (!ret && ww)
+ if (!ret && ww) {
+ i915_gem_object_get(obj);
list_add_tail(&obj->obj_link, &ww->obj_list);
+ }
if (ret == -EALREADY)
ret = 0;
- if (ret == -EDEADLK)
+ if (ret == -EDEADLK) {
+ i915_gem_object_get(obj);
ww->contended = obj;
+ }
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 589388dec48a..3f060ab58c5d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1219,6 +1219,7 @@ static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
list_del(&obj->obj_link);
i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
}
}
@@ -1226,6 +1227,7 @@ void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
{
list_del(&obj->obj_link);
i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
}
void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
@@ -1250,6 +1252,8 @@ int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
if (!ret)
list_add_tail(&ww->contended->obj_link, &ww->obj_list);
+ else
+ i915_gem_object_put(ww->contended);
ww->contended = NULL;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 2/9] drm/i915: Break out dma_resv ww locking utilities to separate files
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
As we're about to add more ww-related functionality,
break out the dma_resv ww locking utilities to their own files
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Make sure filenames are sorted in include file lists and Makefile
(Reported by Matthew Auld)
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 56 ------------------
drivers/gpu/drm/i915/i915_gem.h | 12 ----
drivers/gpu/drm/i915/i915_gem_ww.c | 63 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_ww.h | 21 +++++++
7 files changed, 87 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4f22cac1c49b..16a5a006cf7c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -164,6 +164,7 @@ i915-y += \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_gtt.o \
+ i915_gem_ww.o \
i915_gem.o \
i915_globals.o \
i915_query.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 1fafcc89ecee..bdab929e448b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -14,6 +14,7 @@
#include "display/intel_frontbuffer.h"
#include "i915_gem_object_types.h"
#include "i915_gem_gtt.h"
+#include "i915_gem_ww.h"
#include "i915_vma_types.h"
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.h b/drivers/gpu/drm/i915/gt/intel_renderstate.h
index 48f009203917..4da4c5234ef0 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.h
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include "i915_gem.h"
+#include "i915_gem_ww.h"
struct i915_request;
struct intel_context;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f060ab58c5d..ce64d3005cf2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1204,62 +1204,6 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
return ret;
}
-void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr)
-{
- ww_acquire_init(&ww->ctx, &reservation_ww_class);
- INIT_LIST_HEAD(&ww->obj_list);
- ww->intr = intr;
- ww->contended = NULL;
-}
-
-static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
-{
- struct drm_i915_gem_object *obj;
-
- while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
- list_del(&obj->obj_link);
- i915_gem_object_unlock(obj);
- i915_gem_object_put(obj);
- }
-}
-
-void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
-{
- list_del(&obj->obj_link);
- i915_gem_object_unlock(obj);
- i915_gem_object_put(obj);
-}
-
-void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
-{
- i915_gem_ww_ctx_unlock_all(ww);
- WARN_ON(ww->contended);
- ww_acquire_fini(&ww->ctx);
-}
-
-int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
-{
- int ret = 0;
-
- if (WARN_ON(!ww->contended))
- return -EINVAL;
-
- i915_gem_ww_ctx_unlock_all(ww);
- if (ww->intr)
- ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx);
- else
- dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx);
-
- if (!ret)
- list_add_tail(&ww->contended->obj_link, &ww->obj_list);
- else
- i915_gem_object_put(ww->contended);
-
- ww->contended = NULL;
-
- return ret;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_gem_device.c"
#include "selftests/i915_gem.c"
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 440c35f1abc9..d0752e5553db 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -123,16 +123,4 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
return test_bit(TASKLET_STATE_SCHED, &t->state);
}
-struct i915_gem_ww_ctx {
- struct ww_acquire_ctx ctx;
- struct list_head obj_list;
- bool intr;
- struct drm_i915_gem_object *contended;
-};
-
-void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
-void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
-int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
-void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
-
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.c b/drivers/gpu/drm/i915/i915_gem_ww.c
new file mode 100644
index 000000000000..3f6ff139478e
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_ww.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include <linux/dma-resv.h>
+#include "i915_gem_ww.h"
+#include "gem/i915_gem_object.h"
+
+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr)
+{
+ ww_acquire_init(&ww->ctx, &reservation_ww_class);
+ INIT_LIST_HEAD(&ww->obj_list);
+ ww->intr = intr;
+ ww->contended = NULL;
+}
+
+static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
+{
+ struct drm_i915_gem_object *obj;
+
+ while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
+ list_del(&obj->obj_link);
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+ }
+}
+
+void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
+{
+ list_del(&obj->obj_link);
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+}
+
+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
+{
+ i915_gem_ww_ctx_unlock_all(ww);
+ WARN_ON(ww->contended);
+ ww_acquire_fini(&ww->ctx);
+}
+
+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
+{
+ int ret = 0;
+
+ if (WARN_ON(!ww->contended))
+ return -EINVAL;
+
+ i915_gem_ww_ctx_unlock_all(ww);
+ if (ww->intr)
+ ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx);
+ else
+ dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx);
+
+ if (!ret)
+ list_add_tail(&ww->contended->obj_link, &ww->obj_list);
+ else
+ i915_gem_object_put(ww->contended);
+
+ ww->contended = NULL;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.h b/drivers/gpu/drm/i915/i915_gem_ww.h
new file mode 100644
index 000000000000..f2d8769e4118
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_ww.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#ifndef __I915_GEM_WW_H__
+#define __I915_GEM_WW_H__
+
+#include <drm/drm_drv.h>
+
+struct i915_gem_ww_ctx {
+ struct ww_acquire_ctx ctx;
+ struct list_head obj_list;
+ struct drm_i915_gem_object *contended;
+ bool intr;
+};
+
+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
+void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
+#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 2/9] drm/i915: Break out dma_resv ww locking utilities to separate files
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
As we're about to add more ww-related functionality,
break out the dma_resv ww locking utilities to their own files
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
v2:
- Make sure filenames are sorted in include file lists and Makefile
(Reported by Matthew Auld)
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.h | 1 +
drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
drivers/gpu/drm/i915/i915_gem.c | 56 ------------------
drivers/gpu/drm/i915/i915_gem.h | 12 ----
drivers/gpu/drm/i915/i915_gem_ww.c | 63 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_ww.h | 21 +++++++
7 files changed, 87 insertions(+), 68 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 4f22cac1c49b..16a5a006cf7c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -164,6 +164,7 @@ i915-y += \
i915_cmd_parser.o \
i915_gem_evict.o \
i915_gem_gtt.o \
+ i915_gem_ww.o \
i915_gem.o \
i915_globals.o \
i915_query.o \
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 1fafcc89ecee..bdab929e448b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -14,6 +14,7 @@
#include "display/intel_frontbuffer.h"
#include "i915_gem_object_types.h"
#include "i915_gem_gtt.h"
+#include "i915_gem_ww.h"
#include "i915_vma_types.h"
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.h b/drivers/gpu/drm/i915/gt/intel_renderstate.h
index 48f009203917..4da4c5234ef0 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.h
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include "i915_gem.h"
+#include "i915_gem_ww.h"
struct i915_request;
struct intel_context;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3f060ab58c5d..ce64d3005cf2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1204,62 +1204,6 @@ int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
return ret;
}
-void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr)
-{
- ww_acquire_init(&ww->ctx, &reservation_ww_class);
- INIT_LIST_HEAD(&ww->obj_list);
- ww->intr = intr;
- ww->contended = NULL;
-}
-
-static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
-{
- struct drm_i915_gem_object *obj;
-
- while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
- list_del(&obj->obj_link);
- i915_gem_object_unlock(obj);
- i915_gem_object_put(obj);
- }
-}
-
-void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
-{
- list_del(&obj->obj_link);
- i915_gem_object_unlock(obj);
- i915_gem_object_put(obj);
-}
-
-void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
-{
- i915_gem_ww_ctx_unlock_all(ww);
- WARN_ON(ww->contended);
- ww_acquire_fini(&ww->ctx);
-}
-
-int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
-{
- int ret = 0;
-
- if (WARN_ON(!ww->contended))
- return -EINVAL;
-
- i915_gem_ww_ctx_unlock_all(ww);
- if (ww->intr)
- ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx);
- else
- dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx);
-
- if (!ret)
- list_add_tail(&ww->contended->obj_link, &ww->obj_list);
- else
- i915_gem_object_put(ww->contended);
-
- ww->contended = NULL;
-
- return ret;
-}
-
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/mock_gem_device.c"
#include "selftests/i915_gem.c"
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index 440c35f1abc9..d0752e5553db 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -123,16 +123,4 @@ static inline bool __tasklet_is_scheduled(struct tasklet_struct *t)
return test_bit(TASKLET_STATE_SCHED, &t->state);
}
-struct i915_gem_ww_ctx {
- struct ww_acquire_ctx ctx;
- struct list_head obj_list;
- bool intr;
- struct drm_i915_gem_object *contended;
-};
-
-void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
-void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
-int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
-void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
-
#endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.c b/drivers/gpu/drm/i915/i915_gem_ww.c
new file mode 100644
index 000000000000..3f6ff139478e
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_ww.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#include <linux/dma-resv.h>
+#include "i915_gem_ww.h"
+#include "gem/i915_gem_object.h"
+
+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ww, bool intr)
+{
+ ww_acquire_init(&ww->ctx, &reservation_ww_class);
+ INIT_LIST_HEAD(&ww->obj_list);
+ ww->intr = intr;
+ ww->contended = NULL;
+}
+
+static void i915_gem_ww_ctx_unlock_all(struct i915_gem_ww_ctx *ww)
+{
+ struct drm_i915_gem_object *obj;
+
+ while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
+ list_del(&obj->obj_link);
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+ }
+}
+
+void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj)
+{
+ list_del(&obj->obj_link);
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+}
+
+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ww)
+{
+ i915_gem_ww_ctx_unlock_all(ww);
+ WARN_ON(ww->contended);
+ ww_acquire_fini(&ww->ctx);
+}
+
+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ww)
+{
+ int ret = 0;
+
+ if (WARN_ON(!ww->contended))
+ return -EINVAL;
+
+ i915_gem_ww_ctx_unlock_all(ww);
+ if (ww->intr)
+ ret = dma_resv_lock_slow_interruptible(ww->contended->base.resv, &ww->ctx);
+ else
+ dma_resv_lock_slow(ww->contended->base.resv, &ww->ctx);
+
+ if (!ret)
+ list_add_tail(&ww->contended->obj_link, &ww->obj_list);
+ else
+ i915_gem_object_put(ww->contended);
+
+ ww->contended = NULL;
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.h b/drivers/gpu/drm/i915/i915_gem_ww.h
new file mode 100644
index 000000000000..f2d8769e4118
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_ww.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+#ifndef __I915_GEM_WW_H__
+#define __I915_GEM_WW_H__
+
+#include <drm/drm_drv.h>
+
+struct i915_gem_ww_ctx {
+ struct ww_acquire_ctx ctx;
+ struct list_head obj_list;
+ struct drm_i915_gem_object *contended;
+ bool intr;
+};
+
+void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
+void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
+int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
+void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
+#endif
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 3/9] drm/i915: Introduce a ww transaction helper
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
Introduce a for_i915_gem_ww(){} utility to help make the code
around a ww transaction more readable.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_gem_ww.h | 31 +++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.h b/drivers/gpu/drm/i915/i915_gem_ww.h
index f2d8769e4118..f6b1a796667b 100644
--- a/drivers/gpu/drm/i915/i915_gem_ww.h
+++ b/drivers/gpu/drm/i915/i915_gem_ww.h
@@ -11,11 +11,40 @@ struct i915_gem_ww_ctx {
struct ww_acquire_ctx ctx;
struct list_head obj_list;
struct drm_i915_gem_object *contended;
- bool intr;
+ unsigned short intr;
+ unsigned short loop;
};
void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
+
+/* Internal functions used by the inlines! Don't use. */
+static inline int __i915_gem_ww_fini(struct i915_gem_ww_ctx *ww, int err)
+{
+ ww->loop = 0;
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(ww);
+ if (!err)
+ ww->loop = 1;
+ }
+
+ if (!ww->loop)
+ i915_gem_ww_ctx_fini(ww);
+
+ return err;
+}
+
+static inline void
+__i915_gem_ww_init(struct i915_gem_ww_ctx *ww, bool intr)
+{
+ i915_gem_ww_ctx_init(ww, intr);
+ ww->loop = 1;
+}
+
+#define for_i915_gem_ww(_ww, _err, _intr) \
+ for (__i915_gem_ww_init(_ww, _intr); (_ww)->loop; \
+ _err = __i915_gem_ww_fini(_ww, _err))
+
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 3/9] drm/i915: Introduce a ww transaction helper
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Thomas Hellström
Introduce a for_i915_gem_ww(){} utility to help make the code
around a ww transaction more readable.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_gem_ww.h | 31 +++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_ww.h b/drivers/gpu/drm/i915/i915_gem_ww.h
index f2d8769e4118..f6b1a796667b 100644
--- a/drivers/gpu/drm/i915/i915_gem_ww.h
+++ b/drivers/gpu/drm/i915/i915_gem_ww.h
@@ -11,11 +11,40 @@ struct i915_gem_ww_ctx {
struct ww_acquire_ctx ctx;
struct list_head obj_list;
struct drm_i915_gem_object *contended;
- bool intr;
+ unsigned short intr;
+ unsigned short loop;
};
void i915_gem_ww_ctx_init(struct i915_gem_ww_ctx *ctx, bool intr);
void i915_gem_ww_ctx_fini(struct i915_gem_ww_ctx *ctx);
int __must_check i915_gem_ww_ctx_backoff(struct i915_gem_ww_ctx *ctx);
void i915_gem_ww_unlock_single(struct drm_i915_gem_object *obj);
+
+/* Internal functions used by the inlines! Don't use. */
+static inline int __i915_gem_ww_fini(struct i915_gem_ww_ctx *ww, int err)
+{
+ ww->loop = 0;
+ if (err == -EDEADLK) {
+ err = i915_gem_ww_ctx_backoff(ww);
+ if (!err)
+ ww->loop = 1;
+ }
+
+ if (!ww->loop)
+ i915_gem_ww_ctx_fini(ww);
+
+ return err;
+}
+
+static inline void
+__i915_gem_ww_init(struct i915_gem_ww_ctx *ww, bool intr)
+{
+ i915_gem_ww_ctx_init(ww, intr);
+ ww->loop = 1;
+}
+
+#define for_i915_gem_ww(_ww, _err, _intr) \
+ for (__i915_gem_ww_init(_ww, _intr); (_ww)->loop; \
+ _err = __i915_gem_ww_fini(_ww, _err))
+
#endif
--
2.31.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
In the next patch, we will want to write a PTE for an explicit
dma address, outside of the usual vma.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 21c8b7350b7a..1b676d7700bf 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -555,6 +555,24 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
}
}
+static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ u64 idx = offset >> GEN8_PTE_SHIFT;
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_index(vm, idx);
+ struct i915_page_directory *pd =
+ i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ gen8_pte_t *vaddr;
+
+ vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+}
+
static int gen8_init_scratch(struct i915_address_space *vm)
{
u32 pte_flags;
@@ -734,6 +752,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
+ ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
In the next patch, we will want to write a PTE for an explicit
dma address, outside of the usual vma.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 21c8b7350b7a..1b676d7700bf 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -555,6 +555,24 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
}
}
+static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
+ dma_addr_t addr,
+ u64 offset,
+ enum i915_cache_level level,
+ u32 flags)
+{
+ u64 idx = offset >> GEN8_PTE_SHIFT;
+ struct i915_page_directory * const pdp =
+ gen8_pdp_for_page_index(vm, idx);
+ struct i915_page_directory *pd =
+ i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+ gen8_pte_t *vaddr;
+
+ vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+ vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+ clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+}
+
static int gen8_init_scratch(struct i915_address_space *vm)
{
u32 pte_flags;
@@ -734,6 +752,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
ppgtt->vm.insert_entries = gen8_ppgtt_insert;
+ ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
--
2.31.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
In the next patch, we will want to look at the dma addresses of
individual page tables, so add a routine to iterate over them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 49 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gtt.h | 7 ++++
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 1b676d7700bf..3d02c726c746 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -361,6 +361,54 @@ static void gen8_ppgtt_alloc(struct i915_address_space *vm,
&start, start + length, vm->top);
}
+static void __gen8_ppgtt_foreach(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ u64 *start, u64 end, int lvl,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data)
+{
+ unsigned int idx, len;
+
+ len = gen8_pd_range(*start, end, lvl--, &idx);
+
+ spin_lock(&pd->lock);
+ do {
+ struct i915_page_table *pt = pd->entry[idx];
+
+ atomic_inc(&pt->used);
+ spin_unlock(&pd->lock);
+
+ if (lvl) {
+ __gen8_ppgtt_foreach(vm, as_pd(pt), start, end, lvl,
+ fn, data);
+ } else {
+ fn(vm, pt, data);
+ *start += gen8_pt_count(*start, end);
+ }
+
+ spin_lock(&pd->lock);
+ atomic_dec(&pt->used);
+ } while (idx++, --len);
+ spin_unlock(&pd->lock);
+}
+
+static void gen8_ppgtt_foreach(struct i915_address_space *vm,
+ u64 start, u64 length,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data)
+{
+ start >>= GEN8_PTE_SHIFT;
+ length >>= GEN8_PTE_SHIFT;
+
+ __gen8_ppgtt_foreach(vm, i915_vm_to_ppgtt(vm)->pd,
+ &start, start + length, vm->top,
+ fn, data);
+}
+
static __always_inline u64
gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
struct i915_page_directory *pdp,
@@ -755,6 +803,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
+ ppgtt->vm.foreach = gen8_ppgtt_foreach;
ppgtt->vm.pte_encode = gen8_pte_encode;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index edea95b97c36..9bd89f2a01ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -296,6 +296,13 @@ struct i915_address_space {
u32 flags);
void (*cleanup)(struct i915_address_space *vm);
+ void (*foreach)(struct i915_address_space *vm,
+ u64 start, u64 length,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data);
+
struct i915_vma_ops vma_ops;
I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
In the next patch, we will want to look at the dma addresses of
individual page tables, so add a routine to iterate over them.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 49 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gtt.h | 7 ++++
2 files changed, 56 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 1b676d7700bf..3d02c726c746 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -361,6 +361,54 @@ static void gen8_ppgtt_alloc(struct i915_address_space *vm,
&start, start + length, vm->top);
}
+static void __gen8_ppgtt_foreach(struct i915_address_space *vm,
+ struct i915_page_directory *pd,
+ u64 *start, u64 end, int lvl,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data)
+{
+ unsigned int idx, len;
+
+ len = gen8_pd_range(*start, end, lvl--, &idx);
+
+ spin_lock(&pd->lock);
+ do {
+ struct i915_page_table *pt = pd->entry[idx];
+
+ atomic_inc(&pt->used);
+ spin_unlock(&pd->lock);
+
+ if (lvl) {
+ __gen8_ppgtt_foreach(vm, as_pd(pt), start, end, lvl,
+ fn, data);
+ } else {
+ fn(vm, pt, data);
+ *start += gen8_pt_count(*start, end);
+ }
+
+ spin_lock(&pd->lock);
+ atomic_dec(&pt->used);
+ } while (idx++, --len);
+ spin_unlock(&pd->lock);
+}
+
+static void gen8_ppgtt_foreach(struct i915_address_space *vm,
+ u64 start, u64 length,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data)
+{
+ start >>= GEN8_PTE_SHIFT;
+ length >>= GEN8_PTE_SHIFT;
+
+ __gen8_ppgtt_foreach(vm, i915_vm_to_ppgtt(vm)->pd,
+ &start, start + length, vm->top,
+ fn, data);
+}
+
static __always_inline u64
gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
struct i915_page_directory *pdp,
@@ -755,6 +803,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
ppgtt->vm.clear_range = gen8_ppgtt_clear;
+ ppgtt->vm.foreach = gen8_ppgtt_foreach;
ppgtt->vm.pte_encode = gen8_pte_encode;
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index edea95b97c36..9bd89f2a01ff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -296,6 +296,13 @@ struct i915_address_space {
u32 flags);
void (*cleanup)(struct i915_address_space *vm);
+ void (*foreach)(struct i915_address_space *vm,
+ u64 start, u64 length,
+ void (*fn)(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data),
+ void *data);
+
struct i915_vma_ops vma_ops;
I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 6/9] drm/i915/gt: Export the pinned context constructor and destructor
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Allow internal clients to create and destroy a pinned context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
v2:
- (Thomas) Export also the pinned context destructor
---
drivers/gpu/drm/i915/gt/intel_engine.h | 11 +++++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 ++++++++++++++---------
2 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..36ea9eb52bb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -19,7 +19,9 @@
#include "intel_workarounds.h"
struct drm_printer;
+struct intel_context;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -256,6 +258,15 @@ struct i915_request *
intel_engine_find_active_request(struct intel_engine_cs *engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name);
+
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..fcbaad18ac91 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -810,11 +810,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
#endif
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -825,6 +827,10 @@ create_pinned_context(struct intel_engine_cs *engine,
__set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
ce->timeline = page_pack_bits(NULL, hwsp);
+ ce->ring = __intel_context_ring_size(ring_size);
+
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
err = intel_context_pin(ce); /* perma-pin so it is always available */
if (err) {
@@ -843,7 +849,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -863,8 +869,9 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
- &kernel, "kernel_context");
+ return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
+ I915_GEM_HWS_SEQNO_ADDR,
+ &kernel, "kernel_context");
}
/**
@@ -907,7 +914,7 @@ static int engine_init_common(struct intel_engine_cs *engine)
return 0;
err_context:
- destroy_pinned_context(ce);
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -969,7 +976,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
fput(engine->default_state);
if (engine->kernel_context)
- destroy_pinned_context(engine->kernel_context);
+ intel_engine_destroy_pinned_context(engine->kernel_context);
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
cleanup_status_page(engine);
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 6/9] drm/i915/gt: Export the pinned context constructor and destructor
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Allow internal clients to create and destroy a pinned context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
v2:
- (Thomas) Export also the pinned context destructor
---
drivers/gpu/drm/i915/gt/intel_engine.h | 11 +++++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 ++++++++++++++---------
2 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 8d9184920c51..36ea9eb52bb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -19,7 +19,9 @@
#include "intel_workarounds.h"
struct drm_printer;
+struct intel_context;
struct intel_gt;
+struct lock_class_key;
/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
* but keeps the logic simple. Indeed, the whole purpose of this macro is just
@@ -256,6 +258,15 @@ struct i915_request *
intel_engine_find_active_request(struct intel_engine_cs *engine);
u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name);
+
+void intel_engine_destroy_pinned_context(struct intel_context *ce);
void intel_engine_init_active(struct intel_engine_cs *engine,
unsigned int subclass);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 9ceddfbb1687..fcbaad18ac91 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -810,11 +810,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
#endif
}
-static struct intel_context *
-create_pinned_context(struct intel_engine_cs *engine,
- unsigned int hwsp,
- struct lock_class_key *key,
- const char *name)
+struct intel_context *
+intel_engine_create_pinned_context(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ unsigned int ring_size,
+ unsigned int hwsp,
+ struct lock_class_key *key,
+ const char *name)
{
struct intel_context *ce;
int err;
@@ -825,6 +827,10 @@ create_pinned_context(struct intel_engine_cs *engine,
__set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
ce->timeline = page_pack_bits(NULL, hwsp);
+ ce->ring = __intel_context_ring_size(ring_size);
+
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(vm);
err = intel_context_pin(ce); /* perma-pin so it is always available */
if (err) {
@@ -843,7 +849,7 @@ create_pinned_context(struct intel_engine_cs *engine,
return ce;
}
-static void destroy_pinned_context(struct intel_context *ce)
+void intel_engine_destroy_pinned_context(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_vma *hwsp = engine->status_page.vma;
@@ -863,8 +869,9 @@ create_kernel_context(struct intel_engine_cs *engine)
{
static struct lock_class_key kernel;
- return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
- &kernel, "kernel_context");
+ return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
+ I915_GEM_HWS_SEQNO_ADDR,
+ &kernel, "kernel_context");
}
/**
@@ -907,7 +914,7 @@ static int engine_init_common(struct intel_engine_cs *engine)
return 0;
err_context:
- destroy_pinned_context(ce);
+ intel_engine_destroy_pinned_context(ce);
return ret;
}
@@ -969,7 +976,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
fput(engine->default_state);
if (engine->kernel_context)
- destroy_pinned_context(engine->kernel_context);
+ intel_engine_destroy_pinned_context(engine->kernel_context);
GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
cleanup_status_page(engine);
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
If we pipeline the PTE updates and then do the copy of those pages
within a single unpreemptible command packet, we can submit the copies
and leave them to be scheduled without having to synchronously wait
under a global lock. In order to manage migration, we need to
preallocate the page tables (and keep them pinned and available for use
at any time), causing a bottleneck for migrations as all clients must
contend on the limited resources. By inlining the ppGTT updates and
performing the blit atomically, each client only owns the PTE while in
use, and so we can reschedule individual operations however we see fit.
And most importantly, we do not need to take a global lock on the shared
vm, and wait until the operation is complete before releasing the lock
for others to claim the PTE for themselves.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
v2:
- Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
- Use intel_engine_destroy_pinned_context() to properly take the pinned
context timeline off the engine list. (CI warning).
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 544 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 45 ++
drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
drivers/gpu/drm/i915/gt/selftest_migrate.c | 291 ++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
9 files changed, 901 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 16a5a006cf7c..95bd38e84625 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -108,6 +108,7 @@ gt-y += \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
+ gt/intel_migrate.o \
gt/intel_mocs.o \
gt/intel_ppgtt.o \
gt/intel_rc6.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 36ea9eb52bb5..62f7440bc111 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -188,6 +188,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
+#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX 0x10
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2694dbb9967e..1c3af0fc0456 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -123,8 +123,10 @@
#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
#define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
#define MI_SEMAPHORE_TOKEN_SHIFT 5
+#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
+#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
#define MI_USE_GGTT (1 << 22) /* g4x+ */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
new file mode 100644
index 000000000000..70776316863d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -0,0 +1,544 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_context.h"
+#include "intel_gpu_commands.h"
+#include "intel_gt.h"
+#include "intel_gtt.h"
+#include "intel_migrate.h"
+#include "intel_ring.h"
+
+struct insert_pte_data {
+ u64 offset;
+ bool is_lmem;
+};
+
+#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+
+static bool engine_supports_migration(struct intel_engine_cs *engine)
+{
+ if (!engine)
+ return false;
+
+ /*
+ * We need the ability to prevent aribtration (MI_ARB_ON_OFF),
+ * the ability to write PTE using inline data (MI_STORE_DATA)
+ * and of course the ability to do the block transfer (blits).
+ */
+ GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);
+
+ return true;
+}
+
+static void insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
+{
+ struct insert_pte_data *d = data;
+
+ vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
+ d->is_lmem ? PTE_LM : 0);
+ d->offset += PAGE_SIZE;
+}
+
+static struct i915_address_space *migrate_vm(struct intel_gt *gt)
+{
+ struct i915_vm_pt_stash stash = {};
+ struct i915_ppgtt *vm;
+ int err;
+ int i;
+
+ /*
+ * We construct a very special VM for use by all migration contexts,
+ * it is kept pinned so that it can be used at any time. As we need
+ * to pre-allocate the page directories for the migration VM, this
+ * limits us to only using a small number of prepared vma.
+ *
+ * To be able to pipeline and reschedule migration operations while
+ * avoiding unnecessary contention on the vm itself, the PTE updates
+ * are inline with the blits. All the blits use the same fixed
+ * addresses, with the backing store redirection being updated on the
+ * fly. Only 2 implicit vma are used for all migration operations.
+ *
+ * We lay the ppGTT out as:
+ *
+ * [0, CHUNK_SZ) -> first object
+ * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object
+ * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE
+ *
+ * By exposing the dma addresses of the page directories themselves
+ * within the ppGTT, we are then able to rewrite the PTE prior to use.
+ * But the PTE update and subsequent migration operation must be atomic,
+ * i.e. within the same non-preemptible window so that we do not switch
+ * to another migration context that overwrites the PTE.
+ *
+ * TODO: Add support for huge LMEM PTEs
+ */
+
+ vm = i915_ppgtt_create(gt);
+ if (IS_ERR(vm))
+ return ERR_CAST(vm);
+
+ if (!vm->vm.allocate_va_range || !vm->vm.foreach) {
+ err = -ENODEV;
+ goto err_vm;
+ }
+
+ /*
+ * Each engine instance is assigned its own chunk in the VM, so
+ * that we can run multiple instances concurrently
+ */
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ struct intel_engine_cs *engine;
+ u64 base = (u64)i << 32;
+ struct insert_pte_data d = {};
+ struct i915_gem_ww_ctx ww;
+ u64 sz;
+
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (!engine_supports_migration(engine))
+ continue;
+
+ /*
+ * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
+ * 4x2 page directories for source/destination.
+ */
+ sz = 2 * CHUNK_SZ;
+ d.offset = base + sz;
+
+ /*
+ * We need another page directory setup so that we can write
+ * the 8x512 PTE in each chunk.
+ */
+ sz += (sz >> 12) * sizeof(u64);
+
+ err = i915_vm_alloc_pt_stash(&vm->vm, &stash, sz);
+ if (err)
+ goto err_vm;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_vm_lock_objects(&vm->vm, &ww);
+ if (err)
+ continue;
+ err = i915_vm_map_pt_stash(&vm->vm, &stash);
+ if (err)
+ continue;
+
+ vm->vm.allocate_va_range(&vm->vm, &stash, base, base + sz);
+ }
+ i915_vm_free_pt_stash(&vm->vm, &stash);
+ if (err)
+ goto err_vm;
+
+ /* Now allow the GPU to rewrite the PTE via its own ppGTT */
+ d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
+ vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
+ }
+
+ return &vm->vm;
+
+err_vm:
+ i915_vm_put(&vm->vm);
+ return ERR_PTR(err);
+}
+
+static struct intel_engine_cs *first_copy_engine(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (engine_supports_migration(engine))
+ return engine;
+ }
+
+ return NULL;
+}
+
+static struct intel_context *pinned_context(struct intel_gt *gt)
+{
+ static struct lock_class_key key;
+ struct intel_engine_cs *engine;
+ struct i915_address_space *vm;
+ struct intel_context *ce;
+
+ engine = first_copy_engine(gt);
+ if (!engine)
+ return ERR_PTR(-ENODEV);
+
+ vm = migrate_vm(gt);
+ if (IS_ERR(vm))
+ return ERR_CAST(vm);
+
+ ce = intel_engine_create_pinned_context(engine, vm, SZ_512K,
+ I915_GEM_HWS_MIGRATE,
+ &key, "migrate");
+ i915_vm_put(ce->vm);
+ return ce;
+}
+
+int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt)
+{
+ struct intel_context *ce;
+
+ memset(m, 0, sizeof(*m));
+
+ ce = pinned_context(gt);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ m->context = ce;
+ return 0;
+}
+
+static int random_index(unsigned int max)
+{
+ return upper_32_bits(mul_u32_u32(get_random_u32(), max));
+}
+
+static struct intel_context *__migrate_engines(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engines[MAX_ENGINE_INSTANCE];
+ struct intel_engine_cs *engine;
+ unsigned int count, i;
+
+ count = 0;
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (engine_supports_migration(engine))
+ engines[count++] = engine;
+ }
+
+ return intel_context_create(engines[random_index(count)]);
+}
+
+struct intel_context *intel_migrate_create_context(struct intel_migrate *m)
+{
+ struct intel_context *ce;
+
+ /*
+ * We randomly distribute contexts across the engines upon constrction,
+ * as they all share the same pinned vm, and so in order to allow
+ * multiple blits to run in parallel, we must construct each blit
+ * to use a different range of the vm for its GTT. This has to be
+ * known at construction, so we can not use the late greedy load
+ * balancing of the virtual-engine.
+ */
+ ce = __migrate_engines(m->context->engine->gt);
+ if (IS_ERR(ce))
+ return ce;
+
+ ce->ring = __intel_context_ring_size(SZ_256K);
+
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(m->context->vm);
+
+ return ce;
+}
+
+static inline struct sgt_dma sg_sgt(struct scatterlist *sg)
+{
+ dma_addr_t addr = sg_dma_address(sg);
+
+ return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
+}
+
+static int emit_no_arbitration(struct i915_request *rq)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /* Explicitly disable preemption for this request. */
+ *cs++ = MI_ARB_ON_OFF;
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int emit_pte(struct i915_request *rq,
+ struct sgt_dma *it,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u64 offset,
+ int length)
+{
+ const u64 encode = rq->context->vm->pte_encode(0, cache_level,
+ is_lmem ? PTE_LM : 0);
+ struct intel_ring *ring = rq->ring;
+ int total = 0;
+ u32 *hdr, *cs;
+ int pkt;
+
+ GEM_BUG_ON(INTEL_GEN(rq->engine->i915) < 8);
+
+ /* Compute the page directory offset for the target address range */
+ offset += (u64)rq->engine->instance << 32;
+ offset >>= 12;
+ offset *= sizeof(u64);
+ offset += 2 * CHUNK_SZ;
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /* Pack as many PTE updates as possible into a single MI command */
+ pkt = min_t(int, 0x400, ring->space / sizeof(u32) + 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ hdr = cs;
+ *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+
+ do {
+ if (cs - hdr >= pkt) {
+ *hdr += cs - hdr - 2;
+ *cs++ = MI_NOOP;
+
+ ring->emit = (void *)cs - ring->vaddr;
+ intel_ring_advance(rq, cs);
+ intel_ring_update_space(ring);
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ pkt = min_t(int, 0x400, ring->space / sizeof(u32) + 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ hdr = cs;
+ *cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+ }
+
+ *cs++ = lower_32_bits(encode | it->dma);
+ *cs++ = upper_32_bits(encode | it->dma);
+
+ offset += 8;
+ total += I915_GTT_PAGE_SIZE;
+
+ it->dma += I915_GTT_PAGE_SIZE;
+ if (it->dma >= it->max) {
+ it->sg = __sg_next(it->sg);
+ if (!it->sg || sg_dma_len(it->sg) == 0)
+ break;
+
+ it->dma = sg_dma_address(it->sg);
+ it->max = it->dma + sg_dma_len(it->sg);
+ }
+ } while (total < length);
+
+ *hdr += cs - hdr - 2;
+ *cs++ = MI_NOOP;
+
+ ring->emit = (void *)cs - ring->vaddr;
+ intel_ring_advance(rq, cs);
+ intel_ring_update_space(ring);
+
+ return total;
+}
+
+static bool wa_1209644611_applies(int gen, u32 size)
+{
+ u32 height = size >> PAGE_SHIFT;
+
+ if (gen != 11)
+ return false;
+
+ return height % 4 == 3 && height <= 8;
+}
+
+static int emit_copy(struct i915_request *rq, int size)
+{
+ const int gen = INTEL_GEN(rq->engine->i915);
+ u32 instance = rq->engine->instance;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, gen >= 8 ? 10 : 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ if (gen >= 9 && !wa_1209644611_applies(gen, size)) {
+ *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+ *cs++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = instance;
+ *cs++ = 0;
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ *cs++ = instance;
+ } else if (gen >= 8) {
+ *cs++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = instance;
+ *cs++ = 0;
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ *cs++ = instance;
+ } else {
+ GEM_BUG_ON(instance);
+ *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ }
+
+ intel_ring_advance(rq, cs);
+ return 0;
+}
+
+int
+intel_context_migrate_copy(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out)
+{
+ struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
+ struct i915_request *rq;
+ int err;
+
+ *out = NULL;
+
+ /* GEM_BUG_ON(ce->vm != migrate_vm); */
+
+ GEM_BUG_ON(ce->ring->size < SZ_64K);
+
+ do {
+ int len;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ if (await) {
+ err = i915_request_await_dma_fence(rq, await);
+ if (err)
+ goto out_rq;
+
+ if (rq->engine->emit_init_breadcrumb) {
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ await = NULL;
+ }
+
+ /* The PTE updates + copy must not be interrupted. */
+ err = emit_no_arbitration(rq);
+ if (err)
+ goto out_rq;
+
+ len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem, 0,
+ CHUNK_SZ);
+ if (len <= 0) {
+ err = len;
+ goto out_rq;
+ }
+
+ err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
+ CHUNK_SZ, len);
+ if (err < 0)
+ goto out_rq;
+ if (err < len) {
+ err = -EINVAL;
+ goto out_rq;
+ }
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ err = emit_copy(rq, len);
+
+ /* Arbitration is re-enabled between requests. */
+out_rq:
+ if (*out)
+ i915_request_put(*out);
+ *out = i915_request_get(rq);
+ i915_request_add(rq);
+ if (err || !it_src.sg || !sg_dma_len(it_src.sg))
+ break;
+
+ cond_resched();
+ } while (1);
+
+out_ce:
+ return err;
+}
+
+int intel_migrate_copy(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out)
+{
+ struct intel_context *ce;
+ int err;
+
+ *out = NULL;
+ if (!m->context)
+ return -ENODEV;
+
+ ce = intel_migrate_create_context(m);
+ if (IS_ERR(ce))
+ ce = intel_context_get(m->context);
+ GEM_BUG_ON(IS_ERR(ce));
+
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ err = intel_context_migrate_copy(ce, await,
+ src, src_cache_level, src_is_lmem,
+ dst, dst_cache_level, dst_is_lmem,
+ out);
+
+ intel_context_unpin(ce);
+out:
+ intel_context_put(ce);
+ return err;
+}
+
+void intel_migrate_fini(struct intel_migrate *m)
+{
+ struct intel_context *ce;
+
+ ce = fetch_and_zero(&m->context);
+ if (!ce)
+ return;
+
+ intel_engine_destroy_pinned_context(ce);
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_migrate.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.h b/drivers/gpu/drm/i915/gt/intel_migrate.h
new file mode 100644
index 000000000000..32c61190ed73
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_MIGRATE__
+#define __INTEL_MIGRATE__
+
+#include "intel_migrate_types.h"
+
+struct dma_fence;
+struct i915_request;
+struct i915_gem_ww_ctx;
+struct intel_gt;
+struct scatterlist;
+enum i915_cache_level;
+
+int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt);
+
+struct intel_context *intel_migrate_create_context(struct intel_migrate *m);
+
+int intel_migrate_copy(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out);
+
+int intel_context_migrate_copy(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out);
+
+void intel_migrate_fini(struct intel_migrate *m);
+
+#endif /* __INTEL_MIGRATE__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate_types.h b/drivers/gpu/drm/i915/gt/intel_migrate_types.h
new file mode 100644
index 000000000000..d98230597f42
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate_types.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_MIGRATE_TYPES__
+#define __INTEL_MIGRATE_TYPES__
+
+struct intel_context;
+
+struct intel_migrate {
+ struct intel_context *context;
+};
+
+#endif /* __INTEL_MIGRATE_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h
index dbf5f14a136f..1b32dadfb8c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.h
+++ b/drivers/gpu/drm/i915/gt/intel_ring.h
@@ -49,6 +49,7 @@ static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
* intel_ring_begin()).
*/
GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
+ GEM_BUG_ON(!IS_ALIGNED(rq->ring->emit, 8)); /* RING_TAIL qword align */
}
static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
new file mode 100644
index 000000000000..9784d149ebf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "selftests/i915_random.h"
+
+static const unsigned int sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ CHUNK_SZ - SZ_4K,
+ CHUNK_SZ,
+ CHUNK_SZ + SZ_4K,
+ SZ_64M,
+};
+
+static struct drm_i915_gem_object *
+create_lmem_or_internal(struct drm_i915_private *i915, size_t size)
+{
+ if (HAS_LMEM(i915)) {
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_lmem(i915, size, 0);
+ if (!IS_ERR(obj))
+ return obj;
+ }
+
+ return i915_gem_object_create_internal(i915, size);
+}
+
+static int copy(struct intel_migrate *migrate,
+ int (*fn)(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out),
+ u32 sz, struct rnd_state *prng)
+{
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *src, *dst;
+ struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
+ u32 *vaddr;
+ int err = 0;
+ int i;
+
+ src = create_lmem_or_internal(i915, sz);
+ if (IS_ERR(src))
+ return 0;
+
+ dst = i915_gem_object_create_internal(i915, sz);
+ if (IS_ERR(dst))
+ goto err_free_src;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_gem_object_lock(src, &ww);
+ if (err)
+ continue;
+
+ err = i915_gem_object_lock(dst, &ww);
+ if (err)
+ continue;
+
+ vaddr = i915_gem_object_pin_map(src, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ continue;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = i;
+ i915_gem_object_flush_map(src);
+
+ vaddr = i915_gem_object_pin_map(dst, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto unpin_src;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = ~i;
+ i915_gem_object_flush_map(dst);
+
+ err = fn(migrate, &ww, src, dst, &rq);
+ if (!err)
+ continue;
+
+ if (err != -EDEADLK && err != -EINTR && err != -ERESTARTSYS)
+ pr_err("%ps failed, size: %u\n", fn, sz);
+ if (rq) {
+ i915_request_wait(rq, 0, HZ);
+ i915_request_put(rq);
+ }
+ i915_gem_object_unpin_map(dst);
+unpin_src:
+ i915_gem_object_unpin_map(src);
+ }
+ if (err)
+ goto err_out;
+
+ if (rq) {
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ pr_err("%ps timed out, size: %u\n", fn, sz);
+ err = -ETIME;
+ }
+ i915_request_put(rq);
+ }
+
+ for (i = 0; !err && i < sz / PAGE_SIZE; i++) {
+ int x = i * 1024 + i915_prandom_u32_max_state(1024, prng);
+
+ if (vaddr[x] != x) {
+ pr_err("%ps failed, size: %u, offset: %zu\n",
+ fn, sz, x * sizeof(u32));
+ igt_hexdump(vaddr + i * 1024, 4096);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(dst);
+ i915_gem_object_unpin_map(src);
+
+err_out:
+ i915_gem_object_put(dst);
+err_free_src:
+ i915_gem_object_put(src);
+
+ return err;
+}
+
+static int __migrate_copy(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out)
+{
+ return intel_migrate_copy(migrate, ww, NULL,
+ src->mm.pages->sgl, src->cache_level,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl, dst->cache_level,
+ i915_gem_object_is_lmem(dst),
+ out);
+}
+
+static int __global_copy(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out)
+{
+ return intel_context_migrate_copy(migrate->context, NULL,
+ src->mm.pages->sgl, src->cache_level,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl, dst->cache_level,
+ i915_gem_object_is_lmem(dst),
+ out);
+}
+
+static int
+migrate_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return copy(migrate, __migrate_copy, sz, prng);
+}
+
+static int
+global_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return copy(migrate, __global_copy, sz, prng);
+}
+
+static int live_migrate_copy(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ int err;
+
+ err = migrate_copy(migrate, sizes[i], &prng);
+ if (err == 0)
+ err = global_copy(migrate, sizes[i], &prng);
+ i915_gem_drain_freed_objects(i915);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+struct threaded_migrate {
+ struct intel_migrate *migrate;
+ struct task_struct *tsk;
+ struct rnd_state prng;
+};
+
+static int threaded_migrate(struct intel_migrate *migrate,
+ int (*fn)(void *arg),
+ unsigned int flags)
+{
+ const unsigned int n_cpus = num_online_cpus() + 1;
+ struct threaded_migrate *thread;
+ I915_RND_STATE(prng);
+ unsigned int i;
+ int err = 0;
+
+ thread = kcalloc(n_cpus, sizeof(*thread), GFP_KERNEL);
+ if (!thread)
+ return 0;
+
+ for (i = 0; i < n_cpus; ++i) {
+ struct task_struct *tsk;
+
+ thread[i].migrate = migrate;
+ thread[i].prng =
+ I915_RND_STATE_INITIALIZER(prandom_u32_state(&prng));
+
+ tsk = kthread_run(fn, &thread[i], "igt-%d", i);
+ if (IS_ERR(tsk)) {
+ err = PTR_ERR(tsk);
+ break;
+ }
+
+ get_task_struct(tsk);
+ thread[i].tsk = tsk;
+ }
+
+ msleep(10); /* start all threads before we kthread_stop() */
+
+ for (i = 0; i < n_cpus; ++i) {
+ struct task_struct *tsk = thread[i].tsk;
+ int status;
+
+ if (IS_ERR_OR_NULL(tsk))
+ continue;
+
+ status = kthread_stop(tsk);
+ if (status && !err)
+ err = status;
+
+ put_task_struct(tsk);
+ }
+
+ kfree(thread);
+ return err;
+}
+
+static int __thread_migrate_copy(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return migrate_copy(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_migrate_copy(void *arg)
+{
+ return threaded_migrate(arg, __thread_migrate_copy, 0);
+}
+
+static int __thread_global_copy(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return global_copy(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_global_copy(void *arg)
+{
+ return threaded_migrate(arg, __thread_global_copy, 0);
+}
+
+int intel_migrate_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_migrate_copy),
+ SUBTEST(thread_migrate_copy),
+ SUBTEST(thread_global_copy),
+ };
+ struct intel_migrate m;
+ int err;
+
+ if (intel_migrate_init(&m, &i915->gt))
+ return 0;
+
+ err = i915_subtests(tests, &m);
+ intel_migrate_fini(&m);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..be5e0191eaea 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(migrate, intel_migrate_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
If we pipeline the PTE updates and then do the copy of those pages
within a single unpreemptible command packet, we can submit the copies
and leave them to be scheduled without having to synchronously wait
under a global lock. In order to manage migration, we need to
preallocate the page tables (and keep them pinned and available for use
at any time), causing a bottleneck for migrations as all clients must
contend on the limited resources. By inlining the ppGTT updates and
performing the blit atomically, each client only owns the PTE while in
use, and so we can reschedule individual operations however we see fit.
And most importantly, we do not need to take a global lock on the shared
vm, and wait until the operation is complete before releasing the lock
for others to claim the PTE for themselves.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
v2:
- Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
- Use intel_engine_destroy_pinned_context() to properly take the pinned
context timeline off the engine list. (CI warning).
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 544 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 45 ++
drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
drivers/gpu/drm/i915/gt/selftest_migrate.c | 291 ++++++++++
.../drm/i915/selftests/i915_live_selftests.h | 1 +
9 files changed, 901 insertions(+)
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 16a5a006cf7c..95bd38e84625 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -108,6 +108,7 @@ gt-y += \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
+ gt/intel_migrate.o \
gt/intel_mocs.o \
gt/intel_ppgtt.o \
gt/intel_rc6.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 36ea9eb52bb5..62f7440bc111 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -188,6 +188,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
#define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
#define I915_GEM_HWS_SEQNO 0x40
#define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
+#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
#define I915_GEM_HWS_SCRATCH 0x80
#define I915_HWS_CSB_BUF0_INDEX 0x10
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 2694dbb9967e..1c3af0fc0456 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -123,8 +123,10 @@
#define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
#define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
#define MI_SEMAPHORE_TOKEN_SHIFT 5
+#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
#define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
+#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
#define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
#define MI_USE_GGTT (1 << 22) /* g4x+ */
#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
new file mode 100644
index 000000000000..70776316863d
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -0,0 +1,544 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_context.h"
+#include "intel_gpu_commands.h"
+#include "intel_gt.h"
+#include "intel_gtt.h"
+#include "intel_migrate.h"
+#include "intel_ring.h"
+
+struct insert_pte_data {
+ u64 offset;
+ bool is_lmem;
+};
+
+#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
+
+static bool engine_supports_migration(struct intel_engine_cs *engine)
+{
+ if (!engine)
+ return false;
+
+ /*
+ * We need the ability to prevent aribtration (MI_ARB_ON_OFF),
+ * the ability to write PTE using inline data (MI_STORE_DATA)
+ * and of course the ability to do the block transfer (blits).
+ */
+ GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);
+
+ return true;
+}
+
+static void insert_pte(struct i915_address_space *vm,
+ struct i915_page_table *pt,
+ void *data)
+{
+ struct insert_pte_data *d = data;
+
+ vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
+ d->is_lmem ? PTE_LM : 0);
+ d->offset += PAGE_SIZE;
+}
+
+static struct i915_address_space *migrate_vm(struct intel_gt *gt)
+{
+ struct i915_vm_pt_stash stash = {};
+ struct i915_ppgtt *vm;
+ int err;
+ int i;
+
+ /*
+ * We construct a very special VM for use by all migration contexts,
+ * it is kept pinned so that it can be used at any time. As we need
+ * to pre-allocate the page directories for the migration VM, this
+ * limits us to only using a small number of prepared vma.
+ *
+ * To be able to pipeline and reschedule migration operations while
+ * avoiding unnecessary contention on the vm itself, the PTE updates
+ * are inline with the blits. All the blits use the same fixed
+ * addresses, with the backing store redirection being updated on the
+ * fly. Only 2 implicit vma are used for all migration operations.
+ *
+ * We lay the ppGTT out as:
+ *
+ * [0, CHUNK_SZ) -> first object
+ * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object
+ * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE
+ *
+ * By exposing the dma addresses of the page directories themselves
+ * within the ppGTT, we are then able to rewrite the PTE prior to use.
+ * But the PTE update and subsequent migration operation must be atomic,
+ * i.e. within the same non-preemptible window so that we do not switch
+ * to another migration context that overwrites the PTE.
+ *
+ * TODO: Add support for huge LMEM PTEs
+ */
+
+ vm = i915_ppgtt_create(gt);
+ if (IS_ERR(vm))
+ return ERR_CAST(vm);
+
+ if (!vm->vm.allocate_va_range || !vm->vm.foreach) {
+ err = -ENODEV;
+ goto err_vm;
+ }
+
+ /*
+ * Each engine instance is assigned its own chunk in the VM, so
+ * that we can run multiple instances concurrently
+ */
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ struct intel_engine_cs *engine;
+ u64 base = (u64)i << 32;
+ struct insert_pte_data d = {};
+ struct i915_gem_ww_ctx ww;
+ u64 sz;
+
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (!engine_supports_migration(engine))
+ continue;
+
+ /*
+ * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
+ * 4x2 page directories for source/destination.
+ */
+ sz = 2 * CHUNK_SZ;
+ d.offset = base + sz;
+
+ /*
+ * We need another page directory setup so that we can write
+ * the 8x512 PTE in each chunk.
+ */
+ sz += (sz >> 12) * sizeof(u64);
+
+ err = i915_vm_alloc_pt_stash(&vm->vm, &stash, sz);
+ if (err)
+ goto err_vm;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_vm_lock_objects(&vm->vm, &ww);
+ if (err)
+ continue;
+ err = i915_vm_map_pt_stash(&vm->vm, &stash);
+ if (err)
+ continue;
+
+ vm->vm.allocate_va_range(&vm->vm, &stash, base, base + sz);
+ }
+ i915_vm_free_pt_stash(&vm->vm, &stash);
+ if (err)
+ goto err_vm;
+
+ /* Now allow the GPU to rewrite the PTE via its own ppGTT */
+ d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
+ vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
+ }
+
+ return &vm->vm;
+
+err_vm:
+ i915_vm_put(&vm->vm);
+ return ERR_PTR(err);
+}
+
+static struct intel_engine_cs *first_copy_engine(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engine;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (engine_supports_migration(engine))
+ return engine;
+ }
+
+ return NULL;
+}
+
+static struct intel_context *pinned_context(struct intel_gt *gt)
+{
+ static struct lock_class_key key;
+ struct intel_engine_cs *engine;
+ struct i915_address_space *vm;
+ struct intel_context *ce;
+
+ engine = first_copy_engine(gt);
+ if (!engine)
+ return ERR_PTR(-ENODEV);
+
+ vm = migrate_vm(gt);
+ if (IS_ERR(vm))
+ return ERR_CAST(vm);
+
+ ce = intel_engine_create_pinned_context(engine, vm, SZ_512K,
+ I915_GEM_HWS_MIGRATE,
+ &key, "migrate");
+ i915_vm_put(ce->vm);
+ return ce;
+}
+
+int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt)
+{
+ struct intel_context *ce;
+
+ memset(m, 0, sizeof(*m));
+
+ ce = pinned_context(gt);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ m->context = ce;
+ return 0;
+}
+
+static int random_index(unsigned int max)
+{
+ return upper_32_bits(mul_u32_u32(get_random_u32(), max));
+}
+
+static struct intel_context *__migrate_engines(struct intel_gt *gt)
+{
+ struct intel_engine_cs *engines[MAX_ENGINE_INSTANCE];
+ struct intel_engine_cs *engine;
+ unsigned int count, i;
+
+ count = 0;
+ for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
+ engine = gt->engine_class[COPY_ENGINE_CLASS][i];
+ if (engine_supports_migration(engine))
+ engines[count++] = engine;
+ }
+
+ return intel_context_create(engines[random_index(count)]);
+}
+
+struct intel_context *intel_migrate_create_context(struct intel_migrate *m)
+{
+ struct intel_context *ce;
+
+ /*
+ * We randomly distribute contexts across the engines upon constrction,
+ * as they all share the same pinned vm, and so in order to allow
+ * multiple blits to run in parallel, we must construct each blit
+ * to use a different range of the vm for its GTT. This has to be
+ * known at construction, so we can not use the late greedy load
+ * balancing of the virtual-engine.
+ */
+ ce = __migrate_engines(m->context->engine->gt);
+ if (IS_ERR(ce))
+ return ce;
+
+ ce->ring = __intel_context_ring_size(SZ_256K);
+
+ i915_vm_put(ce->vm);
+ ce->vm = i915_vm_get(m->context->vm);
+
+ return ce;
+}
+
+static inline struct sgt_dma sg_sgt(struct scatterlist *sg)
+{
+ dma_addr_t addr = sg_dma_address(sg);
+
+ return (struct sgt_dma){ sg, addr, addr + sg_dma_len(sg) };
+}
+
+static int emit_no_arbitration(struct i915_request *rq)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 2);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /* Explicitly disable preemption for this request. */
+ *cs++ = MI_ARB_ON_OFF;
+ *cs++ = MI_NOOP;
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
+static int emit_pte(struct i915_request *rq,
+ struct sgt_dma *it,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u64 offset,
+ int length)
+{
+ const u64 encode = rq->context->vm->pte_encode(0, cache_level,
+ is_lmem ? PTE_LM : 0);
+ struct intel_ring *ring = rq->ring;
+ int total = 0;
+ u32 *hdr, *cs;
+ int pkt;
+
+ GEM_BUG_ON(INTEL_GEN(rq->engine->i915) < 8);
+
+ /* Compute the page directory offset for the target address range */
+ offset += (u64)rq->engine->instance << 32;
+ offset >>= 12;
+ offset *= sizeof(u64);
+ offset += 2 * CHUNK_SZ;
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ /* Pack as many PTE updates as possible into a single MI command */
+ pkt = min_t(int, 0x400, ring->space / sizeof(u32) + 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ hdr = cs;
+ *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+
+ do {
+ if (cs - hdr >= pkt) {
+ *hdr += cs - hdr - 2;
+ *cs++ = MI_NOOP;
+
+ ring->emit = (void *)cs - ring->vaddr;
+ intel_ring_advance(rq, cs);
+ intel_ring_update_space(ring);
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ pkt = min_t(int, 0x400, ring->space / sizeof(u32) + 5);
+ pkt = min_t(int, pkt, (ring->size - ring->emit) / sizeof(u32) + 5);
+
+ hdr = cs;
+ *cs++ = MI_STORE_DATA_IMM | REG_BIT(21);
+ *cs++ = lower_32_bits(offset);
+ *cs++ = upper_32_bits(offset);
+ }
+
+ *cs++ = lower_32_bits(encode | it->dma);
+ *cs++ = upper_32_bits(encode | it->dma);
+
+ offset += 8;
+ total += I915_GTT_PAGE_SIZE;
+
+ it->dma += I915_GTT_PAGE_SIZE;
+ if (it->dma >= it->max) {
+ it->sg = __sg_next(it->sg);
+ if (!it->sg || sg_dma_len(it->sg) == 0)
+ break;
+
+ it->dma = sg_dma_address(it->sg);
+ it->max = it->dma + sg_dma_len(it->sg);
+ }
+ } while (total < length);
+
+ *hdr += cs - hdr - 2;
+ *cs++ = MI_NOOP;
+
+ ring->emit = (void *)cs - ring->vaddr;
+ intel_ring_advance(rq, cs);
+ intel_ring_update_space(ring);
+
+ return total;
+}
+
+static bool wa_1209644611_applies(int gen, u32 size)
+{
+ u32 height = size >> PAGE_SHIFT;
+
+ if (gen != 11)
+ return false;
+
+ return height % 4 == 3 && height <= 8;
+}
+
+static int emit_copy(struct i915_request *rq, int size)
+{
+ const int gen = INTEL_GEN(rq->engine->i915);
+ u32 instance = rq->engine->instance;
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, gen >= 8 ? 10 : 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ if (gen >= 9 && !wa_1209644611_applies(gen, size)) {
+ *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+ *cs++ = BLT_DEPTH_32 | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = instance;
+ *cs++ = 0;
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ *cs++ = instance;
+ } else if (gen >= 8) {
+ *cs++ = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (10 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = instance;
+ *cs++ = 0;
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ *cs++ = instance;
+ } else {
+ GEM_BUG_ON(instance);
+ *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | PAGE_SIZE;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE;
+ *cs++ = CHUNK_SZ; /* dst offset */
+ *cs++ = PAGE_SIZE;
+ *cs++ = 0; /* src offset */
+ }
+
+ intel_ring_advance(rq, cs);
+ return 0;
+}
+
+int
+intel_context_migrate_copy(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out)
+{
+ struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
+ struct i915_request *rq;
+ int err;
+
+ *out = NULL;
+
+ /* GEM_BUG_ON(ce->vm != migrate_vm); */
+
+ GEM_BUG_ON(ce->ring->size < SZ_64K);
+
+ do {
+ int len;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ if (await) {
+ err = i915_request_await_dma_fence(rq, await);
+ if (err)
+ goto out_rq;
+
+ if (rq->engine->emit_init_breadcrumb) {
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ await = NULL;
+ }
+
+ /* The PTE updates + copy must not be interrupted. */
+ err = emit_no_arbitration(rq);
+ if (err)
+ goto out_rq;
+
+ len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem, 0,
+ CHUNK_SZ);
+ if (len <= 0) {
+ err = len;
+ goto out_rq;
+ }
+
+ err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
+ CHUNK_SZ, len);
+ if (err < 0)
+ goto out_rq;
+ if (err < len) {
+ err = -EINVAL;
+ goto out_rq;
+ }
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ err = emit_copy(rq, len);
+
+ /* Arbitration is re-enabled between requests. */
+out_rq:
+ if (*out)
+ i915_request_put(*out);
+ *out = i915_request_get(rq);
+ i915_request_add(rq);
+ if (err || !it_src.sg || !sg_dma_len(it_src.sg))
+ break;
+
+ cond_resched();
+ } while (1);
+
+out_ce:
+ return err;
+}
+
+int intel_migrate_copy(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out)
+{
+ struct intel_context *ce;
+ int err;
+
+ *out = NULL;
+ if (!m->context)
+ return -ENODEV;
+
+ ce = intel_migrate_create_context(m);
+ if (IS_ERR(ce))
+ ce = intel_context_get(m->context);
+ GEM_BUG_ON(IS_ERR(ce));
+
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ err = intel_context_migrate_copy(ce, await,
+ src, src_cache_level, src_is_lmem,
+ dst, dst_cache_level, dst_is_lmem,
+ out);
+
+ intel_context_unpin(ce);
+out:
+ intel_context_put(ce);
+ return err;
+}
+
+void intel_migrate_fini(struct intel_migrate *m)
+{
+ struct intel_context *ce;
+
+ ce = fetch_and_zero(&m->context);
+ if (!ce)
+ return;
+
+ intel_engine_destroy_pinned_context(ce);
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_migrate.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.h b/drivers/gpu/drm/i915/gt/intel_migrate.h
new file mode 100644
index 000000000000..32c61190ed73
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_MIGRATE__
+#define __INTEL_MIGRATE__
+
+#include "intel_migrate_types.h"
+
+struct dma_fence;
+struct i915_request;
+struct i915_gem_ww_ctx;
+struct intel_gt;
+struct scatterlist;
+enum i915_cache_level;
+
+int intel_migrate_init(struct intel_migrate *m, struct intel_gt *gt);
+
+struct intel_context *intel_migrate_create_context(struct intel_migrate *m);
+
+int intel_migrate_copy(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out);
+
+int intel_context_migrate_copy(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ struct i915_request **out);
+
+void intel_migrate_fini(struct intel_migrate *m);
+
+#endif /* __INTEL_MIGRATE__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate_types.h b/drivers/gpu/drm/i915/gt/intel_migrate_types.h
new file mode 100644
index 000000000000..d98230597f42
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_migrate_types.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef __INTEL_MIGRATE_TYPES__
+#define __INTEL_MIGRATE_TYPES__
+
+struct intel_context;
+
+struct intel_migrate {
+ struct intel_context *context;
+};
+
+#endif /* __INTEL_MIGRATE_TYPES__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.h b/drivers/gpu/drm/i915/gt/intel_ring.h
index dbf5f14a136f..1b32dadfb8c3 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.h
+++ b/drivers/gpu/drm/i915/gt/intel_ring.h
@@ -49,6 +49,7 @@ static inline void intel_ring_advance(struct i915_request *rq, u32 *cs)
* intel_ring_begin()).
*/
GEM_BUG_ON((rq->ring->vaddr + rq->ring->emit) != cs);
+ GEM_BUG_ON(!IS_ALIGNED(rq->ring->emit, 8)); /* RING_TAIL qword align */
}
static inline u32 intel_ring_wrap(const struct intel_ring *ring, u32 pos)
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
new file mode 100644
index 000000000000..9784d149ebf1
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -0,0 +1,291 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "selftests/i915_random.h"
+
+static const unsigned int sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ CHUNK_SZ - SZ_4K,
+ CHUNK_SZ,
+ CHUNK_SZ + SZ_4K,
+ SZ_64M,
+};
+
+static struct drm_i915_gem_object *
+create_lmem_or_internal(struct drm_i915_private *i915, size_t size)
+{
+ if (HAS_LMEM(i915)) {
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_lmem(i915, size, 0);
+ if (!IS_ERR(obj))
+ return obj;
+ }
+
+ return i915_gem_object_create_internal(i915, size);
+}
+
+static int copy(struct intel_migrate *migrate,
+ int (*fn)(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out),
+ u32 sz, struct rnd_state *prng)
+{
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *src, *dst;
+ struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
+ u32 *vaddr;
+ int err = 0;
+ int i;
+
+ src = create_lmem_or_internal(i915, sz);
+ if (IS_ERR(src))
+ return 0;
+
+ dst = i915_gem_object_create_internal(i915, sz);
+ if (IS_ERR(dst))
+ goto err_free_src;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_gem_object_lock(src, &ww);
+ if (err)
+ continue;
+
+ err = i915_gem_object_lock(dst, &ww);
+ if (err)
+ continue;
+
+ vaddr = i915_gem_object_pin_map(src, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ continue;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = i;
+ i915_gem_object_flush_map(src);
+
+ vaddr = i915_gem_object_pin_map(dst, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ goto unpin_src;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = ~i;
+ i915_gem_object_flush_map(dst);
+
+ err = fn(migrate, &ww, src, dst, &rq);
+ if (!err)
+ continue;
+
+ if (err != -EDEADLK && err != -EINTR && err != -ERESTARTSYS)
+ pr_err("%ps failed, size: %u\n", fn, sz);
+ if (rq) {
+ i915_request_wait(rq, 0, HZ);
+ i915_request_put(rq);
+ }
+ i915_gem_object_unpin_map(dst);
+unpin_src:
+ i915_gem_object_unpin_map(src);
+ }
+ if (err)
+ goto err_out;
+
+ if (rq) {
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ pr_err("%ps timed out, size: %u\n", fn, sz);
+ err = -ETIME;
+ }
+ i915_request_put(rq);
+ }
+
+ for (i = 0; !err && i < sz / PAGE_SIZE; i++) {
+ int x = i * 1024 + i915_prandom_u32_max_state(1024, prng);
+
+ if (vaddr[x] != x) {
+ pr_err("%ps failed, size: %u, offset: %zu\n",
+ fn, sz, x * sizeof(u32));
+ igt_hexdump(vaddr + i * 1024, 4096);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(dst);
+ i915_gem_object_unpin_map(src);
+
+err_out:
+ i915_gem_object_put(dst);
+err_free_src:
+ i915_gem_object_put(src);
+
+ return err;
+}
+
+static int __migrate_copy(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out)
+{
+ return intel_migrate_copy(migrate, ww, NULL,
+ src->mm.pages->sgl, src->cache_level,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl, dst->cache_level,
+ i915_gem_object_is_lmem(dst),
+ out);
+}
+
+static int __global_copy(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *src,
+ struct drm_i915_gem_object *dst,
+ struct i915_request **out)
+{
+ return intel_context_migrate_copy(migrate->context, NULL,
+ src->mm.pages->sgl, src->cache_level,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl, dst->cache_level,
+ i915_gem_object_is_lmem(dst),
+ out);
+}
+
+static int
+migrate_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return copy(migrate, __migrate_copy, sz, prng);
+}
+
+static int
+global_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return copy(migrate, __global_copy, sz, prng);
+}
+
+static int live_migrate_copy(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ int err;
+
+ err = migrate_copy(migrate, sizes[i], &prng);
+ if (err == 0)
+ err = global_copy(migrate, sizes[i], &prng);
+ i915_gem_drain_freed_objects(i915);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+struct threaded_migrate {
+ struct intel_migrate *migrate;
+ struct task_struct *tsk;
+ struct rnd_state prng;
+};
+
+static int threaded_migrate(struct intel_migrate *migrate,
+ int (*fn)(void *arg),
+ unsigned int flags)
+{
+ const unsigned int n_cpus = num_online_cpus() + 1;
+ struct threaded_migrate *thread;
+ I915_RND_STATE(prng);
+ unsigned int i;
+ int err = 0;
+
+ thread = kcalloc(n_cpus, sizeof(*thread), GFP_KERNEL);
+ if (!thread)
+ return 0;
+
+ for (i = 0; i < n_cpus; ++i) {
+ struct task_struct *tsk;
+
+ thread[i].migrate = migrate;
+ thread[i].prng =
+ I915_RND_STATE_INITIALIZER(prandom_u32_state(&prng));
+
+ tsk = kthread_run(fn, &thread[i], "igt-%d", i);
+ if (IS_ERR(tsk)) {
+ err = PTR_ERR(tsk);
+ break;
+ }
+
+ get_task_struct(tsk);
+ thread[i].tsk = tsk;
+ }
+
+ msleep(10); /* start all threads before we kthread_stop() */
+
+ for (i = 0; i < n_cpus; ++i) {
+ struct task_struct *tsk = thread[i].tsk;
+ int status;
+
+ if (IS_ERR_OR_NULL(tsk))
+ continue;
+
+ status = kthread_stop(tsk);
+ if (status && !err)
+ err = status;
+
+ put_task_struct(tsk);
+ }
+
+ kfree(thread);
+ return err;
+}
+
+static int __thread_migrate_copy(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return migrate_copy(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_migrate_copy(void *arg)
+{
+ return threaded_migrate(arg, __thread_migrate_copy, 0);
+}
+
+static int __thread_global_copy(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return global_copy(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_global_copy(void *arg)
+{
+ return threaded_migrate(arg, __thread_global_copy, 0);
+}
+
+int intel_migrate_live_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(live_migrate_copy),
+ SUBTEST(thread_migrate_copy),
+ SUBTEST(thread_global_copy),
+ };
+ struct intel_migrate m;
+ int err;
+
+ if (intel_migrate_init(&m, &i915->gt))
+ return 0;
+
+ err = i915_subtests(tests, &m);
+ intel_migrate_fini(&m);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index a92c0e9b7e6b..be5e0191eaea 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -26,6 +26,7 @@ selftest(gt_mocs, intel_mocs_live_selftests)
selftest(gt_pm, intel_gt_pm_live_selftests)
selftest(gt_heartbeat, intel_heartbeat_live_selftests)
selftest(requests, i915_request_live_selftests)
+selftest(migrate, intel_migrate_live_selftests)
selftest(active, i915_active_live_selftests)
selftest(objects, i915_gem_object_live_selftests)
selftest(mman, i915_gem_mman_live_selftests)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 8/9] drm/i915/gt: Pipelined clear
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Update the PTE and emit a clear within a single unpreemptible packet
such that we can schedule and pipeline clears.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 141 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 20 +++
drivers/gpu/drm/i915/gt/selftest_migrate.c | 163 +++++++++++++++++++++
3 files changed, 324 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 70776316863d..fda05ce3eb9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -490,6 +490,112 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
+static int emit_clear(struct i915_request *rq, int size, u32 value)
+{
+ const int gen = INTEL_GEN(rq->engine->i915);
+ u32 *cs;
+
+ GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
+
+ cs = intel_ring_begin(rq, gen >= 8 ? 8 : 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ if (gen >= 8) {
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = 0; /* offset */
+ *cs++ = 0;
+ *cs++ = value;
+ *cs++ = MI_NOOP;
+ } else {
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = 0;
+ *cs++ = value;
+ }
+
+ intel_ring_advance(rq, cs);
+ return 0;
+}
+
+int
+intel_context_migrate_clear(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out)
+{
+ struct sgt_dma it = sg_sgt(sg);
+ struct i915_request *rq;
+ int err;
+
+ *out = NULL;
+
+ GEM_BUG_ON(ce->ring->size < SZ_64K);
+
+ do {
+ int len;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ if (await) {
+ err = i915_request_await_dma_fence(rq, await);
+ if (err)
+ goto out_rq;
+
+ if (rq->engine->emit_init_breadcrumb) {
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ await = NULL;
+ }
+
+ /* The PTE updates + clear must not be interrupted. */
+ err = emit_no_arbitration(rq);
+ if (err)
+ goto out_rq;
+
+ len = emit_pte(rq, &it, cache_level, is_lmem, 0, CHUNK_SZ);
+ if (len <= 0) {
+ err = len;
+ goto out_rq;
+ }
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ err = emit_clear(rq, len, value);
+
+ /* Arbitration is re-enabled between requests. */
+out_rq:
+ if (*out)
+ i915_request_put(*out);
+ *out = i915_request_get(rq);
+ i915_request_add(rq);
+ if (err || !it.sg || !sg_dma_len(it.sg))
+ break;
+
+ cond_resched();
+ } while (1);
+
+out_ce:
+ return err;
+}
+
int intel_migrate_copy(struct intel_migrate *m,
struct i915_gem_ww_ctx *ww,
struct dma_fence *await,
@@ -528,6 +634,41 @@ int intel_migrate_copy(struct intel_migrate *m,
return err;
}
+int
+intel_migrate_clear(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out)
+{
+ struct intel_context *ce;
+ int err;
+
+ *out = NULL;
+ if (!m->context)
+ return -ENODEV;
+
+ ce = intel_migrate_create_context(m);
+ if (IS_ERR(ce))
+ ce = intel_context_get(m->context);
+ GEM_BUG_ON(IS_ERR(ce));
+
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ err = intel_context_migrate_clear(ce, await, sg, cache_level,
+ is_lmem, value, out);
+
+ intel_context_unpin(ce);
+out:
+ intel_context_put(ce);
+ return err;
+}
+
void intel_migrate_fini(struct intel_migrate *m)
{
struct intel_context *ce;
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.h b/drivers/gpu/drm/i915/gt/intel_migrate.h
index 32c61190ed73..4e18e755a00b 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.h
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.h
@@ -6,6 +6,8 @@
#ifndef __INTEL_MIGRATE__
#define __INTEL_MIGRATE__
+#include <linux/types.h>
+
#include "intel_migrate_types.h"
struct dma_fence;
@@ -40,6 +42,24 @@ int intel_context_migrate_copy(struct intel_context *ce,
bool dst_is_lmem,
struct i915_request **out);
+int
+intel_migrate_clear(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out);
+int
+intel_context_migrate_clear(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out);
+
void intel_migrate_fini(struct intel_migrate *m);
#endif /* __INTEL_MIGRATE__ */
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 9784d149ebf1..159c8656e1b0 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -129,6 +129,82 @@ static int copy(struct intel_migrate *migrate,
return err;
}
+static int clear(struct intel_migrate *migrate,
+ int (*fn)(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out),
+ u32 sz, struct rnd_state *prng)
+{
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
+ u32 *vaddr;
+ int err = 0;
+ int i;
+
+ obj = create_lmem_or_internal(i915, sz);
+ if (IS_ERR(obj))
+ return 0;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_gem_object_lock(obj, &ww);
+ if (err)
+ continue;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ continue;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = ~i;
+ i915_gem_object_flush_map(obj);
+
+ err = fn(migrate, &ww, obj, sz, &rq);
+ if (!err)
+ continue;
+
+ if (err != -EDEADLK && err != -EINTR && err != -ERESTARTSYS)
+ pr_err("%ps failed, size: %u\n", fn, sz);
+ if (rq) {
+ i915_request_wait(rq, 0, HZ);
+ i915_request_put(rq);
+ }
+ i915_gem_object_unpin_map(obj);
+ }
+ if (err)
+ goto err_out;
+
+ if (rq) {
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ pr_err("%ps timed out, size: %u\n", fn, sz);
+ err = -ETIME;
+ }
+ i915_request_put(rq);
+ }
+
+ for (i = 0; !err && i < sz / PAGE_SIZE; i++) {
+ int x = i * 1024 + i915_prandom_u32_max_state(1024, prng);
+
+ if (vaddr[x] != sz) {
+ pr_err("%ps failed, size: %u, offset: %zu\n",
+ fn, sz, x * sizeof(u32));
+ igt_hexdump(vaddr + i * 1024, 4096);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(obj);
+err_out:
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
static int __migrate_copy(struct intel_migrate *migrate,
struct i915_gem_ww_ctx *ww,
struct drm_i915_gem_object *src,
@@ -169,6 +245,44 @@ global_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
return copy(migrate, __global_copy, sz, prng);
}
+static int __migrate_clear(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out)
+{
+ return intel_migrate_clear(migrate, ww, NULL,
+ obj->mm.pages->sgl,
+ obj->cache_level,
+ i915_gem_object_is_lmem(obj),
+ value, out);
+}
+
+static int __global_clear(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out)
+{
+ return intel_context_migrate_clear(migrate->context, NULL,
+ obj->mm.pages->sgl,
+ obj->cache_level,
+ i915_gem_object_is_lmem(obj),
+ value, out);
+}
+
+static int
+migrate_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return clear(migrate, __migrate_clear, sz, prng);
+}
+
+static int
+global_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return clear(migrate, __global_clear, sz, prng);
+}
+
static int live_migrate_copy(void *arg)
{
struct intel_migrate *migrate = arg;
@@ -190,6 +304,28 @@ static int live_migrate_copy(void *arg)
return 0;
}
+static int live_migrate_clear(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ int err;
+
+ err = migrate_clear(migrate, sizes[i], &prng);
+ if (err == 0)
+ err = global_clear(migrate, sizes[i], &prng);
+
+ i915_gem_drain_freed_objects(i915);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
struct threaded_migrate {
struct intel_migrate *migrate;
struct task_struct *tsk;
@@ -271,12 +407,39 @@ static int thread_global_copy(void *arg)
return threaded_migrate(arg, __thread_global_copy, 0);
}
+static int __thread_migrate_clear(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return migrate_clear(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int __thread_global_clear(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return global_clear(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_migrate_clear(void *arg)
+{
+ return threaded_migrate(arg, __thread_migrate_clear, 0);
+}
+
+static int thread_global_clear(void *arg)
+{
+ return threaded_migrate(arg, __thread_global_clear, 0);
+}
+
int intel_migrate_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_migrate_copy),
+ SUBTEST(live_migrate_clear),
SUBTEST(thread_migrate_copy),
+ SUBTEST(thread_migrate_clear),
SUBTEST(thread_global_copy),
+ SUBTEST(thread_global_clear),
};
struct intel_migrate m;
int err;
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 8/9] drm/i915/gt: Pipelined clear
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Update the PTE and emit a clear within a single unpreemptible packet
such that we can schedule and pipeline clears.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_migrate.c | 141 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_migrate.h | 20 +++
drivers/gpu/drm/i915/gt/selftest_migrate.c | 163 +++++++++++++++++++++
3 files changed, 324 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 70776316863d..fda05ce3eb9c 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -490,6 +490,112 @@ intel_context_migrate_copy(struct intel_context *ce,
return err;
}
+static int emit_clear(struct i915_request *rq, int size, u32 value)
+{
+ const int gen = INTEL_GEN(rq->engine->i915);
+ u32 *cs;
+
+ GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
+
+ cs = intel_ring_begin(rq, gen >= 8 ? 8 : 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ if (gen >= 8) {
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = 0; /* offset */
+ *cs++ = 0;
+ *cs++ = value;
+ *cs++ = MI_NOOP;
+ } else {
+ *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
+ *cs++ = 0;
+ *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+ *cs++ = 0;
+ *cs++ = value;
+ }
+
+ intel_ring_advance(rq, cs);
+ return 0;
+}
+
+int
+intel_context_migrate_clear(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out)
+{
+ struct sgt_dma it = sg_sgt(sg);
+ struct i915_request *rq;
+ int err;
+
+ *out = NULL;
+
+ GEM_BUG_ON(ce->ring->size < SZ_64K);
+
+ do {
+ int len;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto out_ce;
+ }
+
+ if (await) {
+ err = i915_request_await_dma_fence(rq, await);
+ if (err)
+ goto out_rq;
+
+ if (rq->engine->emit_init_breadcrumb) {
+ err = rq->engine->emit_init_breadcrumb(rq);
+ if (err)
+ goto out_rq;
+ }
+
+ await = NULL;
+ }
+
+ /* The PTE updates + clear must not be interrupted. */
+ err = emit_no_arbitration(rq);
+ if (err)
+ goto out_rq;
+
+ len = emit_pte(rq, &it, cache_level, is_lmem, 0, CHUNK_SZ);
+ if (len <= 0) {
+ err = len;
+ goto out_rq;
+ }
+
+ err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
+ if (err)
+ goto out_rq;
+
+ err = emit_clear(rq, len, value);
+
+ /* Arbitration is re-enabled between requests. */
+out_rq:
+ if (*out)
+ i915_request_put(*out);
+ *out = i915_request_get(rq);
+ i915_request_add(rq);
+ if (err || !it.sg || !sg_dma_len(it.sg))
+ break;
+
+ cond_resched();
+ } while (1);
+
+out_ce:
+ return err;
+}
+
int intel_migrate_copy(struct intel_migrate *m,
struct i915_gem_ww_ctx *ww,
struct dma_fence *await,
@@ -528,6 +634,41 @@ int intel_migrate_copy(struct intel_migrate *m,
return err;
}
+int
+intel_migrate_clear(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out)
+{
+ struct intel_context *ce;
+ int err;
+
+ *out = NULL;
+ if (!m->context)
+ return -ENODEV;
+
+ ce = intel_migrate_create_context(m);
+ if (IS_ERR(ce))
+ ce = intel_context_get(m->context);
+ GEM_BUG_ON(IS_ERR(ce));
+
+ err = intel_context_pin_ww(ce, ww);
+ if (err)
+ goto out;
+
+ err = intel_context_migrate_clear(ce, await, sg, cache_level,
+ is_lmem, value, out);
+
+ intel_context_unpin(ce);
+out:
+ intel_context_put(ce);
+ return err;
+}
+
void intel_migrate_fini(struct intel_migrate *m)
{
struct intel_context *ce;
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.h b/drivers/gpu/drm/i915/gt/intel_migrate.h
index 32c61190ed73..4e18e755a00b 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.h
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.h
@@ -6,6 +6,8 @@
#ifndef __INTEL_MIGRATE__
#define __INTEL_MIGRATE__
+#include <linux/types.h>
+
#include "intel_migrate_types.h"
struct dma_fence;
@@ -40,6 +42,24 @@ int intel_context_migrate_copy(struct intel_context *ce,
bool dst_is_lmem,
struct i915_request **out);
+int
+intel_migrate_clear(struct intel_migrate *m,
+ struct i915_gem_ww_ctx *ww,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out);
+int
+intel_context_migrate_clear(struct intel_context *ce,
+ struct dma_fence *await,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ u32 value,
+ struct i915_request **out);
+
void intel_migrate_fini(struct intel_migrate *m);
#endif /* __INTEL_MIGRATE__ */
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 9784d149ebf1..159c8656e1b0 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -129,6 +129,82 @@ static int copy(struct intel_migrate *migrate,
return err;
}
+static int clear(struct intel_migrate *migrate,
+ int (*fn)(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out),
+ u32 sz, struct rnd_state *prng)
+{
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ struct drm_i915_gem_object *obj;
+ struct i915_request *rq;
+ struct i915_gem_ww_ctx ww;
+ u32 *vaddr;
+ int err = 0;
+ int i;
+
+ obj = create_lmem_or_internal(i915, sz);
+ if (IS_ERR(obj))
+ return 0;
+
+ for_i915_gem_ww(&ww, err, true) {
+ err = i915_gem_object_lock(obj, &ww);
+ if (err)
+ continue;
+
+ vaddr = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(vaddr)) {
+ err = PTR_ERR(vaddr);
+ continue;
+ }
+
+ for (i = 0; i < sz / sizeof(u32); i++)
+ vaddr[i] = ~i;
+ i915_gem_object_flush_map(obj);
+
+ err = fn(migrate, &ww, obj, sz, &rq);
+ if (!err)
+ continue;
+
+ if (err != -EDEADLK && err != -EINTR && err != -ERESTARTSYS)
+ pr_err("%ps failed, size: %u\n", fn, sz);
+ if (rq) {
+ i915_request_wait(rq, 0, HZ);
+ i915_request_put(rq);
+ }
+ i915_gem_object_unpin_map(obj);
+ }
+ if (err)
+ goto err_out;
+
+ if (rq) {
+ if (i915_request_wait(rq, 0, HZ) < 0) {
+ pr_err("%ps timed out, size: %u\n", fn, sz);
+ err = -ETIME;
+ }
+ i915_request_put(rq);
+ }
+
+ for (i = 0; !err && i < sz / PAGE_SIZE; i++) {
+ int x = i * 1024 + i915_prandom_u32_max_state(1024, prng);
+
+ if (vaddr[x] != sz) {
+ pr_err("%ps failed, size: %u, offset: %zu\n",
+ fn, sz, x * sizeof(u32));
+ igt_hexdump(vaddr + i * 1024, 4096);
+ err = -EINVAL;
+ }
+ }
+
+ i915_gem_object_unpin_map(obj);
+err_out:
+ i915_gem_object_put(obj);
+
+ return err;
+}
+
static int __migrate_copy(struct intel_migrate *migrate,
struct i915_gem_ww_ctx *ww,
struct drm_i915_gem_object *src,
@@ -169,6 +245,44 @@ global_copy(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
return copy(migrate, __global_copy, sz, prng);
}
+static int __migrate_clear(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out)
+{
+ return intel_migrate_clear(migrate, ww, NULL,
+ obj->mm.pages->sgl,
+ obj->cache_level,
+ i915_gem_object_is_lmem(obj),
+ value, out);
+}
+
+static int __global_clear(struct intel_migrate *migrate,
+ struct i915_gem_ww_ctx *ww,
+ struct drm_i915_gem_object *obj,
+ u32 value,
+ struct i915_request **out)
+{
+ return intel_context_migrate_clear(migrate->context, NULL,
+ obj->mm.pages->sgl,
+ obj->cache_level,
+ i915_gem_object_is_lmem(obj),
+ value, out);
+}
+
+static int
+migrate_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return clear(migrate, __migrate_clear, sz, prng);
+}
+
+static int
+global_clear(struct intel_migrate *migrate, u32 sz, struct rnd_state *prng)
+{
+ return clear(migrate, __global_clear, sz, prng);
+}
+
static int live_migrate_copy(void *arg)
{
struct intel_migrate *migrate = arg;
@@ -190,6 +304,28 @@ static int live_migrate_copy(void *arg)
return 0;
}
+static int live_migrate_clear(void *arg)
+{
+ struct intel_migrate *migrate = arg;
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ int err;
+
+ err = migrate_clear(migrate, sizes[i], &prng);
+ if (err == 0)
+ err = global_clear(migrate, sizes[i], &prng);
+
+ i915_gem_drain_freed_objects(i915);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
struct threaded_migrate {
struct intel_migrate *migrate;
struct task_struct *tsk;
@@ -271,12 +407,39 @@ static int thread_global_copy(void *arg)
return threaded_migrate(arg, __thread_global_copy, 0);
}
+static int __thread_migrate_clear(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return migrate_clear(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int __thread_global_clear(void *arg)
+{
+ struct threaded_migrate *tm = arg;
+
+ return global_clear(tm->migrate, 2 * CHUNK_SZ, &tm->prng);
+}
+
+static int thread_migrate_clear(void *arg)
+{
+ return threaded_migrate(arg, __thread_migrate_clear, 0);
+}
+
+static int thread_global_clear(void *arg)
+{
+ return threaded_migrate(arg, __thread_global_clear, 0);
+}
+
int intel_migrate_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_migrate_copy),
+ SUBTEST(live_migrate_clear),
SUBTEST(thread_migrate_copy),
+ SUBTEST(thread_migrate_clear),
SUBTEST(thread_global_copy),
+ SUBTEST(thread_global_clear),
};
struct intel_migrate m;
int err;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [PATCH v2 9/9] drm/i915/gt: Setup a default migration context on the GT
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 6:34 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Set up a default migration context on the GT and use it from the
selftests.
Add a perf selftest and make sure we exercise LMEM if available.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c | 227 +++++++++++++++++-
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
5 files changed, 232 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..67ef057ae918 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -13,6 +13,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+#include "intel_migrate.h"
#include "intel_mocs.h"
#include "intel_rc6.h"
#include "intel_renderstate.h"
@@ -626,6 +627,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_migrate_init(>->migrate, gt);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -649,6 +652,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
+ intel_migrate_fini(>->migrate);
intel_uc_driver_remove(>->uc);
intel_engines_release(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index fecfacf551d5..7450935f2ca8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -24,6 +24,7 @@
#include "intel_reset_types.h"
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
+#include "intel_migrate_types.h"
#include "intel_wakeref.h"
struct drm_i915_private;
@@ -145,6 +146,8 @@ struct intel_gt {
struct i915_vma *scratch;
+ struct intel_migrate migrate;
+
struct intel_gt_info {
intel_engine_mask_t engine_mask;
u8 num_engines;
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index fda05ce3eb9c..935b5f14ff21 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -418,10 +418,9 @@ intel_context_migrate_copy(struct intel_context *ce,
struct i915_request *rq;
int err;
+ GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
*out = NULL;
- /* GEM_BUG_ON(ce->vm != migrate_vm); */
-
GEM_BUG_ON(ce->ring->size < SZ_64K);
do {
@@ -536,6 +535,7 @@ intel_context_migrate_clear(struct intel_context *ce,
struct i915_request *rq;
int err;
+ GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
*out = NULL;
GEM_BUG_ON(ce->ring->size < SZ_64K);
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 159c8656e1b0..396c81364399 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/sort.h>
+
#include "selftests/i915_random.h"
static const unsigned int sizes[] = {
@@ -441,14 +443,229 @@ int intel_migrate_live_selftests(struct drm_i915_private *i915)
SUBTEST(thread_global_copy),
SUBTEST(thread_global_clear),
};
- struct intel_migrate m;
+ struct intel_gt *gt = &i915->gt;
+
+ if (!gt->migrate.context)
+ return 0;
+
+ return i915_subtests(tests, >->migrate);
+}
+
+static struct drm_i915_gem_object *
+create_init_lmem_internal(struct intel_gt *gt, size_t sz, bool try_lmem)
+{
+ struct drm_i915_gem_object *obj = NULL;
int err;
- if (intel_migrate_init(&m, &i915->gt))
+ if (try_lmem && HAS_LMEM(gt->i915))
+ obj = i915_gem_object_create_lmem(gt->i915, sz, 0);
+
+ if (IS_ERR_OR_NULL(obj)) {
+ obj = i915_gem_object_create_internal(gt->i915, sz);
+ if (IS_ERR(obj))
+ return obj;
+ }
+
+ i915_gem_object_trylock(obj);
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return obj;
+}
+
+static int wrap_ktime_compare(const void *A, const void *B)
+{
+ const ktime_t *a = A, *b = B;
+
+ return ktime_compare(*a, *b);
+}
+
+static int __perf_clear_blt(struct intel_context *ce,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ size_t sz)
+{
+ ktime_t t[5];
+ int pass;
+ int err = 0;
+
+ for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
+ struct i915_request *rq;
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
+ is_lmem, 0, &rq);
+ if (rq) {
+ if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ }
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[pass] = ktime_sub(t1, t0);
+ }
+ if (err)
+ return err;
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ pr_info("%s: %zd KiB fill: %lld MiB/s\n",
+ ce->engine->name, sz >> 10,
+ div64_u64(mul_u32_u32(4 * sz,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20);
+ return 0;
+}
+
+static int perf_clear_blt(void *arg)
+{
+ struct intel_gt *gt = arg;
+ static const unsigned long sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ SZ_64M
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ struct drm_i915_gem_object *dst;
+ int err;
+
+ dst = create_init_lmem_internal(gt, sizes[i], true);
+ if (IS_ERR(dst))
+ return PTR_ERR(dst);
+
+ err = __perf_clear_blt(gt->migrate.context,
+ dst->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(dst),
+ sizes[i]);
+
+ i915_gem_object_unlock(dst);
+ i915_gem_object_put(dst);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int __perf_copy_blt(struct intel_context *ce,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ size_t sz)
+{
+ ktime_t t[5];
+ int pass;
+ int err = 0;
+
+ for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
+ struct i915_request *rq;
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = intel_context_migrate_copy(ce, NULL,
+ src, src_cache_level,
+ src_is_lmem,
+ dst, dst_cache_level,
+ dst_is_lmem,
+ &rq);
+ if (rq) {
+ if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ }
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[pass] = ktime_sub(t1, t0);
+ }
+ if (err)
+ return err;
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ pr_info("%s: %zd KiB copy: %lld MiB/s\n",
+ ce->engine->name, sz >> 10,
+ div64_u64(mul_u32_u32(4 * sz,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20);
+ return 0;
+}
+
+static int perf_copy_blt(void *arg)
+{
+ struct intel_gt *gt = arg;
+ static const unsigned long sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ SZ_64M
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ struct drm_i915_gem_object *src, *dst;
+ int err;
+
+ src = create_init_lmem_internal(gt, sizes[i], true);
+ if (IS_ERR(src))
+ return PTR_ERR(src);
+
+ dst = create_init_lmem_internal(gt, sizes[i], false);
+ if (IS_ERR(dst)) {
+ err = PTR_ERR(dst);
+ goto err_src;
+ }
+
+ err = __perf_copy_blt(gt->migrate.context,
+ src->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(dst),
+ sizes[i]);
+
+ i915_gem_object_unlock(dst);
+ i915_gem_object_put(dst);
+err_src:
+ i915_gem_object_unlock(src);
+ i915_gem_object_put(src);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int intel_migrate_perf_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_clear_blt),
+ SUBTEST(perf_copy_blt),
+ };
+ struct intel_gt *gt = &i915->gt;
+
+ if (intel_gt_is_wedged(gt))
return 0;
- err = i915_subtests(tests, &m);
- intel_migrate_fini(&m);
+ if (!gt->migrate.context)
+ return 0;
- return err;
+ return intel_gt_live_subtests(tests, gt);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..5077dc3c3b8c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(migrate, intel_migrate_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
--
2.31.1
^ permalink raw reply related [flat|nested] 50+ messages in thread
* [Intel-gfx] [PATCH v2 9/9] drm/i915/gt: Setup a default migration context on the GT
@ 2021-06-09 6:34 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 6:34 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Thomas Hellström, matthew.auld, Chris Wilson
From: Chris Wilson <chris@chris-wilson.co.uk>
Set up a default migration context on the GT and use it from the
selftests.
Add a perf selftest and make sure we exercise LMEM if available.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +-
drivers/gpu/drm/i915/gt/selftest_migrate.c | 227 +++++++++++++++++-
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
5 files changed, 232 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 2161bf01ef8b..67ef057ae918 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -13,6 +13,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+#include "intel_migrate.h"
#include "intel_mocs.h"
#include "intel_rc6.h"
#include "intel_renderstate.h"
@@ -626,6 +627,8 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_gt;
+ intel_migrate_init(>->migrate, gt);
+
goto out_fw;
err_gt:
__intel_gt_disable(gt);
@@ -649,6 +652,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
{
__intel_gt_disable(gt);
+ intel_migrate_fini(>->migrate);
intel_uc_driver_remove(>->uc);
intel_engines_release(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index fecfacf551d5..7450935f2ca8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -24,6 +24,7 @@
#include "intel_reset_types.h"
#include "intel_rc6_types.h"
#include "intel_rps_types.h"
+#include "intel_migrate_types.h"
#include "intel_wakeref.h"
struct drm_i915_private;
@@ -145,6 +146,8 @@ struct intel_gt {
struct i915_vma *scratch;
+ struct intel_migrate migrate;
+
struct intel_gt_info {
intel_engine_mask_t engine_mask;
u8 num_engines;
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index fda05ce3eb9c..935b5f14ff21 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -418,10 +418,9 @@ intel_context_migrate_copy(struct intel_context *ce,
struct i915_request *rq;
int err;
+ GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
*out = NULL;
- /* GEM_BUG_ON(ce->vm != migrate_vm); */
-
GEM_BUG_ON(ce->ring->size < SZ_64K);
do {
@@ -536,6 +535,7 @@ intel_context_migrate_clear(struct intel_context *ce,
struct i915_request *rq;
int err;
+ GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
*out = NULL;
GEM_BUG_ON(ce->ring->size < SZ_64K);
diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
index 159c8656e1b0..396c81364399 100644
--- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
+++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include <linux/sort.h>
+
#include "selftests/i915_random.h"
static const unsigned int sizes[] = {
@@ -441,14 +443,229 @@ int intel_migrate_live_selftests(struct drm_i915_private *i915)
SUBTEST(thread_global_copy),
SUBTEST(thread_global_clear),
};
- struct intel_migrate m;
+ struct intel_gt *gt = &i915->gt;
+
+ if (!gt->migrate.context)
+ return 0;
+
+ return i915_subtests(tests, >->migrate);
+}
+
+static struct drm_i915_gem_object *
+create_init_lmem_internal(struct intel_gt *gt, size_t sz, bool try_lmem)
+{
+ struct drm_i915_gem_object *obj = NULL;
int err;
- if (intel_migrate_init(&m, &i915->gt))
+ if (try_lmem && HAS_LMEM(gt->i915))
+ obj = i915_gem_object_create_lmem(gt->i915, sz, 0);
+
+ if (IS_ERR_OR_NULL(obj)) {
+ obj = i915_gem_object_create_internal(gt->i915, sz);
+ if (IS_ERR(obj))
+ return obj;
+ }
+
+ i915_gem_object_trylock(obj);
+ err = i915_gem_object_pin_pages(obj);
+ if (err) {
+ i915_gem_object_unlock(obj);
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return obj;
+}
+
+static int wrap_ktime_compare(const void *A, const void *B)
+{
+ const ktime_t *a = A, *b = B;
+
+ return ktime_compare(*a, *b);
+}
+
+static int __perf_clear_blt(struct intel_context *ce,
+ struct scatterlist *sg,
+ enum i915_cache_level cache_level,
+ bool is_lmem,
+ size_t sz)
+{
+ ktime_t t[5];
+ int pass;
+ int err = 0;
+
+ for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
+ struct i915_request *rq;
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
+ is_lmem, 0, &rq);
+ if (rq) {
+ if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ }
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[pass] = ktime_sub(t1, t0);
+ }
+ if (err)
+ return err;
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ pr_info("%s: %zd KiB fill: %lld MiB/s\n",
+ ce->engine->name, sz >> 10,
+ div64_u64(mul_u32_u32(4 * sz,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20);
+ return 0;
+}
+
+static int perf_clear_blt(void *arg)
+{
+ struct intel_gt *gt = arg;
+ static const unsigned long sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ SZ_64M
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ struct drm_i915_gem_object *dst;
+ int err;
+
+ dst = create_init_lmem_internal(gt, sizes[i], true);
+ if (IS_ERR(dst))
+ return PTR_ERR(dst);
+
+ err = __perf_clear_blt(gt->migrate.context,
+ dst->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(dst),
+ sizes[i]);
+
+ i915_gem_object_unlock(dst);
+ i915_gem_object_put(dst);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+static int __perf_copy_blt(struct intel_context *ce,
+ struct scatterlist *src,
+ enum i915_cache_level src_cache_level,
+ bool src_is_lmem,
+ struct scatterlist *dst,
+ enum i915_cache_level dst_cache_level,
+ bool dst_is_lmem,
+ size_t sz)
+{
+ ktime_t t[5];
+ int pass;
+ int err = 0;
+
+ for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
+ struct i915_request *rq;
+ ktime_t t0, t1;
+
+ t0 = ktime_get();
+
+ err = intel_context_migrate_copy(ce, NULL,
+ src, src_cache_level,
+ src_is_lmem,
+ dst, dst_cache_level,
+ dst_is_lmem,
+ &rq);
+ if (rq) {
+ if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -EIO;
+ i915_request_put(rq);
+ }
+ if (err)
+ break;
+
+ t1 = ktime_get();
+ t[pass] = ktime_sub(t1, t0);
+ }
+ if (err)
+ return err;
+
+ sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
+ pr_info("%s: %zd KiB copy: %lld MiB/s\n",
+ ce->engine->name, sz >> 10,
+ div64_u64(mul_u32_u32(4 * sz,
+ 1000 * 1000 * 1000),
+ t[1] + 2 * t[2] + t[3]) >> 20);
+ return 0;
+}
+
+static int perf_copy_blt(void *arg)
+{
+ struct intel_gt *gt = arg;
+ static const unsigned long sizes[] = {
+ SZ_4K,
+ SZ_64K,
+ SZ_2M,
+ SZ_64M
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(sizes); i++) {
+ struct drm_i915_gem_object *src, *dst;
+ int err;
+
+ src = create_init_lmem_internal(gt, sizes[i], true);
+ if (IS_ERR(src))
+ return PTR_ERR(src);
+
+ dst = create_init_lmem_internal(gt, sizes[i], false);
+ if (IS_ERR(dst)) {
+ err = PTR_ERR(dst);
+ goto err_src;
+ }
+
+ err = __perf_copy_blt(gt->migrate.context,
+ src->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(src),
+ dst->mm.pages->sgl,
+ I915_CACHE_NONE,
+ i915_gem_object_is_lmem(dst),
+ sizes[i]);
+
+ i915_gem_object_unlock(dst);
+ i915_gem_object_put(dst);
+err_src:
+ i915_gem_object_unlock(src);
+ i915_gem_object_put(src);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int intel_migrate_perf_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_clear_blt),
+ SUBTEST(perf_copy_blt),
+ };
+ struct intel_gt *gt = &i915->gt;
+
+ if (intel_gt_is_wedged(gt))
return 0;
- err = i915_subtests(tests, &m);
- intel_migrate_fini(&m);
+ if (!gt->migrate.context)
+ return 0;
- return err;
+ return intel_gt_live_subtests(tests, gt);
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index c2389f8a257d..5077dc3c3b8c 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -17,5 +17,6 @@
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
selftest(request, i915_request_perf_selftests)
+selftest(migrate, intel_migrate_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 50+ messages in thread
* Re: [PATCH v2 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 7:44 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 7:44 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> In the next patch, we will want to write a PTE for an explicit
> dma address, outside of the usual vma.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt
@ 2021-06-09 7:44 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 7:44 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> In the next patch, we will want to write a PTE for an explicit
> dma address, outside of the usual vma.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 7:48 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 7:48 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> In the next patch, we will want to look at the dma addresses of
> individual page tables, so add a routine to iterate over them.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
@ 2021-06-09 7:48 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 7:48 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> In the next patch, we will want to look at the dma addresses of
> individual page tables, so add a routine to iterate over them.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prereqs for TTM accelerated migration (rev2)
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
` (9 preceding siblings ...)
(?)
@ 2021-06-09 7:54 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2021-06-09 7:54 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: Prereqs for TTM accelerated migration (rev2)
URL : https://patchwork.freedesktop.org/series/91155/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
be1926db749f drm/i915: Reference objects on the ww object list
ae3f71f8fc2d drm/i915: Break out dma_resv ww locking utilities to separate files
-:141: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#141:
new file mode 100644
-:166: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#166: FILE: drivers/gpu/drm/i915/i915_gem_ww.c:21:
+ while ((obj = list_first_entry_or_null(&ww->obj_list, struct drm_i915_gem_object, obj_link))) {
total: 0 errors, 2 warnings, 0 checks, 183 lines checked
8bf111e86cf9 drm/i915: Introduce a ww transaction helper
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_ww' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_gem_ww.h:46:
+#define for_i915_gem_ww(_ww, _err, _intr) \
+ for (__i915_gem_ww_init(_ww, _intr); (_ww)->loop; \
+ _err = __i915_gem_ww_fini(_ww, _err))
-:56: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_err' - possible side-effects?
#56: FILE: drivers/gpu/drm/i915/i915_gem_ww.h:46:
+#define for_i915_gem_ww(_ww, _err, _intr) \
+ for (__i915_gem_ww_init(_ww, _intr); (_ww)->loop; \
+ _err = __i915_gem_ww_fini(_ww, _err))
total: 0 errors, 0 warnings, 2 checks, 41 lines checked
50f6709e7fff drm/i915/gt: Add an insert_entry for gen8_ppgtt
e63c320c3025 drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
86e3a5a7d285 drm/i915/gt: Export the pinned context constructor and destructor
5fcf6685a775 drm/i915/gt: Pipelined page migration
-:66: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#66:
new file mode 100644
-:880: WARNING:LINE_SPACING: Missing a blank line after declarations
#880: FILE: drivers/gpu/drm/i915/gt/selftest_migrate.c:176:
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
-:909: WARNING:LINE_SPACING: Missing a blank line after declarations
#909: FILE: drivers/gpu/drm/i915/gt/selftest_migrate.c:205:
+ struct threaded_migrate *thread;
+ I915_RND_STATE(prng);
-:934: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#934: FILE: drivers/gpu/drm/i915/gt/selftest_migrate.c:230:
+ msleep(10); /* start all threads before we kthread_stop() */
total: 0 errors, 4 warnings, 0 checks, 933 lines checked
b4f5bf5e3091 drm/i915/gt: Pipelined clear
-:353: WARNING:LINE_SPACING: Missing a blank line after declarations
#353: FILE: drivers/gpu/drm/i915/gt/selftest_migrate.c:311:
+ struct drm_i915_private *i915 = migrate->context->engine->i915;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 378 lines checked
a6745617acf0 drm/i915/gt: Setup a default migration context on the GT
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 6/9] drm/i915/gt: Export the pinned context constructor and destructor
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 8:00 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 8:00 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Allow internal clients to create and destroy a pinned context.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/gt: Export the pinned context constructor and destructor
@ 2021-06-09 8:00 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 8:00 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Allow internal clients to create and destroy a pinned context.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Prereqs for TTM accelerated migration (rev2)
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
` (10 preceding siblings ...)
(?)
@ 2021-06-09 8:23 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2021-06-09 8:23 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 8170 bytes --]
== Series Details ==
Series: Prereqs for TTM accelerated migration (rev2)
URL : https://patchwork.freedesktop.org/series/91155/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10195 -> Patchwork_20318
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/index.html
New tests
---------
New tests have been introduced between CI_DRM_10195 and Patchwork_20318:
### New IGT tests (1) ###
* igt@i915_selftest@live@migrate:
- Statuses : 2 dmesg-warn(s) 35 pass(s)
- Exec time: [0.54, 7.97] s
Known issues
------------
Here are the changes found in Patchwork_20318 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: NOTRUN -> [INCOMPLETE][1] ([i915#2782] / [i915#2940] / [i915#3462])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* {igt@i915_selftest@live@migrate} (NEW):
- {fi-ehl-2}: NOTRUN -> [DMESG-WARN][2] ([i915#1222])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-ehl-2/igt@i915_selftest@live@migrate.html
- {fi-jsl-1}: NOTRUN -> [DMESG-WARN][3] ([i915#1222])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-jsl-1/igt@i915_selftest@live@migrate.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-bsw-kefka: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-bsw-kefka/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_psr@cursor_plane_move:
- fi-bsw-kefka: NOTRUN -> [SKIP][5] ([fdo#109271]) +13 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-bsw-kefka/igt@kms_psr@cursor_plane_move.html
* igt@runner@aborted:
- fi-bsw-kefka: NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#1436])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-bsw-kefka/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0:
- fi-bsw-kefka: [INCOMPLETE][7] ([i915#2539]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-bsw-kefka/igt@gem_exec_suspend@basic-s0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-bsw-kefka/igt@gem_exec_suspend@basic-s0.html
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-icl-u2: [DMESG-FAIL][9] ([i915#3462]) -> [INCOMPLETE][10] ([i915#2782] / [i915#3462])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-icl-u2/igt@i915_selftest@live@execlists.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-icl-u2/igt@i915_selftest@live@execlists.html
- fi-tgl-u2: [INCOMPLETE][11] ([i915#3462]) -> [DMESG-FAIL][12] ([i915#3462])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-tgl-u2/igt@i915_selftest@live@execlists.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-tgl-u2/igt@i915_selftest@live@execlists.html
* igt@runner@aborted:
- fi-skl-6600u: [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14] ([i915#1436] / [i915#2426] / [i915#3363])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-skl-6600u/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-skl-6600u/igt@runner@aborted.html
- fi-icl-u2: [FAIL][15] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][16] ([i915#2782] / [i915#3363])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-icl-u2/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-icl-u2/igt@runner@aborted.html
- fi-kbl-7500u: [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#2426] / [i915#3363])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-kbl-7500u/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-kbl-7500u/igt@runner@aborted.html
- fi-cml-u2: [FAIL][19] ([i915#3363] / [i915#3462]) -> [FAIL][20] ([i915#2082] / [i915#2426] / [i915#3363] / [i915#3462])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-cml-u2/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-cml-u2/igt@runner@aborted.html
- fi-cfl-guc: [FAIL][21] ([i915#3363]) -> [FAIL][22] ([i915#2426] / [i915#3363])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-cfl-guc/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-cfl-guc/igt@runner@aborted.html
- fi-skl-6700k2: [FAIL][23] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][24] ([i915#1436] / [i915#3363])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/fi-skl-6700k2/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/fi-skl-6700k2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1222]: https://gitlab.freedesktop.org/drm/intel/issues/1222
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2539]: https://gitlab.freedesktop.org/drm/intel/issues/2539
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
Participating hosts (46 -> 41)
------------------------------
Missing (5): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10195 -> Patchwork_20318
CI-20190529: 20190529
CI_DRM_10195: 70e4d80795934312a3853a4f4f49445ce6db1271 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6103: 3aa79e55e73d4a49a5222e5dfde486b800a29fe7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20318: a6745617acf0c89f578fcce067c052117a8a42aa @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_20318/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
a6745617acf0 drm/i915/gt: Setup a default migration context on the GT
b4f5bf5e3091 drm/i915/gt: Pipelined clear
5fcf6685a775 drm/i915/gt: Pipelined page migration
86e3a5a7d285 drm/i915/gt: Export the pinned context constructor and destructor
e63c320c3025 drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
50f6709e7fff drm/i915/gt: Add an insert_entry for gen8_ppgtt
8bf111e86cf9 drm/i915: Introduce a ww transaction helper
ae3f71f8fc2d drm/i915: Break out dma_resv ww locking utilities to separate files
be1926db749f drm/i915: Reference objects on the ww object list
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/index.html
[-- Attachment #1.2: Type: text/html, Size: 11583 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for Prereqs for TTM accelerated migration (rev2)
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
` (11 preceding siblings ...)
(?)
@ 2021-06-09 8:23 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2021-06-09 8:23 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: Prereqs for TTM accelerated migration (rev2)
URL : https://patchwork.freedesktop.org/series/91155/
State : warning
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
MODPOST modules-only.symvers
ERROR: modpost: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
ERROR: modpost: "__divdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:150: recipe for target 'modules-only.symvers' failed
make[1]: *** [modules-only.symvers] Error 1
make[1]: *** Deleting file 'modules-only.symvers'
Makefile:1759: recipe for target 'modules' failed
make: *** [modules] Error 2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Prereqs for TTM accelerated migration (rev2)
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
` (12 preceding siblings ...)
(?)
@ 2021-06-09 9:56 ` Patchwork
-1 siblings, 0 replies; 50+ messages in thread
From: Patchwork @ 2021-06-09 9:56 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30267 bytes --]
== Series Details ==
Series: Prereqs for TTM accelerated migration (rev2)
URL : https://patchwork.freedesktop.org/series/91155/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10195_full -> Patchwork_20318_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
New tests
---------
New tests have been introduced between CI_DRM_10195_full and Patchwork_20318_full:
### New IGT tests (2) ###
* igt@i915_selftest@live@migrate:
- Statuses : 6 pass(s)
- Exec time: [1.17, 8.65] s
* igt@i915_selftest@perf@migrate:
- Statuses : 6 pass(s)
- Exec time: [0.69, 5.81] s
Known issues
------------
Here are the changes found in Patchwork_20318_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-clear:
- shard-glk: [PASS][1] -> [FAIL][2] ([i915#1888] / [i915#3160])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-glk3/igt@gem_create@create-clear.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-glk5/igt@gem_create@create-clear.html
* igt@gem_create@create-massive:
- shard-snb: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-snb7/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-snb7/igt@gem_ctx_persistence@idempotent.html
* igt@gem_ctx_ringsize@active@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#3316])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl3/igt@gem_ctx_ringsize@active@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][6] ([i915#2846])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-glk7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_mmap_gtt@big-copy:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#307])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl9/igt@gem_mmap_gtt@big-copy.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl6/igt@gem_mmap_gtt@big-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][15] ([i915#2658])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_vm_create@destroy-race:
- shard-tglb: [PASS][16] -> [TIMEOUT][17] ([i915#2795])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-tglb7/igt@gem_vm_create@destroy-race.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-tglb1/igt@gem_vm_create@destroy-race.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1436] / [i915#716])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl3/igt@gen9_exec_parse@allowed-single.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_hangman@engine-error@vecs0:
- shard-kbl: NOTRUN -> [SKIP][20] ([fdo#109271]) +102 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl4/igt@i915_hangman@engine-error@vecs0.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][21] ([i915#454])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl1/igt@i915_pm_dc@dc6-dpms.html
- shard-skl: NOTRUN -> [FAIL][22] ([i915#454])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live@execlists:
- shard-apl: NOTRUN -> [DMESG-FAIL][23] ([i915#3462])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@i915_selftest@live@execlists.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111304])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl3/igt@kms_ccs@pipe-c-crc-primary-rotation-180.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +17 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl2/igt@kms_chamelium@vga-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +15 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-gamma:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +6 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl3/igt@kms_color_chamelium@pipe-c-gamma.html
* igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +5 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl3/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html
* igt@kms_content_protection@atomic:
- shard-apl: NOTRUN -> [TIMEOUT][29] ([i915#1319]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-kbl: NOTRUN -> [TIMEOUT][30] ([i915#1319]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl4/igt@kms_content_protection@legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#2346] / [i915#533])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#180])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][37] -> [FAIL][38] ([i915#2122]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl2/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl7/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#2672])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#2642])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271]) +72 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> [SKIP][42] ([fdo#109271]) +322 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-snb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#49])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][45] -> [FAIL][46] ([i915#1188]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl6/igt@kms_hdr@bpc-switch-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533]) +2 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#108145] / [i915#265]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][51] ([fdo#108145] / [i915#265]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-kbl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#2733])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html
* igt@kms_psr2_su@frontbuffer:
- shard-skl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][57] -> [SKIP][58] ([fdo#109642] / [fdo#111068] / [i915#658])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb2/igt@kms_psr2_su@page_flip.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb1/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][59] -> [SKIP][60] ([fdo#109441])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2437])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
- shard-apl: NOTRUN -> [SKIP][62] ([fdo#109271]) +171 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl7/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html
* igt@perf@short-reads:
- shard-skl: [PASS][63] -> [FAIL][64] ([i915#51])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl5/igt@perf@short-reads.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl3/igt@perf@short-reads.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2994]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl2/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@recycle:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl4/igt@sysfs_clients@recycle.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][67] ([i915#2842]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-glk5/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: [FAIL][69] ([i915#2842]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-tglb1/igt@gem_exec_fair@basic-pace@bcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-tglb6/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
- shard-glk: [DMESG-WARN][71] ([i915#118] / [i915#95]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-glk2/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-glk1/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-skl: [FAIL][73] ([i915#533]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl9/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [FAIL][75] ([i915#2346]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +8 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-dp1:
- shard-kbl: [FAIL][81] ([i915#2122]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl6/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl7/igt@kms_flip@plain-flip-fb-recreate@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][83] ([i915#2122]) -> [PASS][84] +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-skl: [FAIL][85] ([i915#49]) -> [PASS][86] +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][87] ([fdo#108145] / [i915#265]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][89] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@perf@polling-parameterized:
- shard-iclb: [FAIL][93] ([i915#1542]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb3/igt@perf@polling-parameterized.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb6/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][95] ([i915#658]) -> [SKIP][96] ([i915#588])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][97] ([i915#2684]) -> [WARN][98] ([i915#1804] / [i915#2684]) +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb5/igt@i915_pm_rc6_residency@rc6-fence.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_selftest@live@execlists:
- shard-iclb: [DMESG-FAIL][99] ([i915#3462]) -> [INCOMPLETE][100] ([i915#2782] / [i915#3462])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb3/igt@i915_selftest@live@execlists.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb1/igt@i915_selftest@live@execlists.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][101] ([i915#2920]) -> [SKIP][102] ([i915#658]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: [SKIP][103] ([i915#658]) -> [SKIP][104] ([i915#2920]) +2 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-iclb4/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2505] / [i915#3002] / [i915#3363] / [i915#602])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl2/igt@runner@aborted.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl2/igt@runner@aborted.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl1/igt@runner@aborted.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl7/igt@runner@aborted.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl4/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl4/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl6/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-kbl7/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl6/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl7/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl7/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl1/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl2/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-kbl1/igt@runner@aborted.html
- shard-apl: ([FAIL][121], [FAIL][122]) ([i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][123], [FAIL][124], [FAIL][125]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-apl2/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-apl8/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl6/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl8/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-apl1/igt@runner@aborted.html
- shard-skl: ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129]) ([i915#1436] / [i915#1814] / [i915#2029] / [i915#2426] / [i915#3002] / [i915#3363]) -> ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([i915#1436] / [i915#3002] / [i915#3363])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl7/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10195/shard-skl3/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl8/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl5/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/shard-skl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111304]: https://bugs.freedesktop.org/show_bug.cgi?id=111304
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2642]: https://gitlab.freedesktop.org/drm/intel/issues/2642
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2733]: https://gitlab.freedesktop.org/drm/intel/issues/2733
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2795]: https://gitlab.freedesktop.org/drm/intel/issues/2795
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#307]: https://gitlab.freedesktop.org/drm/intel/issues/307
[i915#3160]: https://gitlab.freedesktop.org/drm/intel/issues/3160
[i915#3316]: https://gitlab.freedesktop.org/drm/intel/issues/3316
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#602]: https://gitlab.freedesktop.org/drm/intel/issues/602
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_10195 -> Patchwork_20318
CI-20190529: 20190529
CI_DRM_10195: 70e4d80795934312a3853a4f4f49445ce6db1271 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6103: 3aa79e55e73d4a49a5222e5dfde486b800a29fe7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_20318: a6745617acf0c89f578fcce067c052117a8a42aa @ git://ano
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20318/index.html
[-- Attachment #1.2: Type: text/html, Size: 38681 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 11:48 ` Daniel Vetter
-1 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2021-06-09 11:48 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx, matthew.auld, dri-devel
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
> A couple of patches from Chris which implement pipelined migration and
> clears by atomically writing the PTEs in place before performing the
> actual blit.
>
> Some ww utilities mainly for the accompanying selftests added by Thomas,
> as well as modified the above patches for ww locking- and lmem support.
>
> The actual hook up to the i915 ttm backend is being worked on and not
> included yet, so this is considered to be an early review opportunity.
>
> v2:
> - A couple of minor style fixes pointed out by Matthew Auld
> - Export and use intel_engine_destroy_pinned_context() to address a
>ls CI warning / failure.
Just to check my understanding of the plan: These are the new windowed
clear/blt functions which we plan to use everywhere, because less nasty
locking implications? And the clear/blt we currently have in upstream will
be replaced?
If so would be nice if this patch set includes that replacement work (I
think right now all we have is the clear for lmem), including updating of
selftests and stuff like that. Just to avoid having two ways to do the
same thing in the driver.
-Daniel
>
> Chris Wilson (6):
> drm/i915/gt: Add an insert_entry for gen8_ppgtt
> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
> drm/i915/gt: Export the pinned context constructor and destructor
> drm/i915/gt: Pipelined page migration
> drm/i915/gt: Pipelined clear
> drm/i915/gt: Setup a default migration context on the GT
>
> Thomas Hellström (3):
> drm/i915: Reference objects on the ww object list
> drm/i915: Break out dma_resv ww locking utilities to separate files
> drm/i915: Introduce a ww transaction helper
>
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
> drivers/gpu/drm/i915/i915_gem.c | 52 --
> drivers/gpu/drm/i915/i915_gem.h | 12 -
> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
> 21 files changed, 1675 insertions(+), 76 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 11:48 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2021-06-09 11:48 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx, matthew.auld, dri-devel
On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
> A couple of patches from Chris which implement pipelined migration and
> clears by atomically writing the PTEs in place before performing the
> actual blit.
>
> Some ww utilities mainly for the accompanying selftests added by Thomas,
> as well as modified the above patches for ww locking- and lmem support.
>
> The actual hook up to the i915 ttm backend is being worked on and not
> included yet, so this is considered to be an early review opportunity.
>
> v2:
> - A couple of minor style fixes pointed out by Matthew Auld
> - Export and use intel_engine_destroy_pinned_context() to address a
>ls CI warning / failure.
Just to check my understanding of the plan: These are the new windowed
clear/blt functions which we plan to use everywhere, because less nasty
locking implications? And the clear/blt we currently have in upstream will
be replaced?
If so would be nice if this patch set includes that replacement work (I
think right now all we have is the clear for lmem), including updating of
selftests and stuff like that. Just to avoid having two ways to do the
same thing in the driver.
-Daniel
>
> Chris Wilson (6):
> drm/i915/gt: Add an insert_entry for gen8_ppgtt
> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
> drm/i915/gt: Export the pinned context constructor and destructor
> drm/i915/gt: Pipelined page migration
> drm/i915/gt: Pipelined clear
> drm/i915/gt: Setup a default migration context on the GT
>
> Thomas Hellström (3):
> drm/i915: Reference objects on the ww object list
> drm/i915: Break out dma_resv ww locking utilities to separate files
> drm/i915: Introduce a ww transaction helper
>
> drivers/gpu/drm/i915/Makefile | 2 +
> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
> drivers/gpu/drm/i915/i915_gem.c | 52 --
> drivers/gpu/drm/i915/i915_gem.h | 12 -
> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
> 21 files changed, 1675 insertions(+), 76 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>
> --
> 2.31.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 12:14 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:14 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> If we pipeline the PTE updates and then do the copy of those pages
> within a single unpreemptible command packet, we can submit the copies
> and leave them to be scheduled without having to synchronously wait
> under a global lock. In order to manage migration, we need to
> preallocate the page tables (and keep them pinned and available for use
> at any time), causing a bottleneck for migrations as all clients must
> contend on the limited resources. By inlining the ppGTT updates and
> performing the blit atomically, each client only owns the PTE while in
> use, and so we can reschedule individual operations however we see fit.
> And most importantly, we do not need to take a global lock on the shared
> vm, and wait until the operation is complete before releasing the lock
> for others to claim the PTE for themselves.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> v2:
> - Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
> - Use intel_engine_destroy_pinned_context() to properly take the pinned
> context timeline off the engine list. (CI warning).
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 544 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 45 ++
> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 291 ++++++++++
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> 9 files changed, 901 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 16a5a006cf7c..95bd38e84625 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -108,6 +108,7 @@ gt-y += \
> gt/intel_gtt.o \
> gt/intel_llc.o \
> gt/intel_lrc.o \
> + gt/intel_migrate.o \
> gt/intel_mocs.o \
> gt/intel_ppgtt.o \
> gt/intel_rc6.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 36ea9eb52bb5..62f7440bc111 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -188,6 +188,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
> +#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
> #define I915_GEM_HWS_SCRATCH 0x80
>
> #define I915_HWS_CSB_BUF0_INDEX 0x10
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 2694dbb9967e..1c3af0fc0456 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -123,8 +123,10 @@
> #define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
> #define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
> #define MI_SEMAPHORE_TOKEN_SHIFT 5
> +#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
> #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
> #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
> +#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
> #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
> #define MI_USE_GGTT (1 << 22) /* g4x+ */
> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> new file mode 100644
> index 000000000000..70776316863d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -0,0 +1,544 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_context.h"
> +#include "intel_gpu_commands.h"
> +#include "intel_gt.h"
> +#include "intel_gtt.h"
> +#include "intel_migrate.h"
> +#include "intel_ring.h"
> +
> +struct insert_pte_data {
> + u64 offset;
> + bool is_lmem;
> +};
> +
> +#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> +
> +static bool engine_supports_migration(struct intel_engine_cs *engine)
> +{
> + if (!engine)
> + return false;
> +
> + /*
> + * We need the ability to prevent aribtration (MI_ARB_ON_OFF),
> + * the ability to write PTE using inline data (MI_STORE_DATA)
> + * and of course the ability to do the block transfer (blits).
> + */
> + GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);
> +
> + return true;
> +}
> +
> +static void insert_pte(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> +{
> + struct insert_pte_data *d = data;
> +
> + vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
> + d->is_lmem ? PTE_LM : 0);
> + d->offset += PAGE_SIZE;
> +}
> +
> +static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> +{
> + struct i915_vm_pt_stash stash = {};
> + struct i915_ppgtt *vm;
> + int err;
> + int i;
> +
> + /*
> + * We construct a very special VM for use by all migration contexts,
> + * it is kept pinned so that it can be used at any time. As we need
> + * to pre-allocate the page directories for the migration VM, this
> + * limits us to only using a small number of prepared vma.
> + *
> + * To be able to pipeline and reschedule migration operations while
> + * avoiding unnecessary contention on the vm itself, the PTE updates
> + * are inline with the blits. All the blits use the same fixed
> + * addresses, with the backing store redirection being updated on the
> + * fly. Only 2 implicit vma are used for all migration operations.
> + *
> + * We lay the ppGTT out as:
> + *
> + * [0, CHUNK_SZ) -> first object
> + * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object
> + * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE
> + *
> + * By exposing the dma addresses of the page directories themselves
> + * within the ppGTT, we are then able to rewrite the PTE prior to use.
> + * But the PTE update and subsequent migration operation must be atomic,
> + * i.e. within the same non-preemptible window so that we do not switch
> + * to another migration context that overwrites the PTE.
> + *
> + * TODO: Add support for huge LMEM PTEs
> + */
> +
> + vm = i915_ppgtt_create(gt);
> + if (IS_ERR(vm))
> + return ERR_CAST(vm);
> +
> + if (!vm->vm.allocate_va_range || !vm->vm.foreach) {
> + err = -ENODEV;
> + goto err_vm;
> + }
> +
> + /*
> + * Each engine instance is assigned its own chunk in the VM, so
> + * that we can run multiple instances concurrently
> + */
> + for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
> + struct intel_engine_cs *engine;
> + u64 base = (u64)i << 32;
> + struct insert_pte_data d = {};
> + struct i915_gem_ww_ctx ww;
> + u64 sz;
> +
> + engine = gt->engine_class[COPY_ENGINE_CLASS][i];
> + if (!engine_supports_migration(engine))
> + continue;
> +
> + /*
> + * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
> + * 4x2 page directories for source/destination.
> + */
> + sz = 2 * CHUNK_SZ;
> + d.offset = base + sz;
> +
> + /*
> + * We need another page directory setup so that we can write
> + * the 8x512 PTE in each chunk.
> + */
> + sz += (sz >> 12) * sizeof(u64);
That was quite the mind warp.
> +
> + err = i915_vm_alloc_pt_stash(&vm->vm, &stash, sz);
> + if (err)
> + goto err_vm;
> +
> + for_i915_gem_ww(&ww, err, true) {
> + err = i915_vm_lock_objects(&vm->vm, &ww);
> + if (err)
> + continue;
> + err = i915_vm_map_pt_stash(&vm->vm, &stash);
> + if (err)
> + continue;
> +
> + vm->vm.allocate_va_range(&vm->vm, &stash, base, base + sz);
I think here we meant:
allocate_va_range(.., base, sz)
Otherwise this might explode for instance > 0? Since the preallocated
stash is too small.
> + }
> + i915_vm_free_pt_stash(&vm->vm, &stash);
> + if (err)
> + goto err_vm;
> +
> + /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> + d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
> + vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
> + }
> +
> + return &vm->vm;
> +
> +err_vm:
> + i915_vm_put(&vm->vm);
> + return ERR_PTR(err);
> +}
> +
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
@ 2021-06-09 12:14 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:14 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> If we pipeline the PTE updates and then do the copy of those pages
> within a single unpreemptible command packet, we can submit the copies
> and leave them to be scheduled without having to synchronously wait
> under a global lock. In order to manage migration, we need to
> preallocate the page tables (and keep them pinned and available for use
> at any time), causing a bottleneck for migrations as all clients must
> contend on the limited resources. By inlining the ppGTT updates and
> performing the blit atomically, each client only owns the PTE while in
> use, and so we can reschedule individual operations however we see fit.
> And most importantly, we do not need to take a global lock on the shared
> vm, and wait until the operation is complete before releasing the lock
> for others to claim the PTE for themselves.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> v2:
> - Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
> - Use intel_engine_destroy_pinned_context() to properly take the pinned
> context timeline off the engine list. (CI warning).
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> drivers/gpu/drm/i915/gt/intel_engine.h | 1 +
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 544 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 45 ++
> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 291 ++++++++++
> .../drm/i915/selftests/i915_live_selftests.h | 1 +
> 9 files changed, 901 insertions(+)
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 16a5a006cf7c..95bd38e84625 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -108,6 +108,7 @@ gt-y += \
> gt/intel_gtt.o \
> gt/intel_llc.o \
> gt/intel_lrc.o \
> + gt/intel_migrate.o \
> gt/intel_mocs.o \
> gt/intel_ppgtt.o \
> gt/intel_rc6.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 36ea9eb52bb5..62f7440bc111 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -188,6 +188,7 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
> #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
> #define I915_GEM_HWS_SEQNO 0x40
> #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
> +#define I915_GEM_HWS_MIGRATE (0x42 * sizeof(u32))
> #define I915_GEM_HWS_SCRATCH 0x80
>
> #define I915_HWS_CSB_BUF0_INDEX 0x10
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 2694dbb9967e..1c3af0fc0456 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -123,8 +123,10 @@
> #define MI_SEMAPHORE_SAD_NEQ_SDD (5 << 12)
> #define MI_SEMAPHORE_TOKEN_MASK REG_GENMASK(9, 5)
> #define MI_SEMAPHORE_TOKEN_SHIFT 5
> +#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
> #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
> #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2)
> +#define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
> #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */
> #define MI_USE_GGTT (1 << 22) /* g4x+ */
> #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> new file mode 100644
> index 000000000000..70776316863d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -0,0 +1,544 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2020 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_context.h"
> +#include "intel_gpu_commands.h"
> +#include "intel_gt.h"
> +#include "intel_gtt.h"
> +#include "intel_migrate.h"
> +#include "intel_ring.h"
> +
> +struct insert_pte_data {
> + u64 offset;
> + bool is_lmem;
> +};
> +
> +#define CHUNK_SZ SZ_8M /* ~1ms at 8GiB/s preemption delay */
> +
> +static bool engine_supports_migration(struct intel_engine_cs *engine)
> +{
> + if (!engine)
> + return false;
> +
> + /*
> + * We need the ability to prevent aribtration (MI_ARB_ON_OFF),
> + * the ability to write PTE using inline data (MI_STORE_DATA)
> + * and of course the ability to do the block transfer (blits).
> + */
> + GEM_BUG_ON(engine->class != COPY_ENGINE_CLASS);
> +
> + return true;
> +}
> +
> +static void insert_pte(struct i915_address_space *vm,
> + struct i915_page_table *pt,
> + void *data)
> +{
> + struct insert_pte_data *d = data;
> +
> + vm->insert_page(vm, px_dma(pt), d->offset, I915_CACHE_NONE,
> + d->is_lmem ? PTE_LM : 0);
> + d->offset += PAGE_SIZE;
> +}
> +
> +static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> +{
> + struct i915_vm_pt_stash stash = {};
> + struct i915_ppgtt *vm;
> + int err;
> + int i;
> +
> + /*
> + * We construct a very special VM for use by all migration contexts,
> + * it is kept pinned so that it can be used at any time. As we need
> + * to pre-allocate the page directories for the migration VM, this
> + * limits us to only using a small number of prepared vma.
> + *
> + * To be able to pipeline and reschedule migration operations while
> + * avoiding unnecessary contention on the vm itself, the PTE updates
> + * are inline with the blits. All the blits use the same fixed
> + * addresses, with the backing store redirection being updated on the
> + * fly. Only 2 implicit vma are used for all migration operations.
> + *
> + * We lay the ppGTT out as:
> + *
> + * [0, CHUNK_SZ) -> first object
> + * [CHUNK_SZ, 2 * CHUNK_SZ) -> second object
> + * [2 * CHUNK_SZ, 2 * CHUNK_SZ + 2 * CHUNK_SZ >> 9] -> PTE
> + *
> + * By exposing the dma addresses of the page directories themselves
> + * within the ppGTT, we are then able to rewrite the PTE prior to use.
> + * But the PTE update and subsequent migration operation must be atomic,
> + * i.e. within the same non-preemptible window so that we do not switch
> + * to another migration context that overwrites the PTE.
> + *
> + * TODO: Add support for huge LMEM PTEs
> + */
> +
> + vm = i915_ppgtt_create(gt);
> + if (IS_ERR(vm))
> + return ERR_CAST(vm);
> +
> + if (!vm->vm.allocate_va_range || !vm->vm.foreach) {
> + err = -ENODEV;
> + goto err_vm;
> + }
> +
> + /*
> + * Each engine instance is assigned its own chunk in the VM, so
> + * that we can run multiple instances concurrently
> + */
> + for (i = 0; i < ARRAY_SIZE(gt->engine_class[COPY_ENGINE_CLASS]); i++) {
> + struct intel_engine_cs *engine;
> + u64 base = (u64)i << 32;
> + struct insert_pte_data d = {};
> + struct i915_gem_ww_ctx ww;
> + u64 sz;
> +
> + engine = gt->engine_class[COPY_ENGINE_CLASS][i];
> + if (!engine_supports_migration(engine))
> + continue;
> +
> + /*
> + * We copy in 8MiB chunks. Each PDE covers 2MiB, so we need
> + * 4x2 page directories for source/destination.
> + */
> + sz = 2 * CHUNK_SZ;
> + d.offset = base + sz;
> +
> + /*
> + * We need another page directory setup so that we can write
> + * the 8x512 PTE in each chunk.
> + */
> + sz += (sz >> 12) * sizeof(u64);
That was quite the mind warp.
> +
> + err = i915_vm_alloc_pt_stash(&vm->vm, &stash, sz);
> + if (err)
> + goto err_vm;
> +
> + for_i915_gem_ww(&ww, err, true) {
> + err = i915_vm_lock_objects(&vm->vm, &ww);
> + if (err)
> + continue;
> + err = i915_vm_map_pt_stash(&vm->vm, &stash);
> + if (err)
> + continue;
> +
> + vm->vm.allocate_va_range(&vm->vm, &stash, base, base + sz);
I think here we meant:
allocate_va_range(.., base, sz)
Otherwise this might explode for instance > 0? Since the preallocated
stash is too small.
> + }
> + i915_vm_free_pt_stash(&vm->vm, &stash);
> + if (err)
> + goto err_vm;
> +
> + /* Now allow the GPU to rewrite the PTE via its own ppGTT */
> + d.is_lmem = i915_gem_object_is_lmem(vm->vm.scratch[0]);
> + vm->vm.foreach(&vm->vm, base, base + sz, insert_pte, &d);
> + }
> +
> + return &vm->vm;
> +
> +err_vm:
> + i915_vm_put(&vm->vm);
> + return ERR_PTR(err);
> +}
> +
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 11:48 ` Daniel Vetter
@ 2021-06-09 12:16 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 12:16 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, matthew.auld, dri-devel
On 6/9/21 1:48 PM, Daniel Vetter wrote:
> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>> A couple of patches from Chris which implement pipelined migration and
>> clears by atomically writing the PTEs in place before performing the
>> actual blit.
>>
>> Some ww utilities mainly for the accompanying selftests added by Thomas,
>> as well as modified the above patches for ww locking- and lmem support.
>>
>> The actual hook up to the i915 ttm backend is being worked on and not
>> included yet, so this is considered to be an early review opportunity.
>>
>> v2:
>> - A couple of minor style fixes pointed out by Matthew Auld
>> - Export and use intel_engine_destroy_pinned_context() to address a
>> ls CI warning / failure.
> Just to check my understanding of the plan: These are the new windowed
> clear/blt functions which we plan to use everywhere, because less nasty
> locking implications? And the clear/blt we currently have in upstream will
> be replaced?
Yes. These are for LMEM clearing and migration. It looks to me like the
other ones we have in upstream are actually unused except for selftests.
We're actually using CPU clearing for now.
>
> If so would be nice if this patch set includes that replacement work (I
> think right now all we have is the clear for lmem), including updating of
> selftests and stuff like that. Just to avoid having two ways to do the
> same thing in the driver.
OK, I'll have a look at stripping the existing code. If we need it
moving forward, we can always re-add.
/Thomas
> -Daniel
>
>> Chris Wilson (6):
>> drm/i915/gt: Add an insert_entry for gen8_ppgtt
>> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
>> drm/i915/gt: Export the pinned context constructor and destructor
>> drm/i915/gt: Pipelined page migration
>> drm/i915/gt: Pipelined clear
>> drm/i915/gt: Setup a default migration context on the GT
>>
>> Thomas Hellström (3):
>> drm/i915: Reference objects on the ww object list
>> drm/i915: Break out dma_resv ww locking utilities to separate files
>> drm/i915: Introduce a ww transaction helper
>>
>> drivers/gpu/drm/i915/Makefile | 2 +
>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
>> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
>> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
>> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
>> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
>> drivers/gpu/drm/i915/i915_gem.c | 52 --
>> drivers/gpu/drm/i915/i915_gem.h | 12 -
>> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
>> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
>> .../drm/i915/selftests/i915_live_selftests.h | 1 +
>> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
>> 21 files changed, 1675 insertions(+), 76 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>>
>> --
>> 2.31.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 12:16 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 12:16 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, matthew.auld, dri-devel
On 6/9/21 1:48 PM, Daniel Vetter wrote:
> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>> A couple of patches from Chris which implement pipelined migration and
>> clears by atomically writing the PTEs in place before performing the
>> actual blit.
>>
>> Some ww utilities mainly for the accompanying selftests added by Thomas,
>> as well as modified the above patches for ww locking- and lmem support.
>>
>> The actual hook up to the i915 ttm backend is being worked on and not
>> included yet, so this is considered to be an early review opportunity.
>>
>> v2:
>> - A couple of minor style fixes pointed out by Matthew Auld
>> - Export and use intel_engine_destroy_pinned_context() to address a
>> ls CI warning / failure.
> Just to check my understanding of the plan: These are the new windowed
> clear/blt functions which we plan to use everywhere, because less nasty
> locking implications? And the clear/blt we currently have in upstream will
> be replaced?
Yes. These are for LMEM clearing and migration. It looks to me like the
other ones we have in upstream are actually unused except for selftests.
We're actually using CPU clearing for now.
>
> If so would be nice if this patch set includes that replacement work (I
> think right now all we have is the clear for lmem), including updating of
> selftests and stuff like that. Just to avoid having two ways to do the
> same thing in the driver.
OK, I'll have a look at stripping the existing code. If we need it
moving forward, we can always re-add.
/Thomas
> -Daniel
>
>> Chris Wilson (6):
>> drm/i915/gt: Add an insert_entry for gen8_ppgtt
>> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
>> drm/i915/gt: Export the pinned context constructor and destructor
>> drm/i915/gt: Pipelined page migration
>> drm/i915/gt: Pipelined clear
>> drm/i915/gt: Setup a default migration context on the GT
>>
>> Thomas Hellström (3):
>> drm/i915: Reference objects on the ww object list
>> drm/i915: Break out dma_resv ww locking utilities to separate files
>> drm/i915: Introduce a ww transaction helper
>>
>> drivers/gpu/drm/i915/Makefile | 2 +
>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
>> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
>> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
>> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
>> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
>> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
>> drivers/gpu/drm/i915/i915_gem.c | 52 --
>> drivers/gpu/drm/i915/i915_gem.h | 12 -
>> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
>> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
>> .../drm/i915/selftests/i915_live_selftests.h | 1 +
>> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
>> 21 files changed, 1675 insertions(+), 76 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>>
>> --
>> 2.31.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 12:16 ` Thomas Hellström
@ 2021-06-09 12:20 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:20 UTC (permalink / raw)
To: Thomas Hellström, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 09/06/2021 13:16, Thomas Hellström wrote:
>
> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>> A couple of patches from Chris which implement pipelined migration and
>>> clears by atomically writing the PTEs in place before performing the
>>> actual blit.
>>>
>>> Some ww utilities mainly for the accompanying selftests added by Thomas,
>>> as well as modified the above patches for ww locking- and lmem support.
>>>
>>> The actual hook up to the i915 ttm backend is being worked on and not
>>> included yet, so this is considered to be an early review opportunity.
>>>
>>> v2:
>>> - A couple of minor style fixes pointed out by Matthew Auld
>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>> ls CI warning / failure.
>> Just to check my understanding of the plan: These are the new windowed
>> clear/blt functions which we plan to use everywhere, because less nasty
>> locking implications? And the clear/blt we currently have in upstream
>> will
>> be replaced?
>
> Yes. These are for LMEM clearing and migration. It looks to me like the
> other ones we have in upstream are actually unused except for selftests.
> We're actually using CPU clearing for now.
>
>>
>> If so would be nice if this patch set includes that replacement work (I
>> think right now all we have is the clear for lmem), including updating of
>> selftests and stuff like that. Just to avoid having two ways to do the
>> same thing in the driver.
>
> OK, I'll have a look at stripping the existing code. If we need it
> moving forward, we can always re-add.
Some low hanging fruit would be all the client_blt stuff which can for
sure be deleted now.
>
> /Thomas
>
>
>> -Daniel
>>
>>> Chris Wilson (6):
>>> drm/i915/gt: Add an insert_entry for gen8_ppgtt
>>> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
>>> drm/i915/gt: Export the pinned context constructor and destructor
>>> drm/i915/gt: Pipelined page migration
>>> drm/i915/gt: Pipelined clear
>>> drm/i915/gt: Setup a default migration context on the GT
>>>
>>> Thomas Hellström (3):
>>> drm/i915: Reference objects on the ww object list
>>> drm/i915: Break out dma_resv ww locking utilities to separate files
>>> drm/i915: Introduce a ww transaction helper
>>>
>>> drivers/gpu/drm/i915/Makefile | 2 +
>>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
>>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
>>> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
>>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
>>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
>>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>>> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
>>> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
>>> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
>>> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
>>> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
>>> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
>>> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
>>> drivers/gpu/drm/i915/i915_gem.c | 52 --
>>> drivers/gpu/drm/i915/i915_gem.h | 12 -
>>> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
>>> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
>>> .../drm/i915/selftests/i915_live_selftests.h | 1 +
>>> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
>>> 21 files changed, 1675 insertions(+), 76 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
>>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
>>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>>>
>>> --
>>> 2.31.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 12:20 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:20 UTC (permalink / raw)
To: Thomas Hellström, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 09/06/2021 13:16, Thomas Hellström wrote:
>
> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>> A couple of patches from Chris which implement pipelined migration and
>>> clears by atomically writing the PTEs in place before performing the
>>> actual blit.
>>>
>>> Some ww utilities mainly for the accompanying selftests added by Thomas,
>>> as well as modified the above patches for ww locking- and lmem support.
>>>
>>> The actual hook up to the i915 ttm backend is being worked on and not
>>> included yet, so this is considered to be an early review opportunity.
>>>
>>> v2:
>>> - A couple of minor style fixes pointed out by Matthew Auld
>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>> ls CI warning / failure.
>> Just to check my understanding of the plan: These are the new windowed
>> clear/blt functions which we plan to use everywhere, because less nasty
>> locking implications? And the clear/blt we currently have in upstream
>> will
>> be replaced?
>
> Yes. These are for LMEM clearing and migration. It looks to me like the
> other ones we have in upstream are actually unused except for selftests.
> We're actually using CPU clearing for now.
>
>>
>> If so would be nice if this patch set includes that replacement work (I
>> think right now all we have is the clear for lmem), including updating of
>> selftests and stuff like that. Just to avoid having two ways to do the
>> same thing in the driver.
>
> OK, I'll have a look at stripping the existing code. If we need it
> moving forward, we can always re-add.
Some low hanging fruit would be all the client_blt stuff which can for
sure be deleted now.
>
> /Thomas
>
>
>> -Daniel
>>
>>> Chris Wilson (6):
>>> drm/i915/gt: Add an insert_entry for gen8_ppgtt
>>> drm/i915/gt: Add a routine to iterate over the pagetables of a GTT
>>> drm/i915/gt: Export the pinned context constructor and destructor
>>> drm/i915/gt: Pipelined page migration
>>> drm/i915/gt: Pipelined clear
>>> drm/i915/gt: Setup a default migration context on the GT
>>>
>>> Thomas Hellström (3):
>>> drm/i915: Reference objects on the ww object list
>>> drm/i915: Break out dma_resv ww locking utilities to separate files
>>> drm/i915: Introduce a ww transaction helper
>>>
>>> drivers/gpu/drm/i915/Makefile | 2 +
>>> drivers/gpu/drm/i915/gem/i915_gem_object.h | 9 +-
>>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 68 ++
>>> drivers/gpu/drm/i915/gt/intel_engine.h | 12 +
>>> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 27 +-
>>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +
>>> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
>>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
>>> drivers/gpu/drm/i915/gt/intel_gtt.h | 7 +
>>> drivers/gpu/drm/i915/gt/intel_migrate.c | 685 ++++++++++++++++++
>>> drivers/gpu/drm/i915/gt/intel_migrate.h | 65 ++
>>> drivers/gpu/drm/i915/gt/intel_migrate_types.h | 15 +
>>> drivers/gpu/drm/i915/gt/intel_renderstate.h | 1 +
>>> drivers/gpu/drm/i915/gt/intel_ring.h | 1 +
>>> drivers/gpu/drm/i915/gt/selftest_migrate.c | 671 +++++++++++++++++
>>> drivers/gpu/drm/i915/i915_gem.c | 52 --
>>> drivers/gpu/drm/i915/i915_gem.h | 12 -
>>> drivers/gpu/drm/i915/i915_gem_ww.c | 63 ++
>>> drivers/gpu/drm/i915/i915_gem_ww.h | 50 ++
>>> .../drm/i915/selftests/i915_live_selftests.h | 1 +
>>> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
>>> 21 files changed, 1675 insertions(+), 76 deletions(-)
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.c
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate.h
>>> create mode 100644 drivers/gpu/drm/i915/gt/intel_migrate_types.h
>>> create mode 100644 drivers/gpu/drm/i915/gt/selftest_migrate.c
>>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.c
>>> create mode 100644 drivers/gpu/drm/i915/i915_gem_ww.h
>>>
>>> --
>>> 2.31.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 12:48 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:48 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> If we pipeline the PTE updates and then do the copy of those pages
> within a single unpreemptible command packet, we can submit the copies
> and leave them to be scheduled without having to synchronously wait
> under a global lock. In order to manage migration, we need to
> preallocate the page tables (and keep them pinned and available for use
> at any time), causing a bottleneck for migrations as all clients must
> contend on the limited resources. By inlining the ppGTT updates and
> performing the blit atomically, each client only owns the PTE while in
> use, and so we can reschedule individual operations however we see fit.
> And most importantly, we do not need to take a global lock on the shared
> vm, and wait until the operation is complete before releasing the lock
> for others to claim the PTE for themselves.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> v2:
> - Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
> - Use intel_engine_destroy_pinned_context() to properly take the pinned
> context timeline off the engine list. (CI warning).
> ---
<snip>
> +
> +int
> +intel_context_migrate_copy(struct intel_context *ce,
> + struct dma_fence *await,
> + struct scatterlist *src,
> + enum i915_cache_level src_cache_level,
> + bool src_is_lmem,
> + struct scatterlist *dst,
> + enum i915_cache_level dst_cache_level,
> + bool dst_is_lmem,
> + struct i915_request **out)
> +{
> + struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
> + struct i915_request *rq;
> + int err;
> +
> + *out = NULL;
> +
> + /* GEM_BUG_ON(ce->vm != migrate_vm); */
Should we drop this?
> +
> + GEM_BUG_ON(ce->ring->size < SZ_64K);
> +
> + do {
> + int len;
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto out_ce;
> + }
> +
> + if (await) {
> + err = i915_request_await_dma_fence(rq, await);
> + if (err)
> + goto out_rq;
> +
> + if (rq->engine->emit_init_breadcrumb) {
> + err = rq->engine->emit_init_breadcrumb(rq);
> + if (err)
> + goto out_rq;
> + }
> +
> + await = NULL;
> + }
> +
> + /* The PTE updates + copy must not be interrupted. */
> + err = emit_no_arbitration(rq);
> + if (err)
> + goto out_rq;
> +
> + len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem, 0,
> + CHUNK_SZ);
> + if (len <= 0) {
> + err = len;
> + goto out_rq;
> + }
> +
> + err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
> + CHUNK_SZ, len);
> + if (err < 0)
> + goto out_rq;
> + if (err < len) {
> + err = -EINVAL;
> + goto out_rq;
> + }
> +
> + err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (err)
> + goto out_rq;
> +
> + err = emit_copy(rq, len);
> +
> + /* Arbitration is re-enabled between requests. */
> +out_rq:
> + if (*out)
> + i915_request_put(*out);
> + *out = i915_request_get(rq);
> + i915_request_add(rq);
> + if (err || !it_src.sg || !sg_dma_len(it_src.sg))
> + break;
> +
> + cond_resched();
> + } while (1);
> +
> +out_ce:
> + return err;
> +}
> +
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/9] drm/i915/gt: Pipelined page migration
@ 2021-06-09 12:48 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 12:48 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> If we pipeline the PTE updates and then do the copy of those pages
> within a single unpreemptible command packet, we can submit the copies
> and leave them to be scheduled without having to synchronously wait
> under a global lock. In order to manage migration, we need to
> preallocate the page tables (and keep them pinned and available for use
> at any time), causing a bottleneck for migrations as all clients must
> contend on the limited resources. By inlining the ppGTT updates and
> performing the blit atomically, each client only owns the PTE while in
> use, and so we can reschedule individual operations however we see fit.
> And most importantly, we do not need to take a global lock on the shared
> vm, and wait until the operation is complete before releasing the lock
> for others to claim the PTE for themselves.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> v2:
> - Add a TODO for huge LMEM ptes (Pointed out by Matthew Auld)
> - Use intel_engine_destroy_pinned_context() to properly take the pinned
> context timeline off the engine list. (CI warning).
> ---
<snip>
> +
> +int
> +intel_context_migrate_copy(struct intel_context *ce,
> + struct dma_fence *await,
> + struct scatterlist *src,
> + enum i915_cache_level src_cache_level,
> + bool src_is_lmem,
> + struct scatterlist *dst,
> + enum i915_cache_level dst_cache_level,
> + bool dst_is_lmem,
> + struct i915_request **out)
> +{
> + struct sgt_dma it_src = sg_sgt(src), it_dst = sg_sgt(dst);
> + struct i915_request *rq;
> + int err;
> +
> + *out = NULL;
> +
> + /* GEM_BUG_ON(ce->vm != migrate_vm); */
Should we drop this?
> +
> + GEM_BUG_ON(ce->ring->size < SZ_64K);
> +
> + do {
> + int len;
> +
> + rq = i915_request_create(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto out_ce;
> + }
> +
> + if (await) {
> + err = i915_request_await_dma_fence(rq, await);
> + if (err)
> + goto out_rq;
> +
> + if (rq->engine->emit_init_breadcrumb) {
> + err = rq->engine->emit_init_breadcrumb(rq);
> + if (err)
> + goto out_rq;
> + }
> +
> + await = NULL;
> + }
> +
> + /* The PTE updates + copy must not be interrupted. */
> + err = emit_no_arbitration(rq);
> + if (err)
> + goto out_rq;
> +
> + len = emit_pte(rq, &it_src, src_cache_level, src_is_lmem, 0,
> + CHUNK_SZ);
> + if (len <= 0) {
> + err = len;
> + goto out_rq;
> + }
> +
> + err = emit_pte(rq, &it_dst, dst_cache_level, dst_is_lmem,
> + CHUNK_SZ, len);
> + if (err < 0)
> + goto out_rq;
> + if (err < len) {
> + err = -EINVAL;
> + goto out_rq;
> + }
> +
> + err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
> + if (err)
> + goto out_rq;
> +
> + err = emit_copy(rq, len);
> +
> + /* Arbitration is re-enabled between requests. */
> +out_rq:
> + if (*out)
> + i915_request_put(*out);
> + *out = i915_request_get(rq);
> + i915_request_add(rq);
> + if (err || !it_src.sg || !sg_dma_len(it_src.sg))
> + break;
> +
> + cond_resched();
> + } while (1);
> +
> +out_ce:
> + return err;
> +}
> +
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 12:20 ` Matthew Auld
@ 2021-06-09 13:08 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 13:08 UTC (permalink / raw)
To: Matthew Auld, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 6/9/21 2:20 PM, Matthew Auld wrote:
> On 09/06/2021 13:16, Thomas Hellström wrote:
>>
>> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>>> A couple of patches from Chris which implement pipelined migration and
>>>> clears by atomically writing the PTEs in place before performing the
>>>> actual blit.
>>>>
>>>> Some ww utilities mainly for the accompanying selftests added by
>>>> Thomas,
>>>> as well as modified the above patches for ww locking- and lmem
>>>> support.
>>>>
>>>> The actual hook up to the i915 ttm backend is being worked on and not
>>>> included yet, so this is considered to be an early review opportunity.
>>>>
>>>> v2:
>>>> - A couple of minor style fixes pointed out by Matthew Auld
>>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>>> ls CI warning / failure.
>>> Just to check my understanding of the plan: These are the new windowed
>>> clear/blt functions which we plan to use everywhere, because less nasty
>>> locking implications? And the clear/blt we currently have in
>>> upstream will
>>> be replaced?
>>
>> Yes. These are for LMEM clearing and migration. It looks to me like
>> the other ones we have in upstream are actually unused except for
>> selftests. We're actually using CPU clearing for now.
>>
>>>
>>> If so would be nice if this patch set includes that replacement work (I
>>> think right now all we have is the clear for lmem), including
>>> updating of
>>> selftests and stuff like that. Just to avoid having two ways to do the
>>> same thing in the driver.
>>
>> OK, I'll have a look at stripping the existing code. If we need it
>> moving forward, we can always re-add.
>
> Some low hanging fruit would be all the client_blt stuff which can for
> sure be deleted now.
What has the client_blt stuff been used for?
In any case, I need 25 commits for commit access to be granted.
/Thomas
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 13:08 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 13:08 UTC (permalink / raw)
To: Matthew Auld, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 6/9/21 2:20 PM, Matthew Auld wrote:
> On 09/06/2021 13:16, Thomas Hellström wrote:
>>
>> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>>> A couple of patches from Chris which implement pipelined migration and
>>>> clears by atomically writing the PTEs in place before performing the
>>>> actual blit.
>>>>
>>>> Some ww utilities mainly for the accompanying selftests added by
>>>> Thomas,
>>>> as well as modified the above patches for ww locking- and lmem
>>>> support.
>>>>
>>>> The actual hook up to the i915 ttm backend is being worked on and not
>>>> included yet, so this is considered to be an early review opportunity.
>>>>
>>>> v2:
>>>> - A couple of minor style fixes pointed out by Matthew Auld
>>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>>> ls CI warning / failure.
>>> Just to check my understanding of the plan: These are the new windowed
>>> clear/blt functions which we plan to use everywhere, because less nasty
>>> locking implications? And the clear/blt we currently have in
>>> upstream will
>>> be replaced?
>>
>> Yes. These are for LMEM clearing and migration. It looks to me like
>> the other ones we have in upstream are actually unused except for
>> selftests. We're actually using CPU clearing for now.
>>
>>>
>>> If so would be nice if this patch set includes that replacement work (I
>>> think right now all we have is the clear for lmem), including
>>> updating of
>>> selftests and stuff like that. Just to avoid having two ways to do the
>>> same thing in the driver.
>>
>> OK, I'll have a look at stripping the existing code. If we need it
>> moving forward, we can always re-add.
>
> Some low hanging fruit would be all the client_blt stuff which can for
> sure be deleted now.
What has the client_blt stuff been used for?
In any case, I need 25 commits for commit access to be granted.
/Thomas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 8/9] drm/i915/gt: Pipelined clear
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 13:42 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 13:42 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Update the PTE and emit a clear within a single unpreemptible packet
> such that we can schedule and pipeline clears.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 141 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 20 +++
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 163 +++++++++++++++++++++
> 3 files changed, 324 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 70776316863d..fda05ce3eb9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -490,6 +490,112 @@ intel_context_migrate_copy(struct intel_context *ce,
> return err;
> }
>
> +static int emit_clear(struct i915_request *rq, int size, u32 value)
> +{
> + const int gen = INTEL_GEN(rq->engine->i915);
> + u32 *cs;
> +
> + GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
> +
> + cs = intel_ring_begin(rq, gen >= 8 ? 8 : 6);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + if (gen >= 8) {
> + *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cs++ = 0;
> + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cs++ = 0; /* offset */
> + *cs++ = 0;
Missing feeding the engine instance into the upper dword for the offset?
> + *cs++ = value;
> + *cs++ = MI_NOOP;
> + } else {
> + *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cs++ = 0;
> + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cs++ = 0;
> + *cs++ = value;
> + }
> +
> + intel_ring_advance(rq, cs);
> + return 0;
> +}
> +
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 8/9] drm/i915/gt: Pipelined clear
@ 2021-06-09 13:42 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 13:42 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Update the PTE and emit a clear within a single unpreemptible packet
> such that we can schedule and pipeline clears.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_migrate.c | 141 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_migrate.h | 20 +++
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 163 +++++++++++++++++++++
> 3 files changed, 324 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 70776316863d..fda05ce3eb9c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -490,6 +490,112 @@ intel_context_migrate_copy(struct intel_context *ce,
> return err;
> }
>
> +static int emit_clear(struct i915_request *rq, int size, u32 value)
> +{
> + const int gen = INTEL_GEN(rq->engine->i915);
> + u32 *cs;
> +
> + GEM_BUG_ON(size >> PAGE_SHIFT > S16_MAX);
> +
> + cs = intel_ring_begin(rq, gen >= 8 ? 8 : 6);
> + if (IS_ERR(cs))
> + return PTR_ERR(cs);
> +
> + if (gen >= 8) {
> + *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (7 - 2);
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cs++ = 0;
> + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cs++ = 0; /* offset */
> + *cs++ = 0;
Missing feeding the engine instance into the upper dword for the offset?
> + *cs++ = value;
> + *cs++ = MI_NOOP;
> + } else {
> + *cs++ = XY_COLOR_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | PAGE_SIZE;
> + *cs++ = 0;
> + *cs++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> + *cs++ = 0;
> + *cs++ = value;
> + }
> +
> + intel_ring_advance(rq, cs);
> + return 0;
> +}
> +
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [PATCH v2 9/9] drm/i915/gt: Setup a default migration context on the GT
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
@ 2021-06-09 14:17 ` Matthew Auld
-1 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 14:17 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Set up a default migration context on the GT and use it from the
> selftests.
> Add a perf selftest and make sure we exercise LMEM if available.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 227 +++++++++++++++++-
> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
> 5 files changed, 232 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..67ef057ae918 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -13,6 +13,7 @@
> #include "intel_gt_clock_utils.h"
> #include "intel_gt_pm.h"
> #include "intel_gt_requests.h"
> +#include "intel_migrate.h"
> #include "intel_mocs.h"
> #include "intel_rc6.h"
> #include "intel_renderstate.h"
> @@ -626,6 +627,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_migrate_init(>->migrate, gt);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -649,6 +652,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
> {
> __intel_gt_disable(gt);
>
> + intel_migrate_fini(>->migrate);
> intel_uc_driver_remove(>->uc);
>
> intel_engines_release(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index fecfacf551d5..7450935f2ca8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -24,6 +24,7 @@
> #include "intel_reset_types.h"
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> +#include "intel_migrate_types.h"
> #include "intel_wakeref.h"
>
> struct drm_i915_private;
> @@ -145,6 +146,8 @@ struct intel_gt {
>
> struct i915_vma *scratch;
>
> + struct intel_migrate migrate;
> +
> struct intel_gt_info {
> intel_engine_mask_t engine_mask;
> u8 num_engines;
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index fda05ce3eb9c..935b5f14ff21 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -418,10 +418,9 @@ intel_context_migrate_copy(struct intel_context *ce,
> struct i915_request *rq;
> int err;
>
> + GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
> *out = NULL;
>
> - /* GEM_BUG_ON(ce->vm != migrate_vm); */
> -
> GEM_BUG_ON(ce->ring->size < SZ_64K);
>
> do {
> @@ -536,6 +535,7 @@ intel_context_migrate_clear(struct intel_context *ce,
> struct i915_request *rq;
> int err;
>
> + GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
> *out = NULL;
>
> GEM_BUG_ON(ce->ring->size < SZ_64K);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
> index 159c8656e1b0..396c81364399 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
> @@ -3,6 +3,8 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/sort.h>
> +
> #include "selftests/i915_random.h"
>
> static const unsigned int sizes[] = {
> @@ -441,14 +443,229 @@ int intel_migrate_live_selftests(struct drm_i915_private *i915)
> SUBTEST(thread_global_copy),
> SUBTEST(thread_global_clear),
> };
> - struct intel_migrate m;
> + struct intel_gt *gt = &i915->gt;
> +
> + if (!gt->migrate.context)
> + return 0;
> +
> + return i915_subtests(tests, >->migrate);
> +}
> +
> +static struct drm_i915_gem_object *
> +create_init_lmem_internal(struct intel_gt *gt, size_t sz, bool try_lmem)
> +{
> + struct drm_i915_gem_object *obj = NULL;
> int err;
>
> - if (intel_migrate_init(&m, &i915->gt))
> + if (try_lmem && HAS_LMEM(gt->i915))
Could drop the HAS_LMEM()
It's elsewhere in the driver normal to just do:
obj = create_lmem()
if (IS_ERR(obj))
obj = create_internal()
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> + obj = i915_gem_object_create_lmem(gt->i915, sz, 0);
> +
> + if (IS_ERR_OR_NULL(obj)) {
> + obj = i915_gem_object_create_internal(gt->i915, sz);
> + if (IS_ERR(obj))
> + return obj;
> + }
> +
> + i915_gem_object_trylock(obj);
> + err = i915_gem_object_pin_pages(obj);
> + if (err) {
> + i915_gem_object_unlock(obj);
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> + }
> +
> + return obj;
> +}
> +
> +static int wrap_ktime_compare(const void *A, const void *B)
> +{
> + const ktime_t *a = A, *b = B;
> +
> + return ktime_compare(*a, *b);
> +}
> +
> +static int __perf_clear_blt(struct intel_context *ce,
> + struct scatterlist *sg,
> + enum i915_cache_level cache_level,
> + bool is_lmem,
> + size_t sz)
> +{
> + ktime_t t[5];
> + int pass;
> + int err = 0;
> +
> + for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
> + struct i915_request *rq;
> + ktime_t t0, t1;
> +
> + t0 = ktime_get();
> +
> + err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
> + is_lmem, 0, &rq);
> + if (rq) {
> + if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
> + err = -EIO;
> + i915_request_put(rq);
> + }
> + if (err)
> + break;
> +
> + t1 = ktime_get();
> + t[pass] = ktime_sub(t1, t0);
> + }
> + if (err)
> + return err;
> +
> + sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> + pr_info("%s: %zd KiB fill: %lld MiB/s\n",
> + ce->engine->name, sz >> 10,
> + div64_u64(mul_u32_u32(4 * sz,
> + 1000 * 1000 * 1000),
> + t[1] + 2 * t[2] + t[3]) >> 20);
> + return 0;
> +}
> +
> +static int perf_clear_blt(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + static const unsigned long sizes[] = {
> + SZ_4K,
> + SZ_64K,
> + SZ_2M,
> + SZ_64M
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(sizes); i++) {
> + struct drm_i915_gem_object *dst;
> + int err;
> +
> + dst = create_init_lmem_internal(gt, sizes[i], true);
> + if (IS_ERR(dst))
> + return PTR_ERR(dst);
> +
> + err = __perf_clear_blt(gt->migrate.context,
> + dst->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(dst),
> + sizes[i]);
> +
> + i915_gem_object_unlock(dst);
> + i915_gem_object_put(dst);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int __perf_copy_blt(struct intel_context *ce,
> + struct scatterlist *src,
> + enum i915_cache_level src_cache_level,
> + bool src_is_lmem,
> + struct scatterlist *dst,
> + enum i915_cache_level dst_cache_level,
> + bool dst_is_lmem,
> + size_t sz)
> +{
> + ktime_t t[5];
> + int pass;
> + int err = 0;
> +
> + for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
> + struct i915_request *rq;
> + ktime_t t0, t1;
> +
> + t0 = ktime_get();
> +
> + err = intel_context_migrate_copy(ce, NULL,
> + src, src_cache_level,
> + src_is_lmem,
> + dst, dst_cache_level,
> + dst_is_lmem,
> + &rq);
> + if (rq) {
> + if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
> + err = -EIO;
> + i915_request_put(rq);
> + }
> + if (err)
> + break;
> +
> + t1 = ktime_get();
> + t[pass] = ktime_sub(t1, t0);
> + }
> + if (err)
> + return err;
> +
> + sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> + pr_info("%s: %zd KiB copy: %lld MiB/s\n",
> + ce->engine->name, sz >> 10,
> + div64_u64(mul_u32_u32(4 * sz,
> + 1000 * 1000 * 1000),
> + t[1] + 2 * t[2] + t[3]) >> 20);
> + return 0;
> +}
> +
> +static int perf_copy_blt(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + static const unsigned long sizes[] = {
> + SZ_4K,
> + SZ_64K,
> + SZ_2M,
> + SZ_64M
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(sizes); i++) {
> + struct drm_i915_gem_object *src, *dst;
> + int err;
> +
> + src = create_init_lmem_internal(gt, sizes[i], true);
> + if (IS_ERR(src))
> + return PTR_ERR(src);
> +
> + dst = create_init_lmem_internal(gt, sizes[i], false);
> + if (IS_ERR(dst)) {
> + err = PTR_ERR(dst);
> + goto err_src;
> + }
> +
> + err = __perf_copy_blt(gt->migrate.context,
> + src->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(src),
> + dst->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(dst),
> + sizes[i]);
> +
> + i915_gem_object_unlock(dst);
> + i915_gem_object_put(dst);
> +err_src:
> + i915_gem_object_unlock(src);
> + i915_gem_object_put(src);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +int intel_migrate_perf_selftests(struct drm_i915_private *i915)
> +{
> + static const struct i915_subtest tests[] = {
> + SUBTEST(perf_clear_blt),
> + SUBTEST(perf_copy_blt),
> + };
> + struct intel_gt *gt = &i915->gt;
> +
> + if (intel_gt_is_wedged(gt))
> return 0;
>
> - err = i915_subtests(tests, &m);
> - intel_migrate_fini(&m);
> + if (!gt->migrate.context)
> + return 0;
>
> - return err;
> + return intel_gt_live_subtests(tests, gt);
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> index c2389f8a257d..5077dc3c3b8c 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> @@ -17,5 +17,6 @@
> */
> selftest(engine_cs, intel_engine_cs_perf_selftests)
> selftest(request, i915_request_perf_selftests)
> +selftest(migrate, intel_migrate_perf_selftests)
> selftest(blt, i915_gem_object_blt_perf_selftests)
> selftest(region, intel_memory_region_perf_selftests)
>
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 9/9] drm/i915/gt: Setup a default migration context on the GT
@ 2021-06-09 14:17 ` Matthew Auld
0 siblings, 0 replies; 50+ messages in thread
From: Matthew Auld @ 2021-06-09 14:17 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: Chris Wilson
On 09/06/2021 07:34, Thomas Hellström wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Set up a default migration context on the GT and use it from the
> selftests.
> Add a perf selftest and make sure we exercise LMEM if available.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 +
> drivers/gpu/drm/i915/gt/intel_migrate.c | 4 +-
> drivers/gpu/drm/i915/gt/selftest_migrate.c | 227 +++++++++++++++++-
> .../drm/i915/selftests/i915_perf_selftests.h | 1 +
> 5 files changed, 232 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 2161bf01ef8b..67ef057ae918 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -13,6 +13,7 @@
> #include "intel_gt_clock_utils.h"
> #include "intel_gt_pm.h"
> #include "intel_gt_requests.h"
> +#include "intel_migrate.h"
> #include "intel_mocs.h"
> #include "intel_rc6.h"
> #include "intel_renderstate.h"
> @@ -626,6 +627,8 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_gt;
>
> + intel_migrate_init(>->migrate, gt);
> +
> goto out_fw;
> err_gt:
> __intel_gt_disable(gt);
> @@ -649,6 +652,7 @@ void intel_gt_driver_remove(struct intel_gt *gt)
> {
> __intel_gt_disable(gt);
>
> + intel_migrate_fini(>->migrate);
> intel_uc_driver_remove(>->uc);
>
> intel_engines_release(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index fecfacf551d5..7450935f2ca8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -24,6 +24,7 @@
> #include "intel_reset_types.h"
> #include "intel_rc6_types.h"
> #include "intel_rps_types.h"
> +#include "intel_migrate_types.h"
> #include "intel_wakeref.h"
>
> struct drm_i915_private;
> @@ -145,6 +146,8 @@ struct intel_gt {
>
> struct i915_vma *scratch;
>
> + struct intel_migrate migrate;
> +
> struct intel_gt_info {
> intel_engine_mask_t engine_mask;
> u8 num_engines;
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index fda05ce3eb9c..935b5f14ff21 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -418,10 +418,9 @@ intel_context_migrate_copy(struct intel_context *ce,
> struct i915_request *rq;
> int err;
>
> + GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
> *out = NULL;
>
> - /* GEM_BUG_ON(ce->vm != migrate_vm); */
> -
> GEM_BUG_ON(ce->ring->size < SZ_64K);
>
> do {
> @@ -536,6 +535,7 @@ intel_context_migrate_clear(struct intel_context *ce,
> struct i915_request *rq;
> int err;
>
> + GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm);
> *out = NULL;
>
> GEM_BUG_ON(ce->ring->size < SZ_64K);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_migrate.c b/drivers/gpu/drm/i915/gt/selftest_migrate.c
> index 159c8656e1b0..396c81364399 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_migrate.c
> @@ -3,6 +3,8 @@
> * Copyright © 2020 Intel Corporation
> */
>
> +#include <linux/sort.h>
> +
> #include "selftests/i915_random.h"
>
> static const unsigned int sizes[] = {
> @@ -441,14 +443,229 @@ int intel_migrate_live_selftests(struct drm_i915_private *i915)
> SUBTEST(thread_global_copy),
> SUBTEST(thread_global_clear),
> };
> - struct intel_migrate m;
> + struct intel_gt *gt = &i915->gt;
> +
> + if (!gt->migrate.context)
> + return 0;
> +
> + return i915_subtests(tests, >->migrate);
> +}
> +
> +static struct drm_i915_gem_object *
> +create_init_lmem_internal(struct intel_gt *gt, size_t sz, bool try_lmem)
> +{
> + struct drm_i915_gem_object *obj = NULL;
> int err;
>
> - if (intel_migrate_init(&m, &i915->gt))
> + if (try_lmem && HAS_LMEM(gt->i915))
Could drop the HAS_LMEM()
It's elsewhere in the driver normal to just do:
obj = create_lmem()
if (IS_ERR(obj))
obj = create_internal()
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> + obj = i915_gem_object_create_lmem(gt->i915, sz, 0);
> +
> + if (IS_ERR_OR_NULL(obj)) {
> + obj = i915_gem_object_create_internal(gt->i915, sz);
> + if (IS_ERR(obj))
> + return obj;
> + }
> +
> + i915_gem_object_trylock(obj);
> + err = i915_gem_object_pin_pages(obj);
> + if (err) {
> + i915_gem_object_unlock(obj);
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> + }
> +
> + return obj;
> +}
> +
> +static int wrap_ktime_compare(const void *A, const void *B)
> +{
> + const ktime_t *a = A, *b = B;
> +
> + return ktime_compare(*a, *b);
> +}
> +
> +static int __perf_clear_blt(struct intel_context *ce,
> + struct scatterlist *sg,
> + enum i915_cache_level cache_level,
> + bool is_lmem,
> + size_t sz)
> +{
> + ktime_t t[5];
> + int pass;
> + int err = 0;
> +
> + for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
> + struct i915_request *rq;
> + ktime_t t0, t1;
> +
> + t0 = ktime_get();
> +
> + err = intel_context_migrate_clear(ce, NULL, sg, cache_level,
> + is_lmem, 0, &rq);
> + if (rq) {
> + if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
> + err = -EIO;
> + i915_request_put(rq);
> + }
> + if (err)
> + break;
> +
> + t1 = ktime_get();
> + t[pass] = ktime_sub(t1, t0);
> + }
> + if (err)
> + return err;
> +
> + sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> + pr_info("%s: %zd KiB fill: %lld MiB/s\n",
> + ce->engine->name, sz >> 10,
> + div64_u64(mul_u32_u32(4 * sz,
> + 1000 * 1000 * 1000),
> + t[1] + 2 * t[2] + t[3]) >> 20);
> + return 0;
> +}
> +
> +static int perf_clear_blt(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + static const unsigned long sizes[] = {
> + SZ_4K,
> + SZ_64K,
> + SZ_2M,
> + SZ_64M
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(sizes); i++) {
> + struct drm_i915_gem_object *dst;
> + int err;
> +
> + dst = create_init_lmem_internal(gt, sizes[i], true);
> + if (IS_ERR(dst))
> + return PTR_ERR(dst);
> +
> + err = __perf_clear_blt(gt->migrate.context,
> + dst->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(dst),
> + sizes[i]);
> +
> + i915_gem_object_unlock(dst);
> + i915_gem_object_put(dst);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static int __perf_copy_blt(struct intel_context *ce,
> + struct scatterlist *src,
> + enum i915_cache_level src_cache_level,
> + bool src_is_lmem,
> + struct scatterlist *dst,
> + enum i915_cache_level dst_cache_level,
> + bool dst_is_lmem,
> + size_t sz)
> +{
> + ktime_t t[5];
> + int pass;
> + int err = 0;
> +
> + for (pass = 0; pass < ARRAY_SIZE(t); pass++) {
> + struct i915_request *rq;
> + ktime_t t0, t1;
> +
> + t0 = ktime_get();
> +
> + err = intel_context_migrate_copy(ce, NULL,
> + src, src_cache_level,
> + src_is_lmem,
> + dst, dst_cache_level,
> + dst_is_lmem,
> + &rq);
> + if (rq) {
> + if (i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
> + err = -EIO;
> + i915_request_put(rq);
> + }
> + if (err)
> + break;
> +
> + t1 = ktime_get();
> + t[pass] = ktime_sub(t1, t0);
> + }
> + if (err)
> + return err;
> +
> + sort(t, ARRAY_SIZE(t), sizeof(*t), wrap_ktime_compare, NULL);
> + pr_info("%s: %zd KiB copy: %lld MiB/s\n",
> + ce->engine->name, sz >> 10,
> + div64_u64(mul_u32_u32(4 * sz,
> + 1000 * 1000 * 1000),
> + t[1] + 2 * t[2] + t[3]) >> 20);
> + return 0;
> +}
> +
> +static int perf_copy_blt(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + static const unsigned long sizes[] = {
> + SZ_4K,
> + SZ_64K,
> + SZ_2M,
> + SZ_64M
> + };
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(sizes); i++) {
> + struct drm_i915_gem_object *src, *dst;
> + int err;
> +
> + src = create_init_lmem_internal(gt, sizes[i], true);
> + if (IS_ERR(src))
> + return PTR_ERR(src);
> +
> + dst = create_init_lmem_internal(gt, sizes[i], false);
> + if (IS_ERR(dst)) {
> + err = PTR_ERR(dst);
> + goto err_src;
> + }
> +
> + err = __perf_copy_blt(gt->migrate.context,
> + src->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(src),
> + dst->mm.pages->sgl,
> + I915_CACHE_NONE,
> + i915_gem_object_is_lmem(dst),
> + sizes[i]);
> +
> + i915_gem_object_unlock(dst);
> + i915_gem_object_put(dst);
> +err_src:
> + i915_gem_object_unlock(src);
> + i915_gem_object_put(src);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +int intel_migrate_perf_selftests(struct drm_i915_private *i915)
> +{
> + static const struct i915_subtest tests[] = {
> + SUBTEST(perf_clear_blt),
> + SUBTEST(perf_copy_blt),
> + };
> + struct intel_gt *gt = &i915->gt;
> +
> + if (intel_gt_is_wedged(gt))
> return 0;
>
> - err = i915_subtests(tests, &m);
> - intel_migrate_fini(&m);
> + if (!gt->migrate.context)
> + return 0;
>
> - return err;
> + return intel_gt_live_subtests(tests, gt);
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> index c2389f8a257d..5077dc3c3b8c 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
> @@ -17,5 +17,6 @@
> */
> selftest(engine_cs, intel_engine_cs_perf_selftests)
> selftest(request, i915_request_perf_selftests)
> +selftest(migrate, intel_migrate_perf_selftests)
> selftest(blt, i915_gem_object_blt_perf_selftests)
> selftest(region, intel_memory_region_perf_selftests)
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 13:08 ` Thomas Hellström
@ 2021-06-09 14:35 ` Thomas Hellström
-1 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 14:35 UTC (permalink / raw)
To: Matthew Auld, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 6/9/21 3:08 PM, Thomas Hellström wrote:
>
> On 6/9/21 2:20 PM, Matthew Auld wrote:
>> On 09/06/2021 13:16, Thomas Hellström wrote:
>>>
>>> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>>>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>>>> A couple of patches from Chris which implement pipelined migration
>>>>> and
>>>>> clears by atomically writing the PTEs in place before performing the
>>>>> actual blit.
>>>>>
>>>>> Some ww utilities mainly for the accompanying selftests added by
>>>>> Thomas,
>>>>> as well as modified the above patches for ww locking- and lmem
>>>>> support.
>>>>>
>>>>> The actual hook up to the i915 ttm backend is being worked on and not
>>>>> included yet, so this is considered to be an early review
>>>>> opportunity.
>>>>>
>>>>> v2:
>>>>> - A couple of minor style fixes pointed out by Matthew Auld
>>>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>>>> ls CI warning / failure.
>>>> Just to check my understanding of the plan: These are the new windowed
>>>> clear/blt functions which we plan to use everywhere, because less
>>>> nasty
>>>> locking implications? And the clear/blt we currently have in
>>>> upstream will
>>>> be replaced?
>>>
>>> Yes. These are for LMEM clearing and migration. It looks to me like
>>> the other ones we have in upstream are actually unused except for
>>> selftests. We're actually using CPU clearing for now.
>>>
>>>>
>>>> If so would be nice if this patch set includes that replacement
>>>> work (I
>>>> think right now all we have is the clear for lmem), including
>>>> updating of
>>>> selftests and stuff like that. Just to avoid having two ways to do the
>>>> same thing in the driver.
>>>
>>> OK, I'll have a look at stripping the existing code. If we need it
>>> moving forward, we can always re-add.
>>
>> Some low hanging fruit would be all the client_blt stuff which can
>> for sure be deleted now.
>
> What has the client_blt stuff been used for?
>
> In any case, I need 25 commits for commit access to be granted.
>
> /Thomas
>
>
Series on trybot now. It's the dg1 live memory_region selftest that
changes sligthly to use the new migration fill blt.
/Thomas
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 14:35 ` Thomas Hellström
0 siblings, 0 replies; 50+ messages in thread
From: Thomas Hellström @ 2021-06-09 14:35 UTC (permalink / raw)
To: Matthew Auld, Daniel Vetter; +Cc: intel-gfx, dri-devel
On 6/9/21 3:08 PM, Thomas Hellström wrote:
>
> On 6/9/21 2:20 PM, Matthew Auld wrote:
>> On 09/06/2021 13:16, Thomas Hellström wrote:
>>>
>>> On 6/9/21 1:48 PM, Daniel Vetter wrote:
>>>> On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
>>>>> A couple of patches from Chris which implement pipelined migration
>>>>> and
>>>>> clears by atomically writing the PTEs in place before performing the
>>>>> actual blit.
>>>>>
>>>>> Some ww utilities mainly for the accompanying selftests added by
>>>>> Thomas,
>>>>> as well as modified the above patches for ww locking- and lmem
>>>>> support.
>>>>>
>>>>> The actual hook up to the i915 ttm backend is being worked on and not
>>>>> included yet, so this is considered to be an early review
>>>>> opportunity.
>>>>>
>>>>> v2:
>>>>> - A couple of minor style fixes pointed out by Matthew Auld
>>>>> - Export and use intel_engine_destroy_pinned_context() to address a
>>>>> ls CI warning / failure.
>>>> Just to check my understanding of the plan: These are the new windowed
>>>> clear/blt functions which we plan to use everywhere, because less
>>>> nasty
>>>> locking implications? And the clear/blt we currently have in
>>>> upstream will
>>>> be replaced?
>>>
>>> Yes. These are for LMEM clearing and migration. It looks to me like
>>> the other ones we have in upstream are actually unused except for
>>> selftests. We're actually using CPU clearing for now.
>>>
>>>>
>>>> If so would be nice if this patch set includes that replacement
>>>> work (I
>>>> think right now all we have is the clear for lmem), including
>>>> updating of
>>>> selftests and stuff like that. Just to avoid having two ways to do the
>>>> same thing in the driver.
>>>
>>> OK, I'll have a look at stripping the existing code. If we need it
>>> moving forward, we can always re-add.
>>
>> Some low hanging fruit would be all the client_blt stuff which can
>> for sure be deleted now.
>
> What has the client_blt stuff been used for?
>
> In any case, I need 25 commits for commit access to be granted.
>
> /Thomas
>
>
Series on trybot now. It's the dg1 live memory_region selftest that
changes sligthly to use the new migration fill blt.
/Thomas
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
2021-06-09 14:35 ` Thomas Hellström
@ 2021-06-09 14:54 ` Daniel Vetter
-1 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2021-06-09 14:54 UTC (permalink / raw)
To: Thomas Hellström; +Cc: dri-devel, intel-gfx, Matthew Auld
On Wed, Jun 09, 2021 at 04:35:57PM +0200, Thomas Hellström wrote:
>
> On 6/9/21 3:08 PM, Thomas Hellström wrote:
> >
> > On 6/9/21 2:20 PM, Matthew Auld wrote:
> > > On 09/06/2021 13:16, Thomas Hellström wrote:
> > > >
> > > > On 6/9/21 1:48 PM, Daniel Vetter wrote:
> > > > > On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
> > > > > > A couple of patches from Chris which implement pipelined
> > > > > > migration and
> > > > > > clears by atomically writing the PTEs in place before performing the
> > > > > > actual blit.
> > > > > >
> > > > > > Some ww utilities mainly for the accompanying selftests
> > > > > > added by Thomas,
> > > > > > as well as modified the above patches for ww locking-
> > > > > > and lmem support.
> > > > > >
> > > > > > The actual hook up to the i915 ttm backend is being worked on and not
> > > > > > included yet, so this is considered to be an early
> > > > > > review opportunity.
> > > > > >
> > > > > > v2:
> > > > > > - A couple of minor style fixes pointed out by Matthew Auld
> > > > > > - Export and use intel_engine_destroy_pinned_context() to address a
> > > > > > ls CI warning / failure.
> > > > > Just to check my understanding of the plan: These are the new windowed
> > > > > clear/blt functions which we plan to use everywhere, because
> > > > > less nasty
> > > > > locking implications? And the clear/blt we currently have in
> > > > > upstream will
> > > > > be replaced?
> > > >
> > > > Yes. These are for LMEM clearing and migration. It looks to me
> > > > like the other ones we have in upstream are actually unused
> > > > except for selftests. We're actually using CPU clearing for now.
> > > >
> > > > >
> > > > > If so would be nice if this patch set includes that
> > > > > replacement work (I
> > > > > think right now all we have is the clear for lmem),
> > > > > including updating of
> > > > > selftests and stuff like that. Just to avoid having two ways to do the
> > > > > same thing in the driver.
> > > >
> > > > OK, I'll have a look at stripping the existing code. If we need
> > > > it moving forward, we can always re-add.
> > >
> > > Some low hanging fruit would be all the client_blt stuff which can
> > > for sure be deleted now.
> >
> > What has the client_blt stuff been used for?
> >
> > In any case, I need 25 commits for commit access to be granted.
> >
> > /Thomas
> >
> >
> Series on trybot now. It's the dg1 live memory_region selftest that changes
> sligthly to use the new migration fill blt.
Thanks a lot for taking care of this!
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 50+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration
@ 2021-06-09 14:54 ` Daniel Vetter
0 siblings, 0 replies; 50+ messages in thread
From: Daniel Vetter @ 2021-06-09 14:54 UTC (permalink / raw)
To: Thomas Hellström; +Cc: dri-devel, intel-gfx, Matthew Auld
On Wed, Jun 09, 2021 at 04:35:57PM +0200, Thomas Hellström wrote:
>
> On 6/9/21 3:08 PM, Thomas Hellström wrote:
> >
> > On 6/9/21 2:20 PM, Matthew Auld wrote:
> > > On 09/06/2021 13:16, Thomas Hellström wrote:
> > > >
> > > > On 6/9/21 1:48 PM, Daniel Vetter wrote:
> > > > > On Wed, Jun 09, 2021 at 08:34:27AM +0200, Thomas Hellström wrote:
> > > > > > A couple of patches from Chris which implement pipelined
> > > > > > migration and
> > > > > > clears by atomically writing the PTEs in place before performing the
> > > > > > actual blit.
> > > > > >
> > > > > > Some ww utilities mainly for the accompanying selftests
> > > > > > added by Thomas,
> > > > > > as well as modified the above patches for ww locking-
> > > > > > and lmem support.
> > > > > >
> > > > > > The actual hook up to the i915 ttm backend is being worked on and not
> > > > > > included yet, so this is considered to be an early
> > > > > > review opportunity.
> > > > > >
> > > > > > v2:
> > > > > > - A couple of minor style fixes pointed out by Matthew Auld
> > > > > > - Export and use intel_engine_destroy_pinned_context() to address a
> > > > > > ls CI warning / failure.
> > > > > Just to check my understanding of the plan: These are the new windowed
> > > > > clear/blt functions which we plan to use everywhere, because
> > > > > less nasty
> > > > > locking implications? And the clear/blt we currently have in
> > > > > upstream will
> > > > > be replaced?
> > > >
> > > > Yes. These are for LMEM clearing and migration. It looks to me
> > > > like the other ones we have in upstream are actually unused
> > > > except for selftests. We're actually using CPU clearing for now.
> > > >
> > > > >
> > > > > If so would be nice if this patch set includes that
> > > > > replacement work (I
> > > > > think right now all we have is the clear for lmem),
> > > > > including updating of
> > > > > selftests and stuff like that. Just to avoid having two ways to do the
> > > > > same thing in the driver.
> > > >
> > > > OK, I'll have a look at stripping the existing code. If we need
> > > > it moving forward, we can always re-add.
> > >
> > > Some low hanging fruit would be all the client_blt stuff which can
> > > for sure be deleted now.
> >
> > What has the client_blt stuff been used for?
> >
> > In any case, I need 25 commits for commit access to be granted.
> >
> > /Thomas
> >
> >
> Series on trybot now. It's the dg1 live memory_region selftest that changes
> sligthly to use the new migration fill blt.
Thanks a lot for taking care of this!
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 50+ messages in thread
end of thread, other threads:[~2021-06-09 14:54 UTC | newest]
Thread overview: 50+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-09 6:34 [PATCH v2 0/9] Prereqs for TTM accelerated migration Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 6:34 ` [PATCH v2 1/9] drm/i915: Reference objects on the ww object list Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 6:34 ` [PATCH v2 2/9] drm/i915: Break out dma_resv ww locking utilities to separate files Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 6:34 ` [PATCH v2 3/9] drm/i915: Introduce a ww transaction helper Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 6:34 ` [PATCH v2 4/9] drm/i915/gt: Add an insert_entry for gen8_ppgtt Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 7:44 ` Matthew Auld
2021-06-09 7:44 ` [Intel-gfx] " Matthew Auld
2021-06-09 6:34 ` [PATCH v2 5/9] drm/i915/gt: Add a routine to iterate over the pagetables of a GTT Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 7:48 ` Matthew Auld
2021-06-09 7:48 ` [Intel-gfx] " Matthew Auld
2021-06-09 6:34 ` [PATCH v2 6/9] drm/i915/gt: Export the pinned context constructor and destructor Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 8:00 ` Matthew Auld
2021-06-09 8:00 ` [Intel-gfx] " Matthew Auld
2021-06-09 6:34 ` [PATCH v2 7/9] drm/i915/gt: Pipelined page migration Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 12:14 ` Matthew Auld
2021-06-09 12:14 ` [Intel-gfx] " Matthew Auld
2021-06-09 12:48 ` Matthew Auld
2021-06-09 12:48 ` [Intel-gfx] " Matthew Auld
2021-06-09 6:34 ` [PATCH v2 8/9] drm/i915/gt: Pipelined clear Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 13:42 ` Matthew Auld
2021-06-09 13:42 ` [Intel-gfx] " Matthew Auld
2021-06-09 6:34 ` [PATCH v2 9/9] drm/i915/gt: Setup a default migration context on the GT Thomas Hellström
2021-06-09 6:34 ` [Intel-gfx] " Thomas Hellström
2021-06-09 14:17 ` Matthew Auld
2021-06-09 14:17 ` [Intel-gfx] " Matthew Auld
2021-06-09 7:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Prereqs for TTM accelerated migration (rev2) Patchwork
2021-06-09 8:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-09 8:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2021-06-09 9:56 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2021-06-09 11:48 ` [Intel-gfx] [PATCH v2 0/9] Prereqs for TTM accelerated migration Daniel Vetter
2021-06-09 11:48 ` Daniel Vetter
2021-06-09 12:16 ` Thomas Hellström
2021-06-09 12:16 ` Thomas Hellström
2021-06-09 12:20 ` Matthew Auld
2021-06-09 12:20 ` Matthew Auld
2021-06-09 13:08 ` Thomas Hellström
2021-06-09 13:08 ` Thomas Hellström
2021-06-09 14:35 ` Thomas Hellström
2021-06-09 14:35 ` Thomas Hellström
2021-06-09 14:54 ` Daniel Vetter
2021-06-09 14:54 ` Daniel Vetter
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