From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org
Subject: [PATCH v6 2/5] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
Date: Wed, 09 Jun 2021 09:01:41 -0700 [thread overview]
Message-ID: <162325450105.2293126.17046356425194082921.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <162325448982.2293126.16916114289970424561.stgit@dwillia2-desk3.amr.corp.intel.com>
CONFIG_CXL_BUS is default 'n' as expected for new functionality. When
that is enabled do not make the end user hunt for all the expected
sub-options to enable. For example CONFIG_CXL_BUS without CONFIG_CXL_MEM
is an odd/expert configuration, so is CONFIG_CXL_MEM without
CONFIG_CXL_ACPI (on ACPI capable platforms). Default CONFIG_CXL_MEM and
CONFIG_CXL_ACPI to CONFIG_CXL_BUS.
Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index d2573f6aef91..1a44b173dcbc 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -15,6 +15,7 @@ if CXL_BUS
config CXL_MEM
tristate "CXL.mem: Memory Devices"
+ default CXL_BUS
help
The CXL.mem protocol allows a device to act as a provider of
"System RAM" and/or "Persistent Memory" that is fully coherent
@@ -49,6 +50,7 @@ config CXL_MEM_RAW_COMMANDS
config CXL_ACPI
tristate "CXL ACPI: Platform Support"
depends on ACPI
+ default CXL_BUS
help
Enable support for host managed device memory (HDM) resources
published by a platform's ACPI CXL memory layout description. See
next prev parent reply other threads:[~2021-06-09 16:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-09 16:01 [PATCH v6 0/5] CXL port and decoder enumeration Dan Williams
2021-06-09 16:01 ` [PATCH v6 1/5] cxl/acpi: Introduce the root of a cxl_port topology Dan Williams
2021-06-09 16:01 ` Dan Williams [this message]
2021-06-09 16:01 ` [PATCH v6 3/5] cxl/acpi: Add downstream port data to cxl_port instances Dan Williams
2021-06-10 0:34 ` Alison Schofield
2021-06-10 11:27 ` Jonathan Cameron
2021-06-09 16:01 ` [PATCH v6 4/5] cxl/acpi: Enumerate host bridge root ports Dan Williams
2021-06-09 16:01 ` [PATCH v6 5/5] cxl/acpi: Introduce cxl_decoder objects Dan Williams
2021-06-09 16:43 ` [PATCH v7 " Dan Williams
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