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From: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
To: adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org
Cc: asutoshd@codeaurora.org, stummala@codeaurora.org,
	vbadigan@codeaurora.org, rampraka@codeaurora.org,
	sayalil@codeaurora.org, sartgarg@codeaurora.org,
	rnayak@codeaurora.org, saiprakash.ranjan@codeaurora.org,
	sibis@codeaurora.org, okukatla@codeaurora.org, djakov@kernel.org,
	cang@codeaurora.org, pragalla@codeaurora.org,
	nitirawa@codeaurora.org, linux-mmc@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, agross@kernel.org,
	bjorn.andersson@linaro.org,
	Shaik Sajida Bhanu <sbhanu@codeaurora.org>
Subject: [PATCH V1] arm64: dts: qcom: sc7180: Added xo clock for eMMC and Sd card
Date: Thu, 10 Jun 2021 12:41:47 +0530	[thread overview]
Message-ID: <1623309107-27833-1-git-send-email-sbhanu@codeaurora.org> (raw)

Added xo clock for eMMC and Sd card.

Signed-off-by: Shaik Sajida Bhanu <sbhanu@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 295844e..5bb6bd4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -701,8 +701,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-					<&gcc GCC_SDCC1_AHB_CLK>;
-			clock-names = "core", "iface";
+					<&gcc GCC_SDCC1_AHB_CLK>,
+					<&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface","xo";
 			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -2666,8 +2667,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-					<&gcc GCC_SDCC2_AHB_CLK>;
-			clock-names = "core", "iface";
+					<&gcc GCC_SDCC2_AHB_CLK>,
+					<&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface", "xo";
 
 			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


             reply	other threads:[~2021-06-10  7:12 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-10  7:11 Shaik Sajida Bhanu [this message]
2021-06-10  7:54 ` [PATCH V1] arm64: dts: qcom: sc7180: Added xo clock for eMMC and Sd card Konrad Dybcio
2021-06-11  3:29   ` Bjorn Andersson
2021-06-14 11:44   ` sbhanu
2021-06-14 11:49     ` Konrad Dybcio
2021-06-11  4:30 ` Bjorn Andersson
2021-06-14 11:55   ` sbhanu
2021-06-14 16:30     ` Bjorn Andersson
2021-06-15 10:00       ` sbhanu

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