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* [Intel-gfx] [CI 0/4] Pipe DMC Support
@ 2021-06-11 19:43 Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
                   ` (7 more replies)
  0 siblings, 8 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2021-06-11 19:43 UTC (permalink / raw)
  To: intel-gfx

One change from previous verison is a fix of SKL
regression. Corner cases for stepping-substepping
combination was missing from fw_info_matches_stepping()
helper. Luckily SKL was the only platform in CI that came
under this category and DMC refused to load.

v2: SKL fix tested on SKL.

v3: Minor changes in Pipe DMC plugging patch
as suggested by Lucas
 
v4: Remove the sanity check for MMIO that no longer
apply to newer platforms.(Anusha)

Anusha Srivatsa (4):
  drm/i915/dmc: Introduce DMC_FW_MAIN
  drm/i915/xelpd: Pipe A DMC plugging
  drm/i915/adl_p: Pipe B DMC Support
  drm/i915/adl_p: Load DMC

 .../drm/i915/display/intel_display_debugfs.c  |   6 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 165 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |  23 ++-
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 123 insertions(+), 78 deletions(-)

-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
@ 2021-06-11 19:43 ` Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
                   ` (6 subsequent siblings)
  7 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2021-06-11 19:43 UTC (permalink / raw)
  To: intel-gfx

This is a prep patch for Pipe DMC plugging.

Add dmc_info struct in intel_dmc to have all common fields
shared between all DMC's in the package.
Add DMC_FW_MAIN(dmc_id 0) to refer to the blob.

v2: Remove dmc_offset and start_mmioaddr from dmc_info struct (Jose)

Cc: Souza, Jose <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 38 +++++++++++++-----------
 drivers/gpu/drm/i915/display/intel_dmc.h | 18 +++++++----
 2 files changed, 33 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 97308da28059..269a57d936ab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -239,7 +239,7 @@ struct stepping_info {
 
 bool intel_dmc_has_payload(struct drm_i915_private *i915)
 {
-	return i915->dmc.dmc_payload;
+	return i915->dmc.dmc_info[DMC_FW_MAIN].payload;
 }
 
 static const struct stepping_info skl_stepping_info[] = {
@@ -316,7 +316,8 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
  */
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
-	u32 *payload = dev_priv->dmc.dmc_payload;
+	struct intel_dmc *dmc = &dev_priv->dmc;
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
 	u32 i, fw_size;
 
 	if (!HAS_DMC(dev_priv)) {
@@ -325,26 +326,26 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
-	if (!intel_dmc_has_payload(dev_priv)) {
+	if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
 		drm_err(&dev_priv->drm,
 			"Tried to program CSR with empty payload\n");
 		return;
 	}
 
-	fw_size = dev_priv->dmc.dmc_fw_size;
+	fw_size = dmc_info->dmc_fw_size;
 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 
 	preempt_disable();
 
 	for (i = 0; i < fw_size; i++)
 		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
-				      payload[i]);
+				      dmc_info->payload[i]);
 
 	preempt_enable();
 
-	for (i = 0; i < dev_priv->dmc.mmio_count; i++) {
-		intel_de_write(dev_priv, dev_priv->dmc.mmioaddr[i],
-			       dev_priv->dmc.mmiodata[i]);
+	for (i = 0; i < dmc_info->mmio_count; i++) {
+		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
+			       dmc_info->mmiodata[i]);
 	}
 
 	dev_priv->dmc.dc_state = 0;
@@ -401,13 +402,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       size_t rem_size)
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 	const u32 *mmioaddr, *mmiodata;
 	u32 mmio_count, mmio_count_max;
 	u8 *payload;
 
-	BUILD_BUG_ON(ARRAY_SIZE(dmc->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
-		     ARRAY_SIZE(dmc->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
+	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
+		     ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
 
 	/*
 	 * Check if we can access common fields, we will checkc again below
@@ -469,10 +471,10 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 				mmioaddr[i]);
 			return 0;
 		}
-		dmc->mmioaddr[i] = _MMIO(mmioaddr[i]);
-		dmc->mmiodata[i] = mmiodata[i];
+		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
+		dmc_info->mmiodata[i] = mmiodata[i];
 	}
-	dmc->mmio_count = mmio_count;
+	dmc_info->mmio_count = mmio_count;
 
 	rem_size -= header_len_bytes;
 
@@ -485,14 +487,14 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size);
 		return 0;
 	}
-	dmc->dmc_fw_size = dmc_header->fw_size;
+	dmc_info->dmc_fw_size = dmc_header->fw_size;
 
-	dmc->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
-	if (!dmc->dmc_payload)
+	dmc_info->payload = kmalloc(payload_size, GFP_KERNEL);
+	if (!dmc_info->payload)
 		return 0;
 
 	payload = (u8 *)(dmc_header) + header_len_bytes;
-	memcpy(dmc->dmc_payload, payload, payload_size);
+	memcpy(dmc_info->payload, payload, payload_size);
 
 	return header_len_bytes + payload_size;
 
@@ -827,5 +829,5 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
 	intel_dmc_ucode_suspend(dev_priv);
 	drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
 
-	kfree(dev_priv->dmc.dmc_payload);
+	kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 4c22f567b61b..b872f3a4fd03 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -16,17 +16,25 @@ struct drm_i915_private;
 #define DMC_VERSION_MAJOR(version)	((version) >> 16)
 #define DMC_VERSION_MINOR(version)	((version) & 0xffff)
 
+enum {
+	DMC_FW_MAIN = 0,
+	DMC_FW_MAX
+};
+
 struct intel_dmc {
 	struct work_struct work;
 	const char *fw_path;
 	u32 required_version;
 	u32 max_fw_size; /* bytes */
-	u32 *dmc_payload;
-	u32 dmc_fw_size; /* dwords */
 	u32 version;
-	u32 mmio_count;
-	i915_reg_t mmioaddr[20];
-	u32 mmiodata[20];
+	struct dmc_fw_info {
+		u32 mmio_count;
+		i915_reg_t mmioaddr[20];
+		u32 mmiodata[20];
+		u32 dmc_fw_size; /*dwords */
+		u32 *payload;
+	} dmc_info[DMC_FW_MAX];
+
 	u32 dc_state;
 	u32 target_dc_state;
 	u32 allowed_dc_mask;
-- 
2.25.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
@ 2021-06-11 19:43 ` Anusha Srivatsa
  2021-06-12  4:39   ` Lucas De Marchi
  2021-06-11 19:43 ` [Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
                   ` (5 subsequent siblings)
  7 siblings, 1 reply; 11+ messages in thread
From: Anusha Srivatsa @ 2021-06-11 19:43 UTC (permalink / raw)
  To: intel-gfx

This patch adds Pipe A plumbing to the already
existing parsing and loading functions which is
taken care of in the prep patches. Adding MAX_DMC_FW
to keep track for both Main and Pipe A DMC while loading
the respective blobs.

Also adding present field in dmc_info.
s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
fw_info_matches_stepping() helper. CSR_PROGRAM() should now
take the starting address of the particular blob (Main or Pipe)
and not hardcode it.

v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.

v3: Add a missing corner cases of stepping-substepping combination in
fw_info_matches_stepping() helper.

v4: Add macro for start_mmioaddr for V1 package. Simplify code
in dmc_set_fw_offset (Lucas)

Cc: Souza, Jose <jose.souza@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 .../drm/i915/display/intel_display_debugfs.c  |   4 +-
 .../drm/i915/display/intel_display_power.c    |   5 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 131 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_dmc.h      |   4 +
 drivers/gpu/drm/i915/i915_reg.h               |   2 +-
 5 files changed, 85 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 88bb05d5c483..2a1c39a0e56e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 	seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
 	seq_printf(m, "path: %s\n", dmc->fw_path);
+	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
+	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
 
 	if (!intel_dmc_has_payload(dev_priv))
 		goto out;
@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 
 out:
 	seq_printf(m, "program base: 0x%08x\n",
-		   intel_de_read(dev_priv, DMC_PROGRAM(0)));
+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
 	seq_printf(m, "ssp base: 0x%08x\n",
 		   intel_de_read(dev_priv, DMC_SSP_BASE));
 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4298ae684d7d..285380079aab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
 {
 	drm_WARN_ONCE(&dev_priv->drm,
-		      !intel_de_read(dev_priv, DMC_PROGRAM(0)),
-		      "DMC program storage start is NULL\n");
+		      !intel_de_read(dev_priv,
+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+				     "DMC program storage start is NULL\n");
 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
 		      "DMC SSP Base Not fine\n");
 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 269a57d936ab..18e0d225a478 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES	32
 #define DMC_V1_MAX_MMIO_COUNT		8
 #define DMC_V3_MAX_MMIO_COUNT		20
+#define DMC_V1_MMIO_START_RANGE		0x80000
 
 struct intel_css_header {
 	/* 0x09 for DMC */
@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 {
 	struct intel_dmc *dmc = &dev_priv->dmc;
-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
-	u32 i, fw_size;
+	u32 id, i;
 
 	if (!HAS_DMC(dev_priv)) {
 		drm_err(&dev_priv->drm,
@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
-	fw_size = dmc_info->dmc_fw_size;
 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
 
 	preempt_disable();
 
-	for (i = 0; i < fw_size; i++)
-		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
-				      dmc_info->payload[i]);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
+			intel_uncore_write_fw(&dev_priv->uncore,
+					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
+					      dmc->dmc_info[id].payload[i]);
+		}
+	}
 
 	preempt_enable();
 
-	for (i = 0; i < dmc_info->mmio_count; i++) {
-		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
-			       dmc_info->mmiodata[i]);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
+			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
+				       dmc->dmc_info[id].mmiodata[i]);
+		}
 	}
 
 	dev_priv->dmc.dc_state = 0;
@@ -353,59 +358,68 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
 	gen9_set_dc_state_debugmask(dev_priv);
 }
 
+static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
+				     const struct stepping_info *si)
+{
+	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
+	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
+	    /*
+	     * If we don't find a more specific one from above two checks, we
+	     * then check for the generic one to be sure to work even with
+	     * "broken firmware"
+	     */
+	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
+	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
+		return true;
+
+	return false;
+}
+
 /*
  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
  * already sanitized.
  */
-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
+static void dmc_set_fw_offset(struct intel_dmc *dmc,
+			      const struct intel_fw_info *fw_info,
 			      unsigned int num_entries,
 			      const struct stepping_info *si,
 			      u8 package_ver)
 {
-	u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
-	unsigned int i;
+	unsigned int i, id;
+
+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
 
 	for (i = 0; i < num_entries; i++) {
-		if (package_ver > 1 && fw_info[i].dmc_id != 0)
-			continue;
+		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
 
-		if (fw_info[i].substepping == '*' &&
-		    si->stepping == fw_info[i].stepping) {
-			dmc_offset = fw_info[i].offset;
-			break;
+		if (id >= DMC_FW_MAX) {
+			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
+			continue;
 		}
 
-		if (si->stepping == fw_info[i].stepping &&
-		    si->substepping == fw_info[i].substepping) {
-			dmc_offset = fw_info[i].offset;
-			break;
-		}
+		/* More specific versions come first, so we don't even have to
+		 * check for the stepping since we already found a previous FW
+		 * for this id.
+		 */
+		if (dmc->dmc_info[id].present)
+			continue;
 
-		if (fw_info[i].stepping == '*' &&
-		    fw_info[i].substepping == '*') {
-			/*
-			 * In theory we should stop the search as generic
-			 * entries should always come after the more specific
-			 * ones, but let's continue to make sure to work even
-			 * with "broken" firmwares. If we don't find a more
-			 * specific one, then we use this entry
-			 */
-			dmc_offset = fw_info[i].offset;
+		if (fw_info_matches_stepping(&fw_info[i], si)) {
+			dmc->dmc_info[id].present = true;
+			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
 		}
 	}
-
-	return dmc_offset;
 }
 
 static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 			       const struct intel_dmc_header_base *dmc_header,
-			       size_t rem_size)
+			       size_t rem_size, u8 dmc_id)
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
 	const u32 *mmioaddr, *mmiodata;
-	u32 mmio_count, mmio_count_max;
+	u32 mmio_count, mmio_count_max, start_mmioaddr;
 	u8 *payload;
 
 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
@@ -432,6 +446,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
 		/* header_len is in dwords */
 		header_len_bytes = dmc_header->header_len * 4;
+		start_mmioaddr = v3->start_mmioaddr;
 		dmc_header_size = sizeof(*v3);
 	} else if (dmc_header->header_ver == 1) {
 		const struct intel_dmc_header_v1 *v1 =
@@ -445,6 +460,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 		mmio_count = v1->mmio_count;
 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
 		header_len_bytes = dmc_header->header_len;
+		start_mmioaddr = DMC_V1_MMIO_START_RANGE;
 		dmc_header_size = sizeof(*v1);
 	} else {
 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
@@ -465,16 +481,11 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
 	}
 
 	for (i = 0; i < mmio_count; i++) {
-		if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
-		    mmioaddr[i] > DMC_MMIO_END_RANGE) {
-			drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
-				mmioaddr[i]);
-			return 0;
-		}
 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
 		dmc_info->mmiodata[i] = mmiodata[i];
 	}
 	dmc_info->mmio_count = mmio_count;
+	dmc_info->start_mmioaddr = start_mmioaddr;
 
 	rem_size -= header_len_bytes;
 
@@ -511,7 +522,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
 {
 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
 	u32 package_size = sizeof(struct intel_package_header);
-	u32 num_entries, max_entries, dmc_offset;
+	u32 num_entries, max_entries;
 	const struct intel_fw_info *fw_info;
 
 	if (rem_size < package_size)
@@ -547,16 +558,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
 
 	fw_info = (const struct intel_fw_info *)
 		((u8 *)package_header + sizeof(*package_header));
-	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
-					package_header->header_ver);
-	if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
-		drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
-			si->stepping);
-		return 0;
-	}
+	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
+			  package_header->header_ver);
 
 	/* dmc_offset is in dwords */
-	return package_size + dmc_offset * 4;
+	return package_size;
 
 error_truncated:
 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -608,7 +614,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 	struct intel_dmc *dmc = &dev_priv->dmc;
 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 	u32 readcount = 0;
-	u32 r;
+	u32 r, offset;
+	int id;
 
 	if (!fw)
 		return;
@@ -629,9 +636,19 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
 
 	readcount += r;
 
-	/* Extract dmc_header information */
-	dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
-	parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
+	for (id = 0; id < DMC_FW_MAX; id++) {
+		if (!dev_priv->dmc.dmc_info[id].present)
+			continue;
+
+		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
+		if (fw->size - offset < 0) {
+			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
+			continue;
+		}
+
+		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
+		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
+	}
 }
 
 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index b872f3a4fd03..007a284b0ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -18,6 +18,7 @@ struct drm_i915_private;
 
 enum {
 	DMC_FW_MAIN = 0,
+	DMC_FW_PIPEA,
 	DMC_FW_MAX
 };
 
@@ -31,8 +32,11 @@ struct intel_dmc {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
 		u32 mmiodata[20];
+		u32 dmc_offset;
+		u32 start_mmioaddr;
 		u32 dmc_fw_size; /*dwords */
 		u32 *payload;
+		bool present;
 	} dmc_info[DMC_FW_MAX];
 
 	u32 dc_state;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e915ec034c98..fb5e8e12ff49 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7751,7 +7751,7 @@ enum {
 #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
 
 /* DMC */
-#define DMC_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
 #define DMC_HTP_ADDR_SKL	0x00500034
 #define DMC_SSP_BASE		_MMIO(0x8F074)
-- 
2.25.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
@ 2021-06-11 19:43 ` Anusha Srivatsa
  2021-06-11 19:43 ` [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC Anusha Srivatsa
                   ` (4 subsequent siblings)
  7 siblings, 0 replies; 11+ messages in thread
From: Anusha Srivatsa @ 2021-06-11 19:43 UTC (permalink / raw)
  To: intel-gfx

ADLP requires us to load both Pipe A and Pipe B.
Plug Pipe B loading support.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 ++
 drivers/gpu/drm/i915/display/intel_dmc.h             | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 2a1c39a0e56e..db38891a9ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -546,6 +546,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "path: %s\n", dmc->fw_path);
 	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
 	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
+	seq_printf(m, "Pipe B fw support: %s\n", yesno(IS_ALDERLAKE_P(dev_priv)));
+	seq_printf(m, "Pipe B fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEB].payload));
 
 	if (!intel_dmc_has_payload(dev_priv))
 		goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 007a284b0ef0..c3c00ff03869 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -19,6 +19,7 @@ struct drm_i915_private;
 enum {
 	DMC_FW_MAIN = 0,
 	DMC_FW_PIPEA,
+	DMC_FW_PIPEB,
 	DMC_FW_MAX
 };
 
-- 
2.25.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
                   ` (2 preceding siblings ...)
  2021-06-11 19:43 ` [Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
@ 2021-06-11 19:43 ` Anusha Srivatsa
  2021-06-12  4:40   ` Lucas De Marchi
  2021-06-11 20:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev7) Patchwork
                   ` (3 subsequent siblings)
  7 siblings, 1 reply; 11+ messages in thread
From: Anusha Srivatsa @ 2021-06-11 19:43 UTC (permalink / raw)
  To: intel-gfx

Load DMC v2.10 on ADLP. The release notes mention that
this version enables few power savings features.

v2: Add DMC_PATH() for ADLP (Lucas)

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 18e0d225a478..f8789d4543bf 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -45,6 +45,10 @@
 
 #define GEN12_DMC_MAX_FW_SIZE		ICL_DMC_MAX_FW_SIZE
 
+#define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 10)
+#define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 10)
+MODULE_FIRMWARE(ADLP_DMC_PATH);
+
 #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
 #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
 MODULE_FIRMWARE(ADLS_DMC_PATH);
@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_dmc_runtime_pm_get(dev_priv);
 
-	if (IS_ALDERLAKE_S(dev_priv)) {
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		dmc->fw_path = ADLP_DMC_PATH;
+		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
+		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
+	} else if (IS_ALDERLAKE_S(dev_priv)) {
 		dmc->fw_path = ADLS_DMC_PATH;
 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
 		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
-- 
2.25.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev7)
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
                   ` (3 preceding siblings ...)
  2021-06-11 19:43 ` [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC Anusha Srivatsa
@ 2021-06-11 20:55 ` Patchwork
  2021-06-11 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-06-11 20:55 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

== Series Details ==

Series: Pipe DMC Support (rev7)
URL   : https://patchwork.freedesktop.org/series/90445/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
f4c89ab48cfd drm/i915/dmc: Introduce DMC_FW_MAIN
519b42fb4bf9 drm/i915/xelpd: Pipe A DMC plugging
-:48: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#48: FILE: drivers/gpu/drm/i915/display/intel_display_debugfs.c:587:
+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

-:63: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#63: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:965:
+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),

total: 0 errors, 2 warnings, 0 checks, 287 lines checked
82459c72a5a5 drm/i915/adl_p: Pipe B DMC Support
99f3d8c71c86 drm/i915/adl_p: Load DMC


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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Pipe DMC Support (rev7)
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
                   ` (4 preceding siblings ...)
  2021-06-11 20:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev7) Patchwork
@ 2021-06-11 20:56 ` Patchwork
  2021-06-11 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2021-06-11 23:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-06-11 20:56 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

== Series Details ==

Series: Pipe DMC Support (rev7)
URL   : https://patchwork.freedesktop.org/series/90445/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1893:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1893:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gem/i915_gem_ttm.c:564:38: warning: symbol 'i915_gem_ttm_obj_ops' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1396:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1207:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Pipe DMC Support (rev7)
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
                   ` (5 preceding siblings ...)
  2021-06-11 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-06-11 21:26 ` Patchwork
  2021-06-11 23:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
  7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-06-11 21:26 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 6424 bytes --]

== Series Details ==

Series: Pipe DMC Support (rev7)
URL   : https://patchwork.freedesktop.org/series/90445/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10213 -> Patchwork_20350
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/index.html

Known issues
------------

  Here are the changes found in Patchwork_20350 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0:
    - {fi-tgl-1115g4}:    [FAIL][1] ([i915#1888]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0.html

  * igt@i915_selftest@live@objects:
    - {fi-tgl-dsi}:       [DMESG-WARN][3] ([i915#2867]) -> [PASS][4] +10 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-tgl-dsi/igt@i915_selftest@live@objects.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-tgl-dsi/igt@i915_selftest@live@objects.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [FAIL][5] ([i915#3049]) -> [SKIP][6] ([fdo#109271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_selftest@live@execlists:
    - fi-icl-u2:          [INCOMPLETE][7] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][8] ([i915#3462])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-icl-u2/igt@i915_selftest@live@execlists.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-icl-u2/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - fi-skl-6600u:       [FAIL][9] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][10] ([i915#1436] / [i915#3363])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-skl-6600u/igt@runner@aborted.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-skl-6600u/igt@runner@aborted.html
    - fi-icl-u2:          [FAIL][11] ([i915#2782] / [i915#3363]) -> [FAIL][12] ([i915#2426] / [i915#2782] / [i915#3363])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-icl-u2/igt@runner@aborted.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-icl-u2/igt@runner@aborted.html
    - fi-kbl-soraka:      [FAIL][13] ([i915#1436] / [i915#3363]) -> [FAIL][14] ([i915#1436] / [i915#2426] / [i915#3363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-kbl-soraka/igt@runner@aborted.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-kbl-soraka/igt@runner@aborted.html
    - fi-kbl-7500u:       [FAIL][15] ([i915#1436] / [i915#3363]) -> [FAIL][16] ([i915#1436] / [i915#2426] / [i915#3363])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-kbl-7500u/igt@runner@aborted.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-kbl-7500u/igt@runner@aborted.html
    - fi-kbl-guc:         [FAIL][17] ([i915#1436] / [i915#3363]) -> [FAIL][18] ([i915#1436] / [i915#2426] / [i915#3363])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-kbl-guc/igt@runner@aborted.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-kbl-guc/igt@runner@aborted.html
    - fi-kbl-7567u:       [FAIL][19] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][20] ([i915#1436] / [i915#3363])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/fi-kbl-7567u/igt@runner@aborted.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/fi-kbl-7567u/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3049]: https://gitlab.freedesktop.org/drm/intel/issues/3049
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3542]: https://gitlab.freedesktop.org/drm/intel/issues/3542
  [i915#3544]: https://gitlab.freedesktop.org/drm/intel/issues/3544
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533


Participating hosts (42 -> 39)
------------------------------

  Additional (1): fi-rkl-11500t 
  Missing    (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 


Build changes
-------------

  * Linux: CI_DRM_10213 -> Patchwork_20350

  CI-20190529: 20190529
  CI_DRM_10213: b09945cfd4510dfc6d9a6a03ce22b66e7419484d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6104: f8f81bd3752f3126a47d9dbba2d0ab29f7c17a19 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20350: 99f3d8c71c86dbbb7b537e16df977a79d2e40757 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

99f3d8c71c86 drm/i915/adl_p: Load DMC
82459c72a5a5 drm/i915/adl_p: Pipe B DMC Support
519b42fb4bf9 drm/i915/xelpd: Pipe A DMC plugging
f4c89ab48cfd drm/i915/dmc: Introduce DMC_FW_MAIN

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/index.html

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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Pipe DMC Support (rev7)
  2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
                   ` (6 preceding siblings ...)
  2021-06-11 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-06-11 23:47 ` Patchwork
  7 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2021-06-11 23:47 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 30246 bytes --]

== Series Details ==

Series: Pipe DMC Support (rev7)
URL   : https://patchwork.freedesktop.org/series/90445/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10213_full -> Patchwork_20350_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20350_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20350_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20350_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb7/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk7/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk2/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  

### Piglit changes ###

#### Possible regressions ####

  * spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_backsecondarycolor-smooth-gl_secondarycolor (NEW):
    - {pig-icl-1065g7}:   NOTRUN -> [INCOMPLETE][5] +7 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/pig-icl-1065g7/spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_backsecondarycolor-smooth-gl_secondarycolor.html

  * spec@glsl-1.30@linker@interpolation-qualifiers@unused-default-gl_backsecondarycolor-unused-noperspective-gl_secondarycolor (NEW):
    - {pig-icl-1065g7}:   NOTRUN -> [CRASH][6] +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/pig-icl-1065g7/spec@glsl-1.30@linker@interpolation-qualifiers@unused-default-gl_backsecondarycolor-unused-noperspective-gl_secondarycolor.html

  * spec@glsl-1.50@execution@texelfetch@gs-texelfetch-usampler2darray (NEW):
    - pig-snb-2600:       NOTRUN -> [FAIL][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/pig-snb-2600/spec@glsl-1.50@execution@texelfetch@gs-texelfetch-usampler2darray.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10213_full and Patchwork_20350_full:

### New Piglit tests (11) ###

  * spec@glsl-1.30@linker@interpolation-qualifiers@default-gl_backsecondarycolor-flat-gl_frontsecondarycolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_backsecondarycolor-default-gl_secondarycolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_backsecondarycolor-smooth-gl_secondarycolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@flat-gl_backsecondarycolor-unused-gl_secondarycolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@noperspective-gl_backcolor-default-gl_frontcolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@noperspective-gl_backcolor-smooth-gl_frontcolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@unused-default-gl_backsecondarycolor-unused-noperspective-gl_secondarycolor:
    - Statuses : 1 crash(s)
    - Exec time: [0.46] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@unused-default-gl_backsecondarycolor-unused-smooth-gl_secondarycolor:
    - Statuses : 1 crash(s)
    - Exec time: [0.41] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@unused-flat-gl_backsecondarycolor-unused-default-gl_secondarycolor:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.30@linker@interpolation-qualifiers@unused-noperspective-gl_frontcolor-unused-smooth-gl_color:
    - Statuses : 1 incomplete(s)
    - Exec time: [0.0] s

  * spec@glsl-1.50@execution@texelfetch@gs-texelfetch-usampler2darray:
    - Statuses : 1 fail(s)
    - Exec time: [0.22] s

  

Known issues
------------

  Here are the changes found in Patchwork_20350_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@idempotent:
    - shard-snb:          NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#1099]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-snb2/igt@gem_ctx_persistence@idempotent.html

  * igt@gem_ctx_persistence@many-contexts:
    - shard-tglb:         [PASS][9] -> [FAIL][10] ([i915#2410])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-tglb6/igt@gem_ctx_persistence@many-contexts.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-tglb3/igt@gem_ctx_persistence@many-contexts.html

  * igt@gem_ctx_shared@q-in-order:
    - shard-snb:          NOTRUN -> [SKIP][11] ([fdo#109271]) +337 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-snb5/igt@gem_ctx_shared@q-in-order.html

  * igt@gem_eio@unwedge-stress:
    - shard-skl:          [PASS][12] -> [TIMEOUT][13] ([i915#2369] / [i915#3063])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl4/igt@gem_eio@unwedge-stress.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl4/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-glk:          [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk3/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][20] ([i915#2842]) +1 similar issue
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_reloc@basic-wide-active@bcs0:
    - shard-apl:          NOTRUN -> [FAIL][21] ([i915#2389]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl6/igt@gem_exec_reloc@basic-wide-active@bcs0.html

  * igt@gem_exec_whisper@basic-queues-priority:
    - shard-iclb:         [PASS][22] -> [INCOMPLETE][23] ([i915#1895])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb2/igt@gem_exec_whisper@basic-queues-priority.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#2190])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@big-copy:
    - shard-glk:          [PASS][25] -> [FAIL][26] ([i915#307])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk3/igt@gem_mmap_gtt@big-copy.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk9/igt@gem_mmap_gtt@big-copy.html

  * igt@gem_mmap_gtt@big-copy-odd:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([i915#307])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb5/igt@gem_mmap_gtt@big-copy-odd.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb7/igt@gem_mmap_gtt@big-copy-odd.html

  * igt@gem_mmap_offset@clear:
    - shard-iclb:         [PASS][29] -> [FAIL][30] ([i915#3160])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb1/igt@gem_mmap_offset@clear.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb4/igt@gem_mmap_offset@clear.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3323])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-apl:          NOTRUN -> [DMESG-WARN][32] ([i915#3002]) +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl8/igt@gem_userptr_blits@input-checking.html

  * igt@gen7_exec_parse@basic-allocation:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([fdo#109289])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@gen7_exec_parse@basic-allocation.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#112306])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-snb:          [PASS][35] -> [DMESG-WARN][36] ([i915#3389])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-snb5/igt@i915_module_load@reload-with-fault-injection.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          [PASS][37] -> [FAIL][38] ([i915#454])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl2/igt@i915_pm_dc@dc6-psr.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl3/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_selftest@live@execlists:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][39] ([i915#3462])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl3/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hangcheck:
    - shard-snb:          NOTRUN -> [INCOMPLETE][40] ([i915#2782])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-snb2/igt@i915_selftest@live@hangcheck.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][41] ([fdo#110725] / [fdo#111614])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +27 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_color_chamelium@pipe-a-ctm-limited-range:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
    - shard-kbl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl2/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-snb:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +17 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-snb5/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][46] ([i915#1319])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl3/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][47] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][48] -> [DMESG-WARN][49] ([i915#180]) +7 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_cursor_edge_walk@pipe-d-256x256-right-edge:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109278]) +7 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_cursor_edge_walk@pipe-d-256x256-right-edge.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109274] / [fdo#109278])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-kbl:          [PASS][52] -> [FAIL][53] ([i915#2346])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl1/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_dp_tiled_display@basic-test-pattern:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#426])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_dp_tiled_display@basic-test-pattern.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][55] -> [FAIL][56] ([i915#79])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109274]) +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_flip@blocking-absolute-wf_vblank@a-edp1:
    - shard-skl:          [PASS][58] -> [DMESG-WARN][59] ([i915#1982]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl7/igt@kms_flip@blocking-absolute-wf_vblank@a-edp1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl9/igt@kms_flip@blocking-absolute-wf_vblank@a-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][60] -> [DMESG-WARN][61] ([i915#180])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
    - shard-apl:          NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2642])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109280]) +10 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt:
    - shard-kbl:          NOTRUN -> [SKIP][64] ([fdo#109271]) +6 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-msflip-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#533]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +3 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][67] ([i915#265]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl8/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_lowres@pipe-c-tiling-none:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([i915#3536])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_plane_lowres@pipe-c-tiling-none.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#2733])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658]) +6 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl1/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([i915#658])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][72] -> [SKIP][73] ([fdo#109441]) +2 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb7/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][74] ([IGT#2])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl8/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][75] -> [INCOMPLETE][76] ([i915#155])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][77] -> [DMESG-WARN][78] ([i915#180] / [i915#295])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-idle:
    - shard-apl:          NOTRUN -> [SKIP][79] ([fdo#109271]) +321 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@kms_vblank@pipe-d-ts-continuation-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#2437]) +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl1/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([i915#2530])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html

  * igt@perf@polling-parameterized:
    - shard-glk:          [PASS][82] -> [FAIL][83] ([i915#1542])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk4/igt@perf@polling-parameterized.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk3/igt@perf@polling-parameterized.html

  * igt@perf_pmu@rc6-suspend:
    - shard-skl:          [PASS][84] -> [INCOMPLETE][85] ([i915#198] / [i915#2910])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl7/igt@perf_pmu@rc6-suspend.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl9/igt@perf_pmu@rc6-suspend.html

  * igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([fdo#109291])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html

  * igt@prime_vgem@coherency-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([fdo#109292])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-write-hang:
    - shard-iclb:         NOTRUN -> [SKIP][88] ([fdo#109295])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@prime_vgem@fence-write-hang.html

  * igt@runner@aborted:
    - shard-apl:          NOTRUN -> ([FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#3363])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl1/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl3/igt@runner@aborted.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@runner@aborted.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl8/igt@runner@aborted.html

  * igt@sysfs_clients@recycle-many:
    - shard-apl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#2994]) +4 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl7/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@sema-50:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([i915#2994])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb5/igt@sysfs_clients@sema-50.html

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - shard-skl:          [PASS][95] -> [FAIL][96] ([i915#1731])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl8/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [FAIL][97] ([i915#2842]) -> [PASS][98] +1 similar issue
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [FAIL][99] ([i915#2842]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
    - shard-apl:          [FAIL][101] ([i915#2842] / [i915#3468]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-apl1/igt@gem_exec_fair@basic-none@vecs0.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][103] ([i915#2842]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-glk:          [FAIL][105] ([i915#307]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk5/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk3/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [FAIL][107] ([i915#2428]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb7/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@kms_async_flips@alternate-sync-async-flip:
    - shard-glk:          [FAIL][109] ([i915#2521]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-glk3/igt@kms_async_flips@alternate-sync-async-flip.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
    - shard-skl:          [FAIL][111] ([i915#3451]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl1/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl5/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [FAIL][113] ([i915#1188]) -> [PASS][114] +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][115] ([i915#180]) -> [PASS][116] +1 similar issue
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][117] ([fdo#108145] / [i915#265]) -> [PASS][118] +2 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][119] ([fdo#109441]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@perf@polling:
    - shard-skl:          [FAIL][121] ([i915#1542]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl6/igt@perf@polling.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl8/igt@perf@polling.html

  * igt@sysfs_heartbeat_interval@mixed@vecs0:
    - shard-skl:          [FAIL][123] ([i915#1731]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-skl8/igt@sysfs_heartbeat_interval@mixed@vecs0.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-skl4/igt@sysfs_heartbeat_interval@mixed@vecs0.html

  
#### Warnings ####

  * igt@i915_selftest@live@execlists:
    - shard-iclb:         [INCOMPLETE][125] ([i915#2782] / [i915#3462]) -> [DMESG-FAIL][126] ([i915#3462])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb4/igt@i915_selftest@live@execlists.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb6/igt@i915_selftest@live@execlists.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
    - shard-iclb:         [SKIP][127] ([i915#658]) -> [SKIP][128] ([i915#2920]) +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][137], [FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl7/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl3/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl7/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/shard-kbl1/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10213/

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20350/index.html

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^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging
  2021-06-11 19:43 ` [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
@ 2021-06-12  4:39   ` Lucas De Marchi
  0 siblings, 0 replies; 11+ messages in thread
From: Lucas De Marchi @ 2021-06-12  4:39 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

On Fri, Jun 11, 2021 at 12:43:53PM -0700, Anusha Srivatsa wrote:
>This patch adds Pipe A plumbing to the already
>existing parsing and loading functions which is
>taken care of in the prep patches. Adding MAX_DMC_FW
>to keep track for both Main and Pipe A DMC while loading
>the respective blobs.
>
>Also adding present field in dmc_info.
>s/find_dmc_fw_offset/csr_set_dmc_fw_offset. While at it add
>fw_info_matches_stepping() helper. CSR_PROGRAM() should now
>take the starting address of the particular blob (Main or Pipe)
>and not hardcode it.
>
>v2: Add dmc_offset and start_mmioaddr fields for dmc_info struct.
>
>v3: Add a missing corner cases of stepping-substepping combination in
>fw_info_matches_stepping() helper.
>
>v4: Add macro for start_mmioaddr for V1 package. Simplify code
>in dmc_set_fw_offset (Lucas)
>
>Cc: Souza, Jose <jose.souza@intel.com>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> .../drm/i915/display/intel_display_debugfs.c  |   4 +-
> .../drm/i915/display/intel_display_power.c    |   5 +-
> drivers/gpu/drm/i915/display/intel_dmc.c      | 131 ++++++++++--------
> drivers/gpu/drm/i915/display/intel_dmc.h      |   4 +
> drivers/gpu/drm/i915/i915_reg.h               |   2 +-
> 5 files changed, 85 insertions(+), 61 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index 88bb05d5c483..2a1c39a0e56e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -544,6 +544,8 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> 	seq_printf(m, "fw loaded: %s\n", yesno(intel_dmc_has_payload(dev_priv)));
> 	seq_printf(m, "path: %s\n", dmc->fw_path);
>+	seq_printf(m, "Pipe A fw support: %s\n", yesno(INTEL_GEN(dev_priv) >= 12));
>+	seq_printf(m, "Pipe A fw loaded: %s\n", yesno(dmc->dmc_info[DMC_FW_PIPEA].payload));
>
> 	if (!intel_dmc_has_payload(dev_priv))
> 		goto out;
>@@ -582,7 +584,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>
> out:
> 	seq_printf(m, "program base: 0x%08x\n",
>-		   intel_de_read(dev_priv, DMC_PROGRAM(0)));
>+		   intel_de_read(dev_priv, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> 	seq_printf(m, "ssp base: 0x%08x\n",
> 		   intel_de_read(dev_priv, DMC_SSP_BASE));
> 	seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, DMC_HTP_SKL));
>diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>index 4298ae684d7d..285380079aab 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_power.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>@@ -961,8 +961,9 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
> {
> 	drm_WARN_ONCE(&dev_priv->drm,
>-		      !intel_de_read(dev_priv, DMC_PROGRAM(0)),
>-		      "DMC program storage start is NULL\n");
>+		      !intel_de_read(dev_priv,
>+				     DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
>+				     "DMC program storage start is NULL\n");
> 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
> 		      "DMC SSP Base Not fine\n");
> 	drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 269a57d936ab..18e0d225a478 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -96,6 +96,7 @@ MODULE_FIRMWARE(BXT_DMC_PATH);
> #define PACKAGE_V2_MAX_FW_INFO_ENTRIES	32
> #define DMC_V1_MAX_MMIO_COUNT		8
> #define DMC_V3_MAX_MMIO_COUNT		20
>+#define DMC_V1_MMIO_START_RANGE		0x80000
>
> struct intel_css_header {
> 	/* 0x09 for DMC */
>@@ -317,8 +318,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
> void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> {
> 	struct intel_dmc *dmc = &dev_priv->dmc;
>-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
>-	u32 i, fw_size;
>+	u32 id, i;
>
> 	if (!HAS_DMC(dev_priv)) {
> 		drm_err(&dev_priv->drm,
>@@ -332,20 +332,25 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 		return;
> 	}
>
>-	fw_size = dmc_info->dmc_fw_size;
> 	assert_rpm_wakelock_held(&dev_priv->runtime_pm);
>
> 	preempt_disable();
>
>-	for (i = 0; i < fw_size; i++)
>-		intel_uncore_write_fw(&dev_priv->uncore, DMC_PROGRAM(i),
>-				      dmc_info->payload[i]);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) {
>+			intel_uncore_write_fw(&dev_priv->uncore,
>+					      DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i),
>+					      dmc->dmc_info[id].payload[i]);
>+		}
>+	}
>
> 	preempt_enable();
>
>-	for (i = 0; i < dmc_info->mmio_count; i++) {
>-		intel_de_write(dev_priv, dmc_info->mmioaddr[i],
>-			       dmc_info->mmiodata[i]);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) {
>+			intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i],
>+				       dmc->dmc_info[id].mmiodata[i]);
>+		}
> 	}
>
> 	dev_priv->dmc.dc_state = 0;
>@@ -353,59 +358,68 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
> 	gen9_set_dc_state_debugmask(dev_priv);
> }
>
>+static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info,
>+				     const struct stepping_info *si)
>+{
>+	if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) ||
>+	    (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) ||
>+	    /*
>+	     * If we don't find a more specific one from above two checks, we
>+	     * then check for the generic one to be sure to work even with
>+	     * "broken firmware"
>+	     */
>+	    (si->stepping == '*' && si->substepping == fw_info->substepping) ||
>+	    (fw_info->stepping == '*' && fw_info->substepping == '*'))
>+		return true;
>+
>+	return false;
>+}
>+
> /*
>  * Search fw_info table for dmc_offset to find firmware binary: num_entries is
>  * already sanitized.
>  */
>-static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
>+static void dmc_set_fw_offset(struct intel_dmc *dmc,
>+			      const struct intel_fw_info *fw_info,
> 			      unsigned int num_entries,
> 			      const struct stepping_info *si,
> 			      u8 package_ver)
> {
>-	u32 dmc_offset = DMC_DEFAULT_FW_OFFSET;
>-	unsigned int i;
>+	unsigned int i, id;
>+
>+	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
>
> 	for (i = 0; i < num_entries; i++) {
>-		if (package_ver > 1 && fw_info[i].dmc_id != 0)
>-			continue;
>+		id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
>
>-		if (fw_info[i].substepping == '*' &&
>-		    si->stepping == fw_info[i].stepping) {
>-			dmc_offset = fw_info[i].offset;
>-			break;
>+		if (id >= DMC_FW_MAX) {
>+			drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id);
>+			continue;
> 		}
>
>-		if (si->stepping == fw_info[i].stepping &&
>-		    si->substepping == fw_info[i].substepping) {
>-			dmc_offset = fw_info[i].offset;
>-			break;
>-		}
>+		/* More specific versions come first, so we don't even have to
>+		 * check for the stepping since we already found a previous FW
>+		 * for this id.
>+		 */
>+		if (dmc->dmc_info[id].present)
>+			continue;
>
>-		if (fw_info[i].stepping == '*' &&
>-		    fw_info[i].substepping == '*') {
>-			/*
>-			 * In theory we should stop the search as generic
>-			 * entries should always come after the more specific
>-			 * ones, but let's continue to make sure to work even
>-			 * with "broken" firmwares. If we don't find a more
>-			 * specific one, then we use this entry
>-			 */
>-			dmc_offset = fw_info[i].offset;
>+		if (fw_info_matches_stepping(&fw_info[i], si)) {
>+			dmc->dmc_info[id].present = true;
>+			dmc->dmc_info[id].dmc_offset = fw_info[i].offset;
> 		}
> 	}
>-
>-	return dmc_offset;
> }
>
> static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 			       const struct intel_dmc_header_base *dmc_header,
>-			       size_t rem_size)
>+			       size_t rem_size, u8 dmc_id)
> {
> 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
>-	struct dmc_fw_info *dmc_info = &dmc->dmc_info[DMC_FW_MAIN];
>+	struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
> 	unsigned int header_len_bytes, dmc_header_size, payload_size, i;
> 	const u32 *mmioaddr, *mmiodata;
>-	u32 mmio_count, mmio_count_max;
>+	u32 mmio_count, mmio_count_max, start_mmioaddr;
> 	u8 *payload;
>
> 	BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
>@@ -432,6 +446,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
> 		/* header_len is in dwords */
> 		header_len_bytes = dmc_header->header_len * 4;
>+		start_mmioaddr = v3->start_mmioaddr;
> 		dmc_header_size = sizeof(*v3);
> 	} else if (dmc_header->header_ver == 1) {
> 		const struct intel_dmc_header_v1 *v1 =
>@@ -445,6 +460,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 		mmio_count = v1->mmio_count;
> 		mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
> 		header_len_bytes = dmc_header->header_len;
>+		start_mmioaddr = DMC_V1_MMIO_START_RANGE;
> 		dmc_header_size = sizeof(*v1);
> 	} else {
> 		drm_err(&i915->drm, "Unknown DMC fw header version: %u\n",
>@@ -465,16 +481,11 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
> 	}
>
> 	for (i = 0; i < mmio_count; i++) {
>-		if (mmioaddr[i] < DMC_MMIO_START_RANGE ||
>-		    mmioaddr[i] > DMC_MMIO_END_RANGE) {
>-			drm_err(&i915->drm, "DMC firmware has wrong mmio address 0x%x\n",
>-				mmioaddr[i]);
>-			return 0;
>-		}
> 		dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]);
> 		dmc_info->mmiodata[i] = mmiodata[i];
> 	}
> 	dmc_info->mmio_count = mmio_count;
>+	dmc_info->start_mmioaddr = start_mmioaddr;
>
> 	rem_size -= header_len_bytes;
>
>@@ -511,7 +522,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
> {
> 	struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
> 	u32 package_size = sizeof(struct intel_package_header);
>-	u32 num_entries, max_entries, dmc_offset;
>+	u32 num_entries, max_entries;
> 	const struct intel_fw_info *fw_info;
>
> 	if (rem_size < package_size)
>@@ -547,16 +558,11 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
>
> 	fw_info = (const struct intel_fw_info *)
> 		((u8 *)package_header + sizeof(*package_header));
>-	dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
>-					package_header->header_ver);
>-	if (dmc_offset == DMC_DEFAULT_FW_OFFSET) {
>-		drm_err(&i915->drm, "DMC firmware not supported for %c stepping\n",
>-			si->stepping);
>-		return 0;
>-	}
>+	dmc_set_fw_offset(dmc, fw_info, num_entries, si,
>+			  package_header->header_ver);
>
> 	/* dmc_offset is in dwords */
>-	return package_size + dmc_offset * 4;
>+	return package_size;
>
> error_truncated:
> 	drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
>@@ -608,7 +614,8 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
> 	struct intel_dmc *dmc = &dev_priv->dmc;
> 	const struct stepping_info *si = intel_get_stepping_info(dev_priv);
> 	u32 readcount = 0;
>-	u32 r;
>+	u32 r, offset;
>+	int id;
>
> 	if (!fw)
> 		return;
>@@ -629,9 +636,19 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
>
> 	readcount += r;
>
>-	/* Extract dmc_header information */
>-	dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
>-	parse_dmc_fw_header(dmc, dmc_header, fw->size - readcount);
>+	for (id = 0; id < DMC_FW_MAX; id++) {
>+		if (!dev_priv->dmc.dmc_info[id].present)
>+			continue;
>+
>+		offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
>+		if (fw->size - offset < 0) {
>+			drm_err(&dev_priv->drm, "Reading beyond the fw_size\n");
>+			continue;
>+		}
>+
>+		dmc_header = (struct intel_dmc_header_base *)&fw->data[offset];
>+		parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id);
>+	}
> }
>
> static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>index b872f3a4fd03..007a284b0ef0 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.h
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>@@ -18,6 +18,7 @@ struct drm_i915_private;
>
> enum {
> 	DMC_FW_MAIN = 0,
>+	DMC_FW_PIPEA,
> 	DMC_FW_MAX
> };
>
>@@ -31,8 +32,11 @@ struct intel_dmc {
> 		u32 mmio_count;
> 		i915_reg_t mmioaddr[20];
> 		u32 mmiodata[20];
>+		u32 dmc_offset;
>+		u32 start_mmioaddr;
> 		u32 dmc_fw_size; /*dwords */
> 		u32 *payload;
>+		bool present;
> 	} dmc_info[DMC_FW_MAX];
>
> 	u32 dc_state;
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index e915ec034c98..fb5e8e12ff49 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7751,7 +7751,7 @@ enum {
> #define  GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED	(3 << 0) /* icl + */
>
> /* DMC */
>-#define DMC_PROGRAM(i)		_MMIO(0x80000 + (i) * 4)
>+#define DMC_PROGRAM(addr, i)	_MMIO((addr) + (i) * 4)
> #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
> #define DMC_HTP_ADDR_SKL	0x00500034
> #define DMC_SSP_BASE		_MMIO(0x8F074)
>-- 
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC
  2021-06-11 19:43 ` [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC Anusha Srivatsa
@ 2021-06-12  4:40   ` Lucas De Marchi
  0 siblings, 0 replies; 11+ messages in thread
From: Lucas De Marchi @ 2021-06-12  4:40 UTC (permalink / raw)
  To: Anusha Srivatsa; +Cc: intel-gfx

On Fri, Jun 11, 2021 at 12:43:55PM -0700, Anusha Srivatsa wrote:
>Load DMC v2.10 on ADLP. The release notes mention that
>this version enables few power savings features.
>
>v2: Add DMC_PATH() for ADLP (Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi@intel.com>
>Cc: Clint Taylor <clinton.a.taylor@intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/i915/display/intel_dmc.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 18e0d225a478..f8789d4543bf 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -45,6 +45,10 @@
>
> #define GEN12_DMC_MAX_FW_SIZE		ICL_DMC_MAX_FW_SIZE
>
>+#define ADLP_DMC_PATH			DMC_PATH(adlp, 2, 10)
>+#define ADLP_DMC_VERSION_REQUIRED	DMC_VERSION(2, 10)
>+MODULE_FIRMWARE(ADLP_DMC_PATH);
>+
> #define ADLS_DMC_PATH			DMC_PATH(adls, 2, 01)
> #define ADLS_DMC_VERSION_REQUIRED	DMC_VERSION(2, 1)
> MODULE_FIRMWARE(ADLS_DMC_PATH);
>@@ -724,7 +728,11 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
> 	 */
> 	intel_dmc_runtime_pm_get(dev_priv);
>
>-	if (IS_ALDERLAKE_S(dev_priv)) {
>+	if (IS_ALDERLAKE_P(dev_priv)) {
>+		dmc->fw_path = ADLP_DMC_PATH;
>+		dmc->required_version = ADLP_DMC_VERSION_REQUIRED;
>+		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>+	} else if (IS_ALDERLAKE_S(dev_priv)) {
> 		dmc->fw_path = ADLS_DMC_PATH;
> 		dmc->required_version = ADLS_DMC_VERSION_REQUIRED;
> 		dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE;
>-- 
>2.25.0
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-06-12  4:40 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-11 19:43 [Intel-gfx] [CI 0/4] Pipe DMC Support Anusha Srivatsa
2021-06-11 19:43 ` [Intel-gfx] [CI 1/4] drm/i915/dmc: Introduce DMC_FW_MAIN Anusha Srivatsa
2021-06-11 19:43 ` [Intel-gfx] [CI 2/4] drm/i915/xelpd: Pipe A DMC plugging Anusha Srivatsa
2021-06-12  4:39   ` Lucas De Marchi
2021-06-11 19:43 ` [Intel-gfx] [CI 3/4] drm/i915/adl_p: Pipe B DMC Support Anusha Srivatsa
2021-06-11 19:43 ` [Intel-gfx] [CI 4/4] drm/i915/adl_p: Load DMC Anusha Srivatsa
2021-06-12  4:40   ` Lucas De Marchi
2021-06-11 20:55 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Pipe DMC Support (rev7) Patchwork
2021-06-11 20:56 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-06-11 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-06-11 23:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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