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[14.203.186.173]) by smtp.gmail.com with ESMTPSA id q5sm13398648pgt.46.2021.07.07.06.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Jul 2021 06:56:43 -0700 (PDT) Date: Wed, 07 Jul 2021 23:56:37 +1000 From: Nicholas Piggin Subject: Re: [PATCH 06/19] LoongArch: Add exception/interrupt handling To: Huacai Chen , Peter Zijlstra Cc: David Airlie , Andrew Morton , Arnd Bergmann , Huacai Chen , Jiaxun Yang , linux-arch@vger.kernel.org, Xuefeng Li , Andy Lutomirski , Thomas Gleixner , Linus Torvalds References: <20210706041820.1536502-1-chenhuacai@loongson.cn> <20210706041820.1536502-7-chenhuacai@loongson.cn> In-Reply-To: MIME-Version: 1.0 Message-Id: <1625665981.7hbs7yesxx.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org Excerpts from Peter Zijlstra's message of July 6, 2021 9:06 pm: > On Tue, Jul 06, 2021 at 12:18:07PM +0800, Huacai Chen wrote: >> + .align 5 /* 32 byte rollback region */ >> +SYM_FUNC_START(__arch_cpu_idle) >> + /* start of rollback region */ >> + LONG_L t0, tp, TI_FLAGS >> + nop >> + andi t0, t0, _TIF_NEED_RESCHED >> + bnez t0, 1f >> + nop >> + nop >> + nop >> + idle 0 >> + /* end of rollback region */ >> +1: >> + jirl zero, ra, 0 >> +SYM_FUNC_END(__arch_cpu_idle) >=20 >> +/* >> + * Common Vectored Interrupt >> + * Complete the register saves and invoke the do_vi() handler >> + */ >> +SYM_FUNC_START(except_vec_vi_handler) >> + la t1, __arch_cpu_idle >> + LONG_L t0, sp, PT_EPC >> + /* 32 byte rollback region */ >> + ori t0, t0, 0x1f >> + xori t0, t0, 0x1f >> + bne t0, t1, 1f >> + LONG_S t0, sp, PT_EPC >=20 > Seriously, you're having your interrupt handler recover from the idle > race? On a *new* architecture? It's heavily derived from MIPS (does that make the wholesale replacement=20 of arch/mips copyright headers a bit questionable?). I don't think it's such a bad trick though -- restartable sequences=20 before they were cool. It can let you save an irq disable in some cases (depending on the arch of course). Thanks, Nick