From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4786EC07E9E for ; Fri, 9 Jul 2021 09:51:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 311586135C for ; Fri, 9 Jul 2021 09:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232129AbhGIJyF (ORCPT ); Fri, 9 Jul 2021 05:54:05 -0400 Received: from mga05.intel.com ([192.55.52.43]:54437 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232118AbhGIJyC (ORCPT ); Fri, 9 Jul 2021 05:54:02 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10039"; a="295316512" X-IronPort-AV: E=Sophos;i="5.84,226,1620716400"; d="scan'208";a="295316512" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2021 02:51:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,226,1620716400"; d="scan'208";a="498856312" Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.182]) by fmsmga002.fm.intel.com with ESMTP; 09 Jul 2021 02:51:17 -0700 From: Yang Weijiang To: pbonzini@redhat.com, seanjc@google.com, vkuznets@redhat.com, jmattson@google.com, wei.w.wang@intel.com, like.xu.linux@gmail.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Yang Weijiang Subject: [PATCH v5 06/13] KVM: x86/vmx: Save/Restore host MSR_ARCH_LBR_CTL state Date: Fri, 9 Jul 2021 18:05:04 +0800 Message-Id: <1625825111-6604-7-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com> References: <1625825111-6604-1-git-send-email-weijiang.yang@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If host is using MSR_ARCH_LBR_CTL then save it before vm-entry and reload it after vm-exit. Co-developed-by: Like Xu Signed-off-by: Like Xu Signed-off-by: Yang Weijiang --- arch/x86/kvm/vmx/vmx.c | 23 +++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.h | 1 + 2 files changed, 24 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 1a79ac1757af..0d714e76e2d5 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1397,6 +1397,26 @@ void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu, decache_tsc_multiplier(vmx); } +static inline unsigned long get_lbrctlmsr(void) +{ + unsigned long lbrctlmsr = 0; + + if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) + return 0; + + rdmsrl(MSR_ARCH_LBR_CTL, lbrctlmsr); + + return lbrctlmsr; +} + +static inline void update_lbrctlmsr(unsigned long lbrctlmsr) +{ + if (!static_cpu_has(X86_FEATURE_ARCH_LBR)) + return; + + wrmsrl(MSR_ARCH_LBR_CTL, lbrctlmsr); +} + /* * Switches to specified vcpu, until a matching vcpu_put(), but assumes * vcpu mutex is already taken. @@ -1410,6 +1430,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) vmx_vcpu_pi_load(vcpu, cpu); vmx->host_debugctlmsr = get_debugctlmsr(); + vmx->host_lbrctlmsr = get_lbrctlmsr(); } static void vmx_vcpu_put(struct kvm_vcpu *vcpu) @@ -6797,6 +6818,8 @@ static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu) /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ if (vmx->host_debugctlmsr) update_debugctlmsr(vmx->host_debugctlmsr); + if (vmx->host_lbrctlmsr) + update_lbrctlmsr(vmx->host_lbrctlmsr); #ifndef CONFIG_X86_64 /* diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h index cc362e2d3eaa..69e243fea23d 100644 --- a/arch/x86/kvm/vmx/vmx.h +++ b/arch/x86/kvm/vmx/vmx.h @@ -328,6 +328,7 @@ struct vcpu_vmx { u64 current_tsc_ratio; unsigned long host_debugctlmsr; + unsigned long host_lbrctlmsr; /* * Only bits masked by msr_ia32_feature_control_valid_bits can be set in -- 2.21.1