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From: Stephen Boyd <sboyd@kernel.org>
To: Dinh Nguyen <dinguyen@kernel.org>, linux-clk@vger.kernel.org
Cc: dinguyen@kernel.org, mturquette@baylibre.com,
	stable@vger.kernel.org, Kris Chaplin <kris.chaplin@intel.com>
Subject: Re: [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation
Date: Mon, 26 Jul 2021 17:56:39 -0700	[thread overview]
Message-ID: <162734739900.2368309.17470062376743652251@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20210713144621.605140-2-dinguyen@kernel.org>

Quoting Dinh Nguyen (2021-07-13 07:46:20)
> Correct the s2f_user0_mux clock representation.
> 
> Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
> Cc: stable@vger.kernel.org
> Signed-off-by: Kris Chaplin <kris.chaplin@intel.com>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---

Applied to clk-next

  reply	other threads:[~2021-07-27  0:56 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-13 14:46 [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Dinh Nguyen
2021-07-13 14:46 ` [PATCH 2/3] clk: socfpga: agilex: fix up s2f_user0_clk representation Dinh Nguyen
2021-07-27  0:56   ` Stephen Boyd [this message]
2021-07-13 14:46 ` [PATCH 3/3] clk: socfpga: agilex: add the bypass register for s2f_usr0 clock Dinh Nguyen
2021-07-27  0:56   ` Stephen Boyd
2021-07-27  0:56 ` [PATCH 1/3] clk: socfpga: agilex: fix the parents of the psi_ref_clk Stephen Boyd

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