From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BC57C432BE for ; Tue, 27 Jul 2021 17:55:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8759E60F8F for ; Tue, 27 Jul 2021 17:55:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231696AbhG0RzE (ORCPT ); Tue, 27 Jul 2021 13:55:04 -0400 Received: from mail.kernel.org ([198.145.29.99]:45170 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229591AbhG0RzD (ORCPT ); Tue, 27 Jul 2021 13:55:03 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id BAE4660F4F; Tue, 27 Jul 2021 17:55:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1627408502; bh=7YITf+6vCWg/2TcduJ15J7mKtAeA2eCG6DFSJLScR9A=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=pokUSmq2ZatQHOM7uTUWqlnIk6ssmOQLkInhd4gsg1+tem2n/aJUnUNK+v8a2ldWs +lKh3Q6Lvt/SAVBgBLQ6IKsySTPNZ/sY+TE+u67g9teoIB4rgOOujzdJvvxIMnPDqc 0TCTsE9xwpBLmj8mLITZ/UauyqTT9CLTBjGke8+gHljsda58MRoT39WmZZdKtFrAeL GztK5R8e+BMHIAwJ3KMy2ov8aXCdFVdN233jqVQ7AR/sttZOF66wduJHsgcJ+8hYv4 nElbyrQ20+Wiwoh6rqN4+Zxwrb7CCtu4/epQMesQZ6qpxkCWS5SIAk0qHygGMgp5d5 0OL0Q2vqBSyMw== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20210726105719.15793-8-chun-jie.chen@mediatek.com> References: <20210726105719.15793-1-chun-jie.chen@mediatek.com> <20210726105719.15793-8-chun-jie.chen@mediatek.com> Subject: Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data From: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, Weiyi Lu , Chun-Jie Chen To: Chun-Jie Chen , Matthias Brugger , Nicolas Boichat , Rob Herring Date: Tue, 27 Jul 2021 10:55:00 -0700 Message-ID: <162740850059.2368309.10593418620932998201@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Quoting Chun-Jie Chen (2021-07-26 03:57:05) > In all MediaTek PLL design, bit0 of CON0 register is always > the enable bit. > However, there's a special case of usbpll on MT8192. > The enable bit of usbpll is moved to bit2 of other register. > Add configurable en_reg and pll_en_bit for enable control or > default 0 where pll data are static variables. > Hence, CON0_BASE_EN could also be removed. > And there might have another special case on other chips, > the enable bit is still on CON0 register but not at bit0. >=20 > Reviewed-by: Ikjoon Jang > Signed-off-by: Weiyi Lu > Signed-off-by: Chun-Jie Chen > --- Applied to clk-next From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5A9FC432BE for ; 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b=pokUSmq2ZatQHOM7uTUWqlnIk6ssmOQLkInhd4gsg1+tem2n/aJUnUNK+v8a2ldWs +lKh3Q6Lvt/SAVBgBLQ6IKsySTPNZ/sY+TE+u67g9teoIB4rgOOujzdJvvxIMnPDqc 0TCTsE9xwpBLmj8mLITZ/UauyqTT9CLTBjGke8+gHljsda58MRoT39WmZZdKtFrAeL GztK5R8e+BMHIAwJ3KMy2ov8aXCdFVdN233jqVQ7AR/sttZOF66wduJHsgcJ+8hYv4 nElbyrQ20+Wiwoh6rqN4+Zxwrb7CCtu4/epQMesQZ6qpxkCWS5SIAk0qHygGMgp5d5 0OL0Q2vqBSyMw== MIME-Version: 1.0 In-Reply-To: <20210726105719.15793-8-chun-jie.chen@mediatek.com> References: <20210726105719.15793-1-chun-jie.chen@mediatek.com> <20210726105719.15793-8-chun-jie.chen@mediatek.com> Subject: Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data From: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, Weiyi Lu , Chun-Jie Chen To: Chun-Jie Chen , Matthias Brugger , Nicolas Boichat , Rob Herring Date: Tue, 27 Jul 2021 10:55:00 -0700 Message-ID: <162740850059.2368309.10593418620932998201@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210727_105503_496369_9FED8F0B X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Quoting Chun-Jie Chen (2021-07-26 03:57:05) > In all MediaTek PLL design, bit0 of CON0 register is always > the enable bit. > However, there's a special case of usbpll on MT8192. > The enable bit of usbpll is moved to bit2 of other register. > Add configurable en_reg and pll_en_bit for enable control or > default 0 where pll data are static variables. > Hence, CON0_BASE_EN could also be removed. > And there might have another special case on other chips, > the enable bit is still on CON0 register but not at bit0. > > Reviewed-by: Ikjoon Jang > Signed-off-by: Weiyi Lu > Signed-off-by: Chun-Jie Chen > --- Applied to clk-next _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B1B0C4338F for ; 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b=pokUSmq2ZatQHOM7uTUWqlnIk6ssmOQLkInhd4gsg1+tem2n/aJUnUNK+v8a2ldWs +lKh3Q6Lvt/SAVBgBLQ6IKsySTPNZ/sY+TE+u67g9teoIB4rgOOujzdJvvxIMnPDqc 0TCTsE9xwpBLmj8mLITZ/UauyqTT9CLTBjGke8+gHljsda58MRoT39WmZZdKtFrAeL GztK5R8e+BMHIAwJ3KMy2ov8aXCdFVdN233jqVQ7AR/sttZOF66wduJHsgcJ+8hYv4 nElbyrQ20+Wiwoh6rqN4+Zxwrb7CCtu4/epQMesQZ6qpxkCWS5SIAk0qHygGMgp5d5 0OL0Q2vqBSyMw== MIME-Version: 1.0 In-Reply-To: <20210726105719.15793-8-chun-jie.chen@mediatek.com> References: <20210726105719.15793-1-chun-jie.chen@mediatek.com> <20210726105719.15793-8-chun-jie.chen@mediatek.com> Subject: Re: [v14 07/21] clk: mediatek: Add configurable enable control to mtk_pll_data From: Stephen Boyd Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, srv_heupstream@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com, Weiyi Lu , Chun-Jie Chen To: Chun-Jie Chen , Matthias Brugger , Nicolas Boichat , Rob Herring Date: Tue, 27 Jul 2021 10:55:00 -0700 Message-ID: <162740850059.2368309.10593418620932998201@swboyd.mtv.corp.google.com> User-Agent: alot/0.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210727_105503_496369_9FED8F0B X-CRM114-Status: UNSURE ( 9.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Quoting Chun-Jie Chen (2021-07-26 03:57:05) > In all MediaTek PLL design, bit0 of CON0 register is always > the enable bit. > However, there's a special case of usbpll on MT8192. > The enable bit of usbpll is moved to bit2 of other register. > Add configurable en_reg and pll_en_bit for enable control or > default 0 where pll data are static variables. > Hence, CON0_BASE_EN could also be removed. > And there might have another special case on other chips, > the enable bit is still on CON0 register but not at bit0. > > Reviewed-by: Ikjoon Jang > Signed-off-by: Weiyi Lu > Signed-off-by: Chun-Jie Chen > --- Applied to clk-next _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel