From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de> To: linux-tip-commits@vger.kernel.org Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, stable@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [tip: irq/core] x86/msi: Force affinity setup before startup Date: Tue, 10 Aug 2021 09:07:42 -0000 [thread overview] Message-ID: <162858646212.395.10672951353758752263.tip-bot2@tip-bot2> (raw) In-Reply-To: <20210729222542.886722080@linutronix.de> The following commit has been merged into the irq/core branch of tip: Commit-ID: ff363f480e5997051dd1de949121ffda3b753741 Gitweb: https://git.kernel.org/tip/ff363f480e5997051dd1de949121ffda3b753741 Author: Thomas Gleixner <tglx@linutronix.de> AuthorDate: Thu, 29 Jul 2021 23:51:50 +02:00 Committer: Thomas Gleixner <tglx@linutronix.de> CommitterDate: Tue, 10 Aug 2021 10:59:21 +02:00 x86/msi: Force affinity setup before startup The X86 MSI mechanism cannot handle interrupt affinity changes safely after startup other than from an interrupt handler, unless interrupt remapping is enabled. The startup sequence in the generic interrupt code violates that assumption. Mark the irq chips with the new IRQCHIP_AFFINITY_PRE_STARTUP flag so that the default interrupt setting happens before the interrupt is started up for the first time. While the interrupt remapping MSI chip does not require this, there is no point in treating it differently as this might spare an interrupt to a CPU which is not in the default affinity mask. For the non-remapping case go to the direct write path when the interrupt is not yet started similar to the not yet activated case. Fixes: 18404756765c ("genirq: Expose default irq affinity mask (take 3)") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20210729222542.886722080@linutronix.de --- arch/x86/kernel/apic/msi.c | 11 ++++++++--- arch/x86/kernel/hpet.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c index 44ebe25..dbacb9e 100644 --- a/arch/x86/kernel/apic/msi.c +++ b/arch/x86/kernel/apic/msi.c @@ -58,11 +58,13 @@ msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) * The quirk bit is not set in this case. * - The new vector is the same as the old vector * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up) + * - The interrupt is not yet started up * - The new destination CPU is the same as the old destination CPU */ if (!irqd_msi_nomask_quirk(irqd) || cfg->vector == old_cfg.vector || old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR || + !irqd_is_started(irqd) || cfg->dest_apicid == old_cfg.dest_apicid) { irq_msi_update_msg(irqd, cfg); return ret; @@ -150,7 +152,8 @@ static struct irq_chip pci_msi_controller = { .irq_ack = irq_chip_ack_parent, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_set_affinity = msi_set_affinity, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, @@ -219,7 +222,8 @@ static struct irq_chip pci_msi_ir_controller = { .irq_mask = pci_msi_mask_irq, .irq_ack = irq_chip_ack_parent, .irq_retrigger = irq_chip_retrigger_hierarchy, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static struct msi_domain_info pci_msi_ir_domain_info = { @@ -273,7 +277,8 @@ static struct irq_chip dmar_msi_controller = { .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_compose_msi_msg = dmar_msi_compose_msg, .irq_write_msi_msg = dmar_msi_write_msg, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_AFFINITY_PRE_STARTUP, }; static int dmar_msi_init(struct irq_domain *domain, diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c index 08651a4..42fc41d 100644 --- a/arch/x86/kernel/hpet.c +++ b/arch/x86/kernel/hpet.c @@ -508,7 +508,7 @@ static struct irq_chip hpet_msi_controller __ro_after_init = { .irq_set_affinity = msi_domain_set_affinity, .irq_retrigger = irq_chip_retrigger_hierarchy, .irq_write_msi_msg = hpet_msi_write_msg, - .flags = IRQCHIP_SKIP_SET_WAKE, + .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP, }; static int hpet_msi_init(struct irq_domain *domain,
next prev parent reply other threads:[~2021-08-10 9:08 UTC|newest] Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-29 21:51 [patch V2 00/19] PCI/MSI, x86: Cure a couple of inconsistencies Thomas Gleixner 2021-07-29 21:51 ` [patch V2 01/19] PCI/MSI: Enable and mask MSI-X early Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 02/19] PCI/MSI: Mask all unused MSI-X entries Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 03/19] PCI/MSI: Enforce that MSI-X table entry is masked for update Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 04/19] PCI/MSI: Enforce MSI[X] entry updates to be visible Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 05/19] PCI/MSI: Do not set invalid bits in MSI mask Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 06/19] PCI/MSI: Correct misleading comments Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 07/19] PCI/MSI: Use msi_mask_irq() in pci_msi_shutdown() Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 08/19] PCI/MSI: Protect msi_desc::masked for multi-MSI Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 09/19] genirq: Provide IRQCHIP_AFFINITY_PRE_STARTUP Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 10/19] x86/ioapic: Force affinity setup before startup Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 11/19] x86/msi: " Thomas Gleixner 2021-08-10 9:07 ` tip-bot2 for Thomas Gleixner [this message] 2021-07-29 21:51 ` [patch V2 12/19] s390/pci: Do not mask MSI[-X] entries on teardown Thomas Gleixner 2021-08-03 12:48 ` Niklas Schnelle 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 13/19] PCI/MSI: Simplify msi_verify_entries() Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 14/19] PCI/MSI: Rename msi_desc::masked Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 15/19] PCI/MSI: Consolidate error handling in msi_capability_init() Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 16/19] PCI/MSI: Deobfuscate virtual MSI-X Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 17/19] PCI/MSI: Cleanup msi_mask() Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 18/19] PCI/MSI: Provide a new set of mask and unmask functions Thomas Gleixner [not found] ` <87r1f6bpt7.wl-maz@kernel.org> 2021-08-09 18:56 ` Thomas Gleixner 2021-08-09 19:08 ` [patch V3 " Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-07-29 21:51 ` [patch V2 19/19] PCI/MSI: Use new mask/unmask functions Thomas Gleixner 2021-08-10 9:07 ` [tip: irq/core] " tip-bot2 for Thomas Gleixner 2021-08-10 7:49 ` [patch V2 00/19] PCI/MSI, x86: Cure a couple of inconsistencies Marc Zyngier
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=162858646212.395.10672951353758752263.tip-bot2@tip-bot2 \ --to=tip-bot2@linutronix.de \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-tip-commits@vger.kernel.org \ --cc=maz@kernel.org \ --cc=stable@vger.kernel.org \ --cc=tglx@linutronix.de \ --cc=x86@kernel.org \ --subject='Re: [tip: irq/core] x86/msi: Force affinity setup before startup' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.