From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F252FC4320A for ; Mon, 16 Aug 2021 12:11:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D89666320F for ; Mon, 16 Aug 2021 12:11:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233156AbhHPMMN (ORCPT ); Mon, 16 Aug 2021 08:12:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:51156 "EHLO mailgw02.mediatek.com" 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15.0.1497.2; Mon, 16 Aug 2021 20:11:38 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 16 Aug 2021 20:11:38 +0800 Message-ID: <1629115898.29907.3.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] spmi: mediatek: Add support for MT6873/8192 From: Hsin-hsiung Wang To: Stephen Boyd CC: Matthias Brugger , Rob Herring , , , , , , Date: Mon, 16 Aug 2021 20:11:38 +0800 In-Reply-To: <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> References: <1627972461-2627-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1627972461-2627-4-git-send-email-hsin-hsiung.wang@mediatek.com> <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGksDQoNCk9uIE1vbiwgMjAyMS0wOC0wOSBhdCAxMDo1NSAtMDcwMCwgU3RlcGhlbiBCb3lkIHdy b3RlOg0KPiBRdW90aW5nIEhzaW4tSHNpdW5nIFdhbmcgKDIwMjEtMDgtMDIgMjM6MzQ6MTkpDQo+ ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvc3BtaS9zcG1pLW10ay1wbWlmLmMgYi9kcml2ZXJzL3Nw bWkvc3BtaS1tdGstcG1pZi5jDQo+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQNCj4gPiBpbmRleCAw MDAwMDAwMDAwMDAuLjk0YzQ1ZDQ2YWIwYw0KPiA+IC0tLSAvZGV2L251bGwNCj4gPiArKysgYi9k cml2ZXJzL3NwbWkvc3BtaS1tdGstcG1pZi5jDQo+ID4gQEAgLTAsMCArMSw0NjUgQEANCj4gPiAr Ly8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjANCj4gPiArLy8NCj4gPiArLy8gQ29w eXJpZ2h0IChjKSAyMDIxIE1lZGlhVGVrIEluYy4NCj4gPiArDQo+ID4gKyNpbmNsdWRlIDxsaW51 eC9jbGsuaD4NCj4gPiArI2luY2x1ZGUgPGxpbnV4L2lvcG9sbC5oPg0KPiA+ICsjaW5jbHVkZSA8 bGludXgvbW9kdWxlLmg+DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9vZl9kZXZpY2UuaD4NCj4gDQo+ IGluY2x1ZGUgcGxhdGZvcm1fZGV2aWNlLmggZm9yIHRoZSBwbGF0Zm9ybSBkZXZpY2UgZHJpdmVy IHRoYXQgdGhpcyBpcy4NCj4gDQpUaGFua3MgZm9yIHRoZSBjb21taXQsIEkgd2lsbCB1cGRhdGUg aXQgaW4gdGhlIG5leHQgcGF0Y2guDQoNCj4gPiArI2luY2x1ZGUgPGxpbnV4L3NwbWkuaD4NCj4g PiArDQo+ID4gKyNkZWZpbmUgU1dJTkZfSURMRSAgICAgMHgwMA0KPiA+ICsjZGVmaW5lIFNXSU5G X1dGVkxEQ0xSIDB4MDYNCj4gPiArDQo+ID4gKyNkZWZpbmUgR0VUX1NXSU5GKHgpICAgKCgoeCkg Pj4gMSkgJiAweDcpDQo+ID4gKw0KPiA+ICsjZGVmaW5lIFBNSUZfQ01EX1JFR18wICAgICAgICAg MA0KPiA+ICsjZGVmaW5lIFBNSUZfQ01EX1JFRyAgICAgICAgICAgMQ0KPiA+ICsjZGVmaW5lIFBN SUZfQ01EX0VYVF9SRUcgICAgICAgMg0KPiA+ICsjZGVmaW5lIFBNSUZfQ01EX0VYVF9SRUdfTE9O RyAgMw0KPiA+ICsNCj4gPiArI2RlZmluZSBQTUlGX0RFTEFZX1VTICAgMTANCj4gPiArI2RlZmlu ZSBQTUlGX1RJTUVPVVRfVVMgKDEwICogMTAwMCkNCj4gPiArDQo+ID4gKyNkZWZpbmUgUE1JRl9D SEFOX09GRlNFVCAweDUNCj4gPiArDQo+ID4gKyNkZWZpbmUgUE1JRl9NQVhfQ0xLUyAgMw0KPiA+ ICsNCj4gPiArI2RlZmluZSBTUE1JX09QX1NUX0JVU1kgMQ0KPiA+ICsNCj4gPiArc3RydWN0IGNo X3JlZyB7DQo+ID4gKyAgICAgICB1MzIgY2hfc3RhOw0KPiA+ICsgICAgICAgdTMyIHdkYXRhOw0K PiA+ICsgICAgICAgdTMyIHJkYXRhOw0KPiA+ICsgICAgICAgdTMyIGNoX3NlbmQ7DQo+ID4gKyAg ICAgICB1MzIgY2hfcmR5Ow0KPiA+ICt9Ow0KPiA+ICsNCj4gPiArc3RydWN0IHBtaWZfZGF0YSB7 DQo+ID4gKyAgICAgICBjb25zdCB1MzIgICAgICAgKnJlZ3M7DQo+ID4gKyAgICAgICBjb25zdCB1 MzIgICAgICAgKnNwbWltc3RfcmVnczsNCj4gPiArICAgICAgIHUzMiAgICAgc29jX2NoYW47DQo+ ID4gK307DQo+ID4gKw0KPiA+ICtzdHJ1Y3QgcG1pZiB7DQo+ID4gKyAgICAgICB2b2lkIF9faW9t ZW0gICAgKmJhc2U7DQo+ID4gKyAgICAgICB2b2lkIF9faW9tZW0gICAgKnNwbWltc3RfYmFzZTsN Cj4gPiArICAgICAgIHN0cnVjdCBjaF9yZWcgICBjaGFuOw0KPiA+ICsgICAgICAgc3RydWN0IGNs a19idWxrX2RhdGEgY2xrc1tQTUlGX01BWF9DTEtTXTsNCj4gPiArICAgICAgIHUzMiBuY2xrczsN Cj4gDQo+IHNpemVfdD8gU3VyZWx5IDMyLWJpdHMgaXNuJ3QgaW1wb3J0YW50Lg0KPiANCg0KVGhh bmtzLiBJIHdpbGwgdXNlIHNpemVfdCBpbiB0aGUgbmV4dCBwYXRjaC4NCg0KPiA+ICsgICAgICAg Y29uc3Qgc3RydWN0IHBtaWZfZGF0YSAqZGF0YTsNCj4gPiArfTsNCj4gPiArDQo+ID4gK3N0YXRp YyBjb25zdCBjaGFyICogY29uc3QgcG1pZl9jbG9ja19uYW1lc1tdID0gew0KPiA+ICsgICAgICAg InBtaWZfc3lzX2NrIiwgInBtaWZfdG1yX2NrIiwgInNwbWltc3RfY2xrX211eCIsDQo+ID4gK307 DQo+IFsuLi5dDQo+ID4gKw0KPiA+ICtzdGF0aWMgYm9vbCBwbWlmX2lzX2ZzbV92bGRjbHIoc3Ry dWN0IHBtaWYgKmFyYikNCj4gPiArew0KPiA+ICsgICAgICAgdTMyIHJlZ19yZGF0YTsNCj4gPiAr DQo+ID4gKyAgICAgICByZWdfcmRhdGEgPSBwbWlmX3JlYWRsKGFyYiwgYXJiLT5jaGFuLmNoX3N0 YSk7DQo+IA0KPiBOZXdsaW5lIGhlcmUgcGxlYXNlLg0KPiANCg0KVGhhbmtzLCBJIHdpbGwgdXBk YXRlIGl0IGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4gKyAgICAgICByZXR1cm4gR0VUX1NXSU5G KHJlZ19yZGF0YSkgPT0gU1dJTkZfV0ZWTERDTFI7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRp YyBpbnQgcG1pZl9hcmJfY21kKHN0cnVjdCBzcG1pX2NvbnRyb2xsZXIgKmN0cmwsIHU4IG9wYywg dTggc2lkKQ0KPiA+ICt7DQo+ID4gKyAgICAgICBzdHJ1Y3QgcG1pZiAqYXJiID0gc3BtaV9jb250 cm9sbGVyX2dldF9kcnZkYXRhKGN0cmwpOw0KPiA+ICsgICAgICAgdTMyIHJkYXRhLCBjbWQ7DQo+ ID4gKyAgICAgICBpbnQgcmV0Ow0KPiA+ICsNCj4gPiArICAgICAgIC8qIENoZWNrIHRoZSBvcGNv ZGUgKi8NCj4gPiArICAgICAgIGlmIChvcGMgPCBTUE1JX0NNRF9SRVNFVCB8fCBvcGMgPiBTUE1J X0NNRF9XQUtFVVApDQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiAtRUlOVkFMOw0KPiA+ICsN Cj4gPiArICAgICAgIGNtZCA9IG9wYyAtIFNQTUlfQ01EX1JFU0VUOw0KPiA+ICsNCj4gPiArICAg ICAgIG10a19zcG1pX3dyaXRlbChhcmIsIChjbWQgPDwgMHg0KSB8IHNpZCwgU1BNSV9PUF9TVF9D VFJMKTsNCj4gPiArICAgICAgIHJldCA9IHJlYWRsX3BvbGxfdGltZW91dF9hdG9taWMoYXJiLT5z cG1pbXN0X2Jhc2UgKyBhcmItPmRhdGEtPnNwbWltc3RfcmVnc1tTUE1JX09QX1NUX1NUQV0sDQo+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJkYXRhLCAocmRhdGEg JiBTUE1JX09QX1NUX0JVU1kpID09IFNQTUlfT1BfU1RfQlVTWSwNCj4gPiArICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgUE1JRl9ERUxBWV9VUywgUE1JRl9USU1FT1VUX1VT KTsNCj4gPiArICAgICAgIGlmIChyZXQgPCAwKQ0KPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJy KCZjdHJsLT5kZXYsICJ0aW1lb3V0LCBlcnIgPSAlZFxuIiwgcmV0KTsNCj4gPiArDQo+ID4gKyAg ICAgICByZXR1cm4gcmV0Ow0KPiA+ICt9DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50IHBtaWZfc3Bt aV9yZWFkX2NtZChzdHJ1Y3Qgc3BtaV9jb250cm9sbGVyICpjdHJsLCB1OCBvcGMsIHU4IHNpZCwN Cj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICB1MTYgYWRkciwgdTggKmJ1Ziwgc2l6 ZV90IGxlbikNCj4gPiArew0KPiA+ICsgICAgICAgc3RydWN0IHBtaWYgKmFyYiA9IHNwbWlfY29u dHJvbGxlcl9nZXRfZHJ2ZGF0YShjdHJsKTsNCj4gPiArICAgICAgIHN0cnVjdCBjaF9yZWcgKmlu Zl9yZWc7DQo+ID4gKyAgICAgICBpbnQgcmV0Ow0KPiA+ICsgICAgICAgdTMyIGRhdGEsIGNtZDsN Cj4gPiArDQo+ID4gKyAgICAgICAvKiBDaGVjayBmb3IgYXJndW1lbnQgdmFsaWRhdGlvbi4gKi8N Cj4gPiArICAgICAgIGlmIChzaWQgJiB+MHhmKSB7DQo+ID4gKyAgICAgICAgICAgICAgIGRldl9l cnIoJmN0cmwtPmRldiwgImV4Y2VlZCB0aGUgbWF4IHNsdiBpZFxuIik7DQo+ID4gKyAgICAgICAg ICAgICAgIHJldHVybiAtRUlOVkFMOw0KPiA+ICsgICAgICAgfQ0KPiA+ICsNCj4gPiArICAgICAg IGlmIChsZW4gPiA0KSB7DQo+ID4gKyAgICAgICAgICAgICAgIGRldl9lcnIoJmN0cmwtPmRldiwg InBtaWYgc3VwcG9ydHMgMS4uNCBieXRlcyBwZXIgdHJhbnMsIGJ1dDolenUgcmVxdWVzdGVkIiwg bGVuKTsNCj4gDQo+IE1pc3NpbmcgbmV3bGluZQ0KPiANCg0KVGhhbmtzLCBJIHdpbGwgdXBkYXRl IGl0IGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiAtRUlO VkFMOw0KPiA+ICsgICAgICAgfQ0KPiA+ICsNCj4gPiArICAgICAgIGlmIChvcGMgPj0gMHg2MCAm JiBvcGMgPD0gMHg3ZikNCj4gPiArICAgICAgICAgICAgICAgb3BjID0gUE1JRl9DTURfUkVHOw0K PiA+ICsgICAgICAgZWxzZSBpZiAoKG9wYyA+PSAweDIwICYmIG9wYyA8PSAweDJmKSB8fCAob3Bj ID49IDB4MzggJiYgb3BjIDw9IDB4M2YpKQ0KPiA+ICsgICAgICAgICAgICAgICBvcGMgPSBQTUlG X0NNRF9FWFRfUkVHX0xPTkc7DQo+ID4gKyAgICAgICBlbHNlDQo+ID4gKyAgICAgICAgICAgICAg IHJldHVybiAtRUlOVkFMOw0KPiA+ICsNCj4gPiArICAgICAgIC8qIFdhaXQgZm9yIFNvZnR3YXJl IEludGVyZmFjZSBGU00gc3RhdGUgdG8gYmUgSURMRS4gKi8NCj4gPiArICAgICAgIGluZl9yZWcg PSAmYXJiLT5jaGFuOw0KPiA+ICsgICAgICAgcmV0ID0gcmVhZGxfcG9sbF90aW1lb3V0X2F0b21p YyhhcmItPmJhc2UgKyBhcmItPmRhdGEtPnJlZ3NbaW5mX3JlZy0+Y2hfc3RhXSwNCj4gPiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZGF0YSwgR0VUX1NXSU5GKGRhdGEp ID09IFNXSU5GX0lETEUsDQo+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIFBNSUZfREVMQVlfVVMsIFBNSUZfVElNRU9VVF9VUyk7DQo+ID4gKyAgICAgICBpZiAocmV0 IDwgMCkgew0KPiA+ICsgICAgICAgICAgICAgICAvKiBzZXQgY2hhbm5lbCByZWFkeSBpZiB0aGUg ZGF0YSBoYXMgdHJhbnNmZXJyZWQgKi8NCj4gPiArICAgICAgICAgICAgICAgaWYgKHBtaWZfaXNf ZnNtX3ZsZGNscihhcmIpKQ0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgIHBtaWZfd3JpdGVs KGFyYiwgMSwgaW5mX3JlZy0+Y2hfcmR5KTsNCj4gPiArICAgICAgICAgICAgICAgZGV2X2Vycigm Y3RybC0+ZGV2LCAiZmFpbGVkIHRvIHdhaXQgZm9yIFNXSU5GX0lETEVcbiIpOw0KPiA+ICsgICAg ICAgICAgICAgICBnb3RvIG91dDsNCj4gPiArICAgICAgIH0NCj4gPiArDQo+ID4gKyAgICAgICAv KiBTZW5kIHRoZSBjb21tYW5kLiAqLw0KPiA+ICsgICAgICAgY21kID0gKG9wYyA8PCAzMCkgfCAo c2lkIDw8IDI0KSB8ICgobGVuIC0gMSkgPDwgMTYpIHwgYWRkcjsNCj4gPiArICAgICAgIHBtaWZf d3JpdGVsKGFyYiwgY21kLCBpbmZfcmVnLT5jaF9zZW5kKTsNCj4gPiArDQo+ID4gKyAgICAgICAv Kg0KPiA+ICsgICAgICAgICogV2FpdCBmb3IgU29mdHdhcmUgSW50ZXJmYWNlIEZTTSBzdGF0ZSB0 byBiZSBXRlZMRENMUiwNCj4gPiArICAgICAgICAqIHJlYWQgdGhlIGRhdGEgYW5kIGNsZWFyIHRo ZSB2YWxpZCBmbGFnLg0KPiA+ICsgICAgICAgICovDQo+ID4gKyAgICAgICByZXQgPSByZWFkbF9w b2xsX3RpbWVvdXRfYXRvbWljKGFyYi0+YmFzZSArIGFyYi0+ZGF0YS0+cmVnc1tpbmZfcmVnLT5j aF9zdGFdLA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBkYXRh LCBHRVRfU1dJTkYoZGF0YSkgPT0gU1dJTkZfV0ZWTERDTFIsDQo+ID4gKyAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIFBNSUZfREVMQVlfVVMsIFBNSUZfVElNRU9VVF9VUyk7 DQo+ID4gKyAgICAgICBpZiAocmV0IDwgMCkgew0KPiA+ICsgICAgICAgICAgICAgICBkZXZfZXJy KCZjdHJsLT5kZXYsICJmYWlsZWQgdG8gd2FpdCBmb3IgU1dJTkZfV0ZWTERDTFJcbiIpOw0KPiA+ ICsgICAgICAgICAgICAgICBnb3RvIG91dDsNCj4gPiArICAgICAgIH0NCj4gPiArDQo+ID4gKyAg ICAgICBkYXRhID0gcG1pZl9yZWFkbChhcmIsIGluZl9yZWctPnJkYXRhKTsNCj4gPiArICAgICAg IG1lbWNweShidWYsICZkYXRhLCBsZW4pOw0KPiA+ICsgICAgICAgcG1pZl93cml0ZWwoYXJiLCAx LCBpbmZfcmVnLT5jaF9yZHkpOw0KPiA+ICsNCj4gPiArb3V0Og0KPiA+ICsgICAgICAgaWYgKHJl dCA8IDApDQo+ID4gKyAgICAgICAgICAgICAgIHJldHVybiByZXQ7DQo+ID4gKw0KPiA+ICsgICAg ICAgcmV0dXJuIDA7DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBpbnQgcG1pZl9zcG1pX3dy aXRlX2NtZChzdHJ1Y3Qgc3BtaV9jb250cm9sbGVyICpjdHJsLCB1OCBvcGMsIHU4IHNpZCwNCj4g PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgdTE2IGFkZHIsIGNvbnN0IHU4ICpidWYs IHNpemVfdCBsZW4pDQo+ID4gK3sNCj4gPiArICAgICAgIHN0cnVjdCBwbWlmICphcmIgPSBzcG1p X2NvbnRyb2xsZXJfZ2V0X2RydmRhdGEoY3RybCk7DQo+ID4gKyAgICAgICBzdHJ1Y3QgY2hfcmVn ICppbmZfcmVnOw0KPiA+ICsgICAgICAgaW50IHJldDsNCj4gPiArICAgICAgIHUzMiBkYXRhLCBj bWQ7DQo+ID4gKw0KPiA+ICsgICAgICAgaWYgKGxlbiA+IDQpIHsNCj4gPiArICAgICAgICAgICAg ICAgZGV2X2VycigmY3RybC0+ZGV2LCAicG1pZiBzdXBwb3J0cyAxLi40IGJ5dGVzIHBlciB0cmFu cywgYnV0OiV6dSByZXF1ZXN0ZWQiLCBsZW4pOw0KPiANCj4gTWlzc2luZyBuZXdsaW5lDQo+IA0K DQpUaGFua3MsIEkgd2lsbCB1cGRhdGUgaXQgaW4gdGhlIG5leHQgcGF0Y2guDQoNCj4gPiArICAg ICAgICAgICAgICAgcmV0dXJuIC1FSU5WQUw7DQo+ID4gKyAgICAgICB9DQo+ID4gKw0KPiA+ICsg ICAgICAgLyogQ2hlY2sgdGhlIG9wY29kZSAqLw0KPiA+ICsgICAgICAgaWYgKG9wYyA+PSAweDQw ICYmIG9wYyA8PSAweDVGKQ0KPiA+ICsgICAgICAgICAgICAgICBvcGMgPSBQTUlGX0NNRF9SRUc7 DQo+ID4gKyAgICAgICBlbHNlIGlmICgob3BjIDw9IDB4RikgfHwgKG9wYyA+PSAweDMwICYmIG9w YyA8PSAweDM3KSkNCj4gPiArICAgICAgICAgICAgICAgb3BjID0gUE1JRl9DTURfRVhUX1JFR19M T05HOw0KPiA+ICsgICAgICAgZWxzZSBpZiAob3BjID49IDB4ODApDQo+ID4gKyAgICAgICAgICAg ICAgIG9wYyA9IFBNSUZfQ01EX1JFR18wOw0KPiA+ICsgICAgICAgZWxzZQ0KPiA+ICsgICAgICAg ICAgICAgICByZXR1cm4gLUVJTlZBTDsNCj4gPiArDQo+ID4gKyAgICAgICAvKiBXYWl0IGZvciBT b2Z0d2FyZSBJbnRlcmZhY2UgRlNNIHN0YXRlIHRvIGJlIElETEUuICovDQo+ID4gKyAgICAgICBp bmZfcmVnID0gJmFyYi0+Y2hhbjsNCj4gPiArICAgICAgIHJldCA9IHJlYWRsX3BvbGxfdGltZW91 dF9hdG9taWMoYXJiLT5iYXNlICsgYXJiLT5kYXRhLT5yZWdzW2luZl9yZWctPmNoX3N0YV0sDQo+ ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGRhdGEsIEdFVF9TV0lO RihkYXRhKSA9PSBTV0lORl9JRExFLA0KPiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICBQTUlGX0RFTEFZX1VTLCBQTUlGX1RJTUVPVVRfVVMpOw0KPiA+ICsgICAgICAg aWYgKHJldCA8IDApIHsNCj4gPiArICAgICAgICAgICAgICAgLyogc2V0IGNoYW5uZWwgcmVhZHkg aWYgdGhlIGRhdGEgaGFzIHRyYW5zZmVycmVkICovDQo+ID4gKyAgICAgICAgICAgICAgIGlmIChw bWlmX2lzX2ZzbV92bGRjbHIoYXJiKSkNCj4gPiArICAgICAgICAgICAgICAgICAgICAgICBwbWlm X3dyaXRlbChhcmIsIDEsIGluZl9yZWctPmNoX3JkeSk7DQo+ID4gKyAgICAgICAgICAgICAgIGRl dl9lcnIoJmN0cmwtPmRldiwgImZhaWxlZCB0byB3YWl0IGZvciBTV0lORl9JRExFXG4iKTsNCj4g PiArICAgICAgICAgICAgICAgZ290byBvdXQ7DQo+ID4gKyAgICAgICB9DQo+ID4gKw0KPiA+ICsg ICAgICAgLyogU2V0IHRoZSB3cml0ZSBkYXRhLiAqLw0KPiA+ICsgICAgICAgbWVtY3B5KCZkYXRh LCBidWYsIGxlbik7DQo+ID4gKyAgICAgICBwbWlmX3dyaXRlbChhcmIsIGRhdGEsIGluZl9yZWct PndkYXRhKTsNCj4gPiArDQo+ID4gKyAgICAgICAvKiBTZW5kIHRoZSBjb21tYW5kLiAqLw0KPiA+ ICsgICAgICAgY21kID0gKG9wYyA8PCAzMCkgfCBCSVQoMjkpIHwgKHNpZCA8PCAyNCkgfCAoKGxl biAtIDEpIDw8IDE2KSB8IGFkZHI7DQo+ID4gKyAgICAgICBwbWlmX3dyaXRlbChhcmIsIGNtZCwg aW5mX3JlZy0+Y2hfc2VuZCk7DQo+ID4gKw0KPiA+ICtvdXQ6DQo+ID4gKyAgICAgICBpZiAocmV0 IDwgMCkNCj4gPiArICAgICAgICAgICAgICAgcmV0dXJuIHJldDsNCj4gPiArDQo+ID4gKyAgICAg ICByZXR1cm4gMDsNCj4gDQo+IFNpbXBsaWZ5IHRvIA0KPiANCj4gCW91dDoNCj4gCQlyZXR1cm4g cmV0Ow0KPiANCg0KVGhhbmtzLCBJIHdpbGwgdXBkYXRlIGl0IGluIHRoZSBuZXh0IHBhdGNoLg0K DQo+ID4gK30NCj4gPiArDQo+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcG1pZl9kYXRhIG10Njg3 M19wbWlmX2FyYiA9IHsNCj4gPiArICAgICAgIC5yZWdzID0gbXQ2ODczX3JlZ3MsDQo+ID4gKyAg ICAgICAuc3BtaW1zdF9yZWdzID0gbXQ2ODczX3NwbWlfcmVncywNCj4gPiArICAgICAgIC5zb2Nf Y2hhbiA9IDIsDQo+ID4gK307DQo+ID4gKw0KPiA+ICtzdGF0aWMgaW50IG10a19zcG1pX3Byb2Jl KHN0cnVjdCBwbGF0Zm9ybV9kZXZpY2UgKnBkZXYpDQo+ID4gK3sNCj4gPiArICAgICAgIHN0cnVj dCBwbWlmICphcmI7DQo+ID4gKyAgICAgICBzdHJ1Y3Qgc3BtaV9jb250cm9sbGVyICpjdHJsOw0K PiA+ICsgICAgICAgaW50IGVyciwgaTsNCj4gPiArICAgICAgIHUzMiBjaGFuX29mZnNldDsNCj4g PiArDQo+ID4gKyAgICAgICBjdHJsID0gc3BtaV9jb250cm9sbGVyX2FsbG9jKCZwZGV2LT5kZXYs IHNpemVvZigqYXJiKSk7DQo+ID4gKyAgICAgICBpZiAoIWN0cmwpDQo+ID4gKyAgICAgICAgICAg ICAgIHJldHVybiAtRU5PTUVNOw0KPiA+ICsNCj4gPiArICAgICAgIGFyYiA9IHNwbWlfY29udHJv bGxlcl9nZXRfZHJ2ZGF0YShjdHJsKTsNCj4gPiArICAgICAgIGFyYi0+ZGF0YSA9IG9mX2Rldmlj ZV9nZXRfbWF0Y2hfZGF0YSgmcGRldi0+ZGV2KTsNCj4gDQo+IFVzZSBkZXZpY2VfZ2V0X21hdGNo X2RhdGEoKSBpbnN0ZWFkIHBsZWFzZS4NCj4gDQoNClRoYW5rcywgSSB3aWxsIGNoYW5nZSB0byB1 c2UgZGV2aWNlX2dldF9tYXRjaF9kYXRhIGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4gKyAgICAg ICBpZiAoIWFyYi0+ZGF0YSkgew0KPiA+ICsgICAgICAgICAgICAgICBlcnIgPSAtRUlOVkFMOw0K PiA+ICsgICAgICAgICAgICAgICBkZXZfZXJyKCZwZGV2LT5kZXYsICJDYW5ub3QgZ2V0IGRydl9k YXRhXG4iKTsNCj4gPiArICAgICAgICAgICAgICAgZ290byBlcnJfcHV0X2N0cmw7DQo+ID4gKyAg ICAgICB9DQo+ID4gKw0KPiA+ICsgICAgICAgYXJiLT5iYXNlID0gZGV2bV9wbGF0Zm9ybV9pb3Jl bWFwX3Jlc291cmNlX2J5bmFtZShwZGV2LCAicG1pZiIpOw0KPiA+ICsgICAgICAgaWYgKElTX0VS UihhcmItPmJhc2UpKSB7DQo+ID4gKyAgICAgICAgICAgICAgIGVyciA9IFBUUl9FUlIoYXJiLT5i YXNlKTsNCj4gPiArICAgICAgICAgICAgICAgZGV2X2VycigmcGRldi0+ZGV2LCAicG1pZiBmYWls ZWQgdG8gZ2V0IHRoZSByZW1hcHBwZWQgbWVtb3J5XG4iKTsNCj4gDQo+IFBsZWFzZSBkcm9wIHBy aW50IGFzIHRoZSBBUEkgYWxyZWFkeSBwcmludHMgZXJyb3JzIGZvciBldmVyeSBwcm9ibGVtLg0K PiANCg0KVGhhbmtzLCBJIHdpbGwgdXBkYXRlIGl0IGluIHRoZSBuZXh0IHBhdGNoLg0KDQo+ID4g KyAgICAgICAgICAgICAgIGdvdG8gZXJyX3B1dF9jdHJsOw0KPiA+ICsgICAgICAgfQ0KPiA+ICsN Cj4gPiArICAgICAgIGFyYi0+c3BtaW1zdF9iYXNlID0gZGV2bV9wbGF0Zm9ybV9pb3JlbWFwX3Jl c291cmNlX2J5bmFtZShwZGV2LCAic3BtaW1zdCIpOw0KPiA+ICsgICAgICAgaWYgKElTX0VSUihh cmItPnNwbWltc3RfYmFzZSkpIHsNCj4gPiArICAgICAgICAgICAgICAgZXJyID0gUFRSX0VSUihh cmItPnNwbWltc3RfYmFzZSk7DQo+ID4gKyAgICAgICAgICAgICAgIGRldl9lcnIoJnBkZXYtPmRl diwgInNwbWltc3QgZmFpbGVkIHRvIGdldCB0aGUgcmVtYXBwcGVkIG1lbW9yeVxuIik7DQo+IA0K PiBQbGVhc2UgZHJvcCBwcmludCBhcyB0aGUgQVBJIGFscmVhZHkgcHJpbnRzIGVycm9ycyBmb3Ig ZXZlcnkgcHJvYmxlbS4NCj4gDQoNClRoYW5rcywgSSB3aWxsIHVwZGF0ZSBpdCBpbiB0aGUgbmV4 dCBwYXRjaC4NCg0KPiA+ICsgICAgICAgICAgICAgICBnb3RvIGVycl9wdXRfY3RybDsNCj4gPiAr ICAgICAgIH0NCj4gPiArDQo+ID4gKyAgICAgICBhcmItPm5jbGtzID0gQVJSQVlfU0laRShwbWlm X2Nsb2NrX25hbWVzKTsNCj4gPiArICAgICAgIGlmIChhcmItPm5jbGtzID4gUE1JRl9NQVhfQ0xL Uykgew0KPiA+ICsgICAgICAgICAgICAgICBlcnIgPSAtRUlOVkFMOw0KPiA+ICsgICAgICAgICAg ICAgICBkZXZfZXJyKCZwZGV2LT5kZXYsICJleGNlZWQgdGhlIG1heCBjbG9jayBudW1iZXJzXG4i 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[172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 16 Aug 2021 20:11:38 +0800 Message-ID: <1629115898.29907.3.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] spmi: mediatek: Add support for MT6873/8192 From: Hsin-hsiung Wang To: Stephen Boyd CC: Matthias Brugger , Rob Herring , , , , , , Date: Mon, 16 Aug 2021 20:11:38 +0800 In-Reply-To: <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> References: <1627972461-2627-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1627972461-2627-4-git-send-email-hsin-hsiung.wang@mediatek.com> <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210816_051151_373279_09C1F510 X-CRM114-Status: GOOD ( 30.79 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi, On Mon, 2021-08-09 at 10:55 -0700, Stephen Boyd wrote: > Quoting Hsin-Hsiung Wang (2021-08-02 23:34:19) > > diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c > > new file mode 100644 > > index 000000000000..94c45d46ab0c > > --- /dev/null > > +++ b/drivers/spmi/spmi-mtk-pmif.c > > @@ -0,0 +1,465 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2021 MediaTek Inc. > > + > > +#include > > +#include > > +#include > > +#include > > include platform_device.h for the platform device driver that this is. > Thanks for the commit, I will update it in the next patch. > > +#include > > + > > +#define SWINF_IDLE 0x00 > > +#define SWINF_WFVLDCLR 0x06 > > + > > +#define GET_SWINF(x) (((x) >> 1) & 0x7) > > + > > +#define PMIF_CMD_REG_0 0 > > +#define PMIF_CMD_REG 1 > > +#define PMIF_CMD_EXT_REG 2 > > +#define PMIF_CMD_EXT_REG_LONG 3 > > + > > +#define PMIF_DELAY_US 10 > > +#define PMIF_TIMEOUT_US (10 * 1000) > > + > > +#define PMIF_CHAN_OFFSET 0x5 > > + > > +#define PMIF_MAX_CLKS 3 > > + > > +#define SPMI_OP_ST_BUSY 1 > > + > > +struct ch_reg { > > + u32 ch_sta; > > + u32 wdata; > > + u32 rdata; > > + u32 ch_send; > > + u32 ch_rdy; > > +}; > > + > > +struct pmif_data { > > + const u32 *regs; > > + const u32 *spmimst_regs; > > + u32 soc_chan; > > +}; > > + > > +struct pmif { > > + void __iomem *base; > > + void __iomem *spmimst_base; > > + struct ch_reg chan; > > + struct clk_bulk_data clks[PMIF_MAX_CLKS]; > > + u32 nclks; > > size_t? Surely 32-bits isn't important. > Thanks. I will use size_t in the next patch. > > + const struct pmif_data *data; > > +}; > > + > > +static const char * const pmif_clock_names[] = { > > + "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux", > > +}; > [...] > > + > > +static bool pmif_is_fsm_vldclr(struct pmif *arb) > > +{ > > + u32 reg_rdata; > > + > > + reg_rdata = pmif_readl(arb, arb->chan.ch_sta); > > Newline here please. > Thanks, I will update it in the next patch. > > + return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR; > > +} > > + > > +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + u32 rdata, cmd; > > + int ret; > > + > > + /* Check the opcode */ > > + if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) > > + return -EINVAL; > > + > > + cmd = opc - SPMI_CMD_RESET; > > + > > + mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); > > + ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA], > > + rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) > > + dev_err(&ctrl->dev, "timeout, err = %d\n", ret); > > + > > + return ret; > > +} > > + > > +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, > > + u16 addr, u8 *buf, size_t len) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + struct ch_reg *inf_reg; > > + int ret; > > + u32 data, cmd; > > + > > + /* Check for argument validation. */ > > + if (sid & ~0xf) { > > + dev_err(&ctrl->dev, "exceed the max slv id\n"); > > + return -EINVAL; > > + } > > + > > + if (len > 4) { > > + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); > > Missing newline > Thanks, I will update it in the next patch. > > + return -EINVAL; > > + } > > + > > + if (opc >= 0x60 && opc <= 0x7f) > > + opc = PMIF_CMD_REG; > > + else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f)) > > + opc = PMIF_CMD_EXT_REG_LONG; > > + else > > + return -EINVAL; > > + > > + /* Wait for Software Interface FSM state to be IDLE. */ > > + inf_reg = &arb->chan; > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_IDLE, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + /* set channel ready if the data has transferred */ > > + if (pmif_is_fsm_vldclr(arb)) > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); > > + goto out; > > + } > > + > > + /* Send the command. */ > > + cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; > > + pmif_writel(arb, cmd, inf_reg->ch_send); > > + > > + /* > > + * Wait for Software Interface FSM state to be WFVLDCLR, > > + * read the data and clear the valid flag. > > + */ > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_WFVLDCLR, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n"); > > + goto out; > > + } > > + > > + data = pmif_readl(arb, inf_reg->rdata); > > + memcpy(buf, &data, len); > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + > > +out: > > + if (ret < 0) > > + return ret; > > + > > + return 0; > > +} > > + > > +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, > > + u16 addr, const u8 *buf, size_t len) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + struct ch_reg *inf_reg; > > + int ret; > > + u32 data, cmd; > > + > > + if (len > 4) { > > + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); > > Missing newline > Thanks, I will update it in the next patch. > > + return -EINVAL; > > + } > > + > > + /* Check the opcode */ > > + if (opc >= 0x40 && opc <= 0x5F) > > + opc = PMIF_CMD_REG; > > + else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37)) > > + opc = PMIF_CMD_EXT_REG_LONG; > > + else if (opc >= 0x80) > > + opc = PMIF_CMD_REG_0; > > + else > > + return -EINVAL; > > + > > + /* Wait for Software Interface FSM state to be IDLE. */ > > + inf_reg = &arb->chan; > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_IDLE, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + /* set channel ready if the data has transferred */ > > + if (pmif_is_fsm_vldclr(arb)) > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); > > + goto out; > > + } > > + > > + /* Set the write data. */ > > + memcpy(&data, buf, len); > > + pmif_writel(arb, data, inf_reg->wdata); > > + > > + /* Send the command. */ > > + cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; > > + pmif_writel(arb, cmd, inf_reg->ch_send); > > + > > +out: > > + if (ret < 0) > > + return ret; > > + > > + return 0; > > Simplify to > > out: > return ret; > Thanks, I will update it in the next patch. > > +} > > + > > +static const struct pmif_data mt6873_pmif_arb = { > > + .regs = mt6873_regs, > > + .spmimst_regs = mt6873_spmi_regs, > > + .soc_chan = 2, > > +}; > > + > > +static int mtk_spmi_probe(struct platform_device *pdev) > > +{ > > + struct pmif *arb; > > + struct spmi_controller *ctrl; > > + int err, i; > > + u32 chan_offset; > > + > > + ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb)); > > + if (!ctrl) > > + return -ENOMEM; > > + > > + arb = spmi_controller_get_drvdata(ctrl); > > + arb->data = of_device_get_match_data(&pdev->dev); > > Use device_get_match_data() instead please. > Thanks, I will change to use device_get_match_data in the next patch. > > + if (!arb->data) { > > + err = -EINVAL; > > + dev_err(&pdev->dev, "Cannot get drv_data\n"); > > + goto err_put_ctrl; > > + } > > + > > + arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif"); > > + if (IS_ERR(arb->base)) { > > + err = PTR_ERR(arb->base); > > + dev_err(&pdev->dev, "pmif failed to get the remappped memory\n"); > > Please drop print as the API already prints errors for every problem. > Thanks, I will update it in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst"); > > + if (IS_ERR(arb->spmimst_base)) { > > + err = PTR_ERR(arb->spmimst_base); > > + dev_err(&pdev->dev, "spmimst failed to get the remappped memory\n"); > > Please drop print as the API already prints errors for every problem. > Thanks, I will update it in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + arb->nclks = ARRAY_SIZE(pmif_clock_names); > > + if (arb->nclks > PMIF_MAX_CLKS) { > > + err = -EINVAL; > > + dev_err(&pdev->dev, "exceed the max clock numbers\n"); > > Do we really care? The dt schema should be checking this instead of the > driver. > Thanks, I will remove the check in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + for (i = 0; i < arb->nclks; i++) > > + arb->clks[i].id = pmif_clock_names[i]; > > + _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 548D3C4338F for ; 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Mon, 16 Aug 2021 20:11:38 +0800 Message-ID: <1629115898.29907.3.camel@mtksdaap41> Subject: Re: [PATCH v10 3/5] spmi: mediatek: Add support for MT6873/8192 From: Hsin-hsiung Wang To: Stephen Boyd CC: Matthias Brugger , Rob Herring , , , , , , Date: Mon, 16 Aug 2021 20:11:38 +0800 In-Reply-To: <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> References: <1627972461-2627-1-git-send-email-hsin-hsiung.wang@mediatek.com> <1627972461-2627-4-git-send-email-hsin-hsiung.wang@mediatek.com> <162853170949.1975443.12492156194100139076@swboyd.mtv.corp.google.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210816_051151_373279_09C1F510 X-CRM114-Status: GOOD ( 30.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Mon, 2021-08-09 at 10:55 -0700, Stephen Boyd wrote: > Quoting Hsin-Hsiung Wang (2021-08-02 23:34:19) > > diff --git a/drivers/spmi/spmi-mtk-pmif.c b/drivers/spmi/spmi-mtk-pmif.c > > new file mode 100644 > > index 000000000000..94c45d46ab0c > > --- /dev/null > > +++ b/drivers/spmi/spmi-mtk-pmif.c > > @@ -0,0 +1,465 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// Copyright (c) 2021 MediaTek Inc. > > + > > +#include > > +#include > > +#include > > +#include > > include platform_device.h for the platform device driver that this is. > Thanks for the commit, I will update it in the next patch. > > +#include > > + > > +#define SWINF_IDLE 0x00 > > +#define SWINF_WFVLDCLR 0x06 > > + > > +#define GET_SWINF(x) (((x) >> 1) & 0x7) > > + > > +#define PMIF_CMD_REG_0 0 > > +#define PMIF_CMD_REG 1 > > +#define PMIF_CMD_EXT_REG 2 > > +#define PMIF_CMD_EXT_REG_LONG 3 > > + > > +#define PMIF_DELAY_US 10 > > +#define PMIF_TIMEOUT_US (10 * 1000) > > + > > +#define PMIF_CHAN_OFFSET 0x5 > > + > > +#define PMIF_MAX_CLKS 3 > > + > > +#define SPMI_OP_ST_BUSY 1 > > + > > +struct ch_reg { > > + u32 ch_sta; > > + u32 wdata; > > + u32 rdata; > > + u32 ch_send; > > + u32 ch_rdy; > > +}; > > + > > +struct pmif_data { > > + const u32 *regs; > > + const u32 *spmimst_regs; > > + u32 soc_chan; > > +}; > > + > > +struct pmif { > > + void __iomem *base; > > + void __iomem *spmimst_base; > > + struct ch_reg chan; > > + struct clk_bulk_data clks[PMIF_MAX_CLKS]; > > + u32 nclks; > > size_t? Surely 32-bits isn't important. > Thanks. I will use size_t in the next patch. > > + const struct pmif_data *data; > > +}; > > + > > +static const char * const pmif_clock_names[] = { > > + "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux", > > +}; > [...] > > + > > +static bool pmif_is_fsm_vldclr(struct pmif *arb) > > +{ > > + u32 reg_rdata; > > + > > + reg_rdata = pmif_readl(arb, arb->chan.ch_sta); > > Newline here please. > Thanks, I will update it in the next patch. > > + return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR; > > +} > > + > > +static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + u32 rdata, cmd; > > + int ret; > > + > > + /* Check the opcode */ > > + if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) > > + return -EINVAL; > > + > > + cmd = opc - SPMI_CMD_RESET; > > + > > + mtk_spmi_writel(arb, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); > > + ret = readl_poll_timeout_atomic(arb->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA], > > + rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) > > + dev_err(&ctrl->dev, "timeout, err = %d\n", ret); > > + > > + return ret; > > +} > > + > > +static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, > > + u16 addr, u8 *buf, size_t len) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + struct ch_reg *inf_reg; > > + int ret; > > + u32 data, cmd; > > + > > + /* Check for argument validation. */ > > + if (sid & ~0xf) { > > + dev_err(&ctrl->dev, "exceed the max slv id\n"); > > + return -EINVAL; > > + } > > + > > + if (len > 4) { > > + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); > > Missing newline > Thanks, I will update it in the next patch. > > + return -EINVAL; > > + } > > + > > + if (opc >= 0x60 && opc <= 0x7f) > > + opc = PMIF_CMD_REG; > > + else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f)) > > + opc = PMIF_CMD_EXT_REG_LONG; > > + else > > + return -EINVAL; > > + > > + /* Wait for Software Interface FSM state to be IDLE. */ > > + inf_reg = &arb->chan; > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_IDLE, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + /* set channel ready if the data has transferred */ > > + if (pmif_is_fsm_vldclr(arb)) > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); > > + goto out; > > + } > > + > > + /* Send the command. */ > > + cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; > > + pmif_writel(arb, cmd, inf_reg->ch_send); > > + > > + /* > > + * Wait for Software Interface FSM state to be WFVLDCLR, > > + * read the data and clear the valid flag. > > + */ > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_WFVLDCLR, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n"); > > + goto out; > > + } > > + > > + data = pmif_readl(arb, inf_reg->rdata); > > + memcpy(buf, &data, len); > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + > > +out: > > + if (ret < 0) > > + return ret; > > + > > + return 0; > > +} > > + > > +static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, > > + u16 addr, const u8 *buf, size_t len) > > +{ > > + struct pmif *arb = spmi_controller_get_drvdata(ctrl); > > + struct ch_reg *inf_reg; > > + int ret; > > + u32 data, cmd; > > + > > + if (len > 4) { > > + dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); > > Missing newline > Thanks, I will update it in the next patch. > > + return -EINVAL; > > + } > > + > > + /* Check the opcode */ > > + if (opc >= 0x40 && opc <= 0x5F) > > + opc = PMIF_CMD_REG; > > + else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37)) > > + opc = PMIF_CMD_EXT_REG_LONG; > > + else if (opc >= 0x80) > > + opc = PMIF_CMD_REG_0; > > + else > > + return -EINVAL; > > + > > + /* Wait for Software Interface FSM state to be IDLE. */ > > + inf_reg = &arb->chan; > > + ret = readl_poll_timeout_atomic(arb->base + arb->data->regs[inf_reg->ch_sta], > > + data, GET_SWINF(data) == SWINF_IDLE, > > + PMIF_DELAY_US, PMIF_TIMEOUT_US); > > + if (ret < 0) { > > + /* set channel ready if the data has transferred */ > > + if (pmif_is_fsm_vldclr(arb)) > > + pmif_writel(arb, 1, inf_reg->ch_rdy); > > + dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); > > + goto out; > > + } > > + > > + /* Set the write data. */ > > + memcpy(&data, buf, len); > > + pmif_writel(arb, data, inf_reg->wdata); > > + > > + /* Send the command. */ > > + cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; > > + pmif_writel(arb, cmd, inf_reg->ch_send); > > + > > +out: > > + if (ret < 0) > > + return ret; > > + > > + return 0; > > Simplify to > > out: > return ret; > Thanks, I will update it in the next patch. > > +} > > + > > +static const struct pmif_data mt6873_pmif_arb = { > > + .regs = mt6873_regs, > > + .spmimst_regs = mt6873_spmi_regs, > > + .soc_chan = 2, > > +}; > > + > > +static int mtk_spmi_probe(struct platform_device *pdev) > > +{ > > + struct pmif *arb; > > + struct spmi_controller *ctrl; > > + int err, i; > > + u32 chan_offset; > > + > > + ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb)); > > + if (!ctrl) > > + return -ENOMEM; > > + > > + arb = spmi_controller_get_drvdata(ctrl); > > + arb->data = of_device_get_match_data(&pdev->dev); > > Use device_get_match_data() instead please. > Thanks, I will change to use device_get_match_data in the next patch. > > + if (!arb->data) { > > + err = -EINVAL; > > + dev_err(&pdev->dev, "Cannot get drv_data\n"); > > + goto err_put_ctrl; > > + } > > + > > + arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif"); > > + if (IS_ERR(arb->base)) { > > + err = PTR_ERR(arb->base); > > + dev_err(&pdev->dev, "pmif failed to get the remappped memory\n"); > > Please drop print as the API already prints errors for every problem. > Thanks, I will update it in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst"); > > + if (IS_ERR(arb->spmimst_base)) { > > + err = PTR_ERR(arb->spmimst_base); > > + dev_err(&pdev->dev, "spmimst failed to get the remappped memory\n"); > > Please drop print as the API already prints errors for every problem. > Thanks, I will update it in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + arb->nclks = ARRAY_SIZE(pmif_clock_names); > > + if (arb->nclks > PMIF_MAX_CLKS) { > > + err = -EINVAL; > > + dev_err(&pdev->dev, "exceed the max clock numbers\n"); > > Do we really care? The dt schema should be checking this instead of the > driver. > Thanks, I will remove the check in the next patch. > > + goto err_put_ctrl; > > + } > > + > > + for (i = 0; i < arb->nclks; i++) > > + arb->clks[i].id = pmif_clock_names[i]; > > + _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel