[Intel-gfx] [PATCH 00/21] i915/display: split and constify vtable

[Intel-gfx] [PATCH 00/21] i915/display: split and constify vtable

[Dave Airlie]

This is orthogonal to my display ptr refactoring and should probably
be applied first.

The display funcs vtable was a bit of mess, lots of intermixing of
internal display functionality and interfaces to watermarks/irqs.

It's also considered not great security practice to leave writeable
function pointers around for exploits to get into.

This series attempts to address both problems, first there are a
few cleanups, then it splits the function table into multiple pieces.
Some of the splits might be bikesheds but I think we should apply first
and merge things later if there is good reason.

The second half converts all the vtables to static const structs,
I've used macros in some of them to make it less messy, the cdclk
one is probably the worst one.

Dave.

[Intel-gfx] [PATCH 01/21] drm/i915/pm: drop get_fifo_size vfunc.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.

Signed-off-by: Dave Airlie <airlied@redhat.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  2 --
 drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index be2392bbcecc..6511ec674c23 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
 			  const struct intel_cdclk_config *cdclk_config,
 			  enum pipe pipe);
 	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
-	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
-			     enum i9xx_plane_id i9xx_plane);
 	int (*compute_pipe_wm)(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc);
 	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..d9993eb3730d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	else
 		wm_info = &i830_a_wm_info;
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+	if (DISPLAY_VER(dev_priv) == 2)
+		fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+	else
+		fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 	if (DISPLAY_VER(dev_priv) == 2)
 		wm_info = &i830_bc_wm_info;
 
-	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+	if (DISPLAY_VER(dev_priv) == 2)
+		fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+	else
+		fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
 	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
 	if (intel_crtc_active(crtc)) {
 		const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
 	pipe_mode = &crtc->config->hw.pipe_mode;
 	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
 				       &i845_wm_info,
-				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+				       i845_get_fifo_size(dev_priv, PLANE_A),
 				       4, pessimal_latency_ns);
 	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
 	fwater_lo |= (3<<8) | planea_wm;
@@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		dev_priv->display.update_wm = i965_update_wm;
 	} else if (DISPLAY_VER(dev_priv) == 3) {
 		dev_priv->display.update_wm = i9xx_update_wm;
-		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
 	} else if (DISPLAY_VER(dev_priv) == 2) {
-		if (INTEL_NUM_PIPES(dev_priv) == 1) {
+		if (INTEL_NUM_PIPES(dev_priv) == 1)
 			dev_priv->display.update_wm = i845_update_wm;
-			dev_priv->display.get_fifo_size = i845_get_fifo_size;
-		} else {
+		else
 			dev_priv->display.update_wm = i9xx_update_wm;
-			dev_priv->display.get_fifo_size = i830_get_fifo_size;
-		}
 	} else {
 		drm_err(&dev_priv->drm,
 			"unexpected fall-through in %s\n", __func__);
-- 
2.31.1

[Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

The crtc was never being used here.
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 drivers/gpu/drm/i915/intel_pm.c              | 18 ++++++------------
 drivers/gpu/drm/i915/intel_pm.h              |  2 +-
 4 files changed, 13 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1f447ba776c7..d95283bf2631 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2373,7 +2373,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 
 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
-		intel_update_watermarks(crtc);
+		intel_update_watermarks(dev_priv);
 
 	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
 		hsw_enable_ips(new_crtc_state);
@@ -2529,7 +2529,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		if (dev_priv->display.initial_watermarks)
 			dev_priv->display.initial_watermarks(state, crtc);
 		else if (new_crtc_state->update_wm_pre)
-			intel_update_watermarks(crtc);
+			intel_update_watermarks(dev_priv);
 	}
 
 	/*
@@ -3576,7 +3576,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	if (dev_priv->display.initial_watermarks)
 		dev_priv->display.initial_watermarks(state, crtc);
 	else
-		intel_update_watermarks(crtc);
+		intel_update_watermarks(dev_priv);
 	intel_enable_pipe(new_crtc_state);
 
 	intel_crtc_vblank_on(new_crtc_state);
@@ -3643,7 +3643,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
 	if (!dev_priv->display.initial_watermarks)
-		intel_update_watermarks(crtc);
+		intel_update_watermarks(dev_priv);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
 	if (IS_I830(dev_priv))
@@ -3719,7 +3719,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 		encoder->base.crtc = NULL;
 
 	intel_fbc_disable(crtc);
-	intel_update_watermarks(crtc);
+	intel_update_watermarks(dev_priv);
 	intel_disable_shared_dpll(crtc_state);
 
 	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6511ec674c23..ef903d70ab0b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
 	void (*optimize_watermarks)(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc);
 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
-	void (*update_wm)(struct intel_crtc *crtc);
+	void (*update_wm)(struct drm_i915_private *dev_priv);
 	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
 	/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9993eb3730d..406baa49e6ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
 	return enabled;
 }
 
-static void pnv_update_wm(struct intel_crtc *unused_crtc)
+static void pnv_update_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	struct intel_crtc *crtc;
 	const struct cxsr_latency *latency;
 	u32 reg;
@@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
 
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static void i965_update_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	struct intel_crtc *crtc;
 	int srwm = 1;
 	int cursor_sr = 16;
@@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
 
 #undef FW_WM
 
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static void i9xx_update_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	const struct intel_watermark_params *wm_info;
 	u32 fwater_lo;
 	u32 fwater_hi;
@@ -2481,9 +2478,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
 		intel_set_memory_cxsr(dev_priv, true);
 }
 
-static void i845_update_wm(struct intel_crtc *unused_crtc)
+static void i845_update_wm(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
 	struct intel_crtc *crtc;
 	const struct drm_display_mode *pipe_mode;
 	u32 fwater_lo;
@@ -7169,12 +7165,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
  * We don't use the sprite, so we can ignore that.  And on Crestline we have
  * to set the non-SR watermarks to 8.
  */
-void intel_update_watermarks(struct intel_crtc *crtc)
+void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
 	if (dev_priv->display.update_wm)
-		dev_priv->display.update_wm(crtc);
+		dev_priv->display.update_wm(dev_priv);
 }
 
 void intel_enable_ipc(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 941b3ae555c8..99bce0b4f5fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -29,7 +29,7 @@ struct skl_wm_level;
 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_i915_private *dev_priv);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct intel_crtc *crtc);
+void intel_update_watermarks(struct drm_i915_private *dev_priv);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
-- 
2.31.1

[Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

A vague goal is to have the vfunc table be the api between
wm and display, not having direction function calls cross
the boundary.

This aligns the legacy update_wm with the newer vfuncs.

The comment probably needs to live somewhere else, it seems
like it should live in the pm side though not the display side,
but I brought it along for the ride.
---
 drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c              | 39 -------------------
 drivers/gpu/drm/i915/intel_pm.h              |  1 -
 3 files changed, 40 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d95283bf2631..b495371c1889 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -125,6 +125,46 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
 static void intel_modeset_setup_hw_state(struct drm_device *dev,
 					 struct drm_modeset_acquire_ctx *ctx);
 
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current modes
+ * @crtc: the #intel_crtc on which to compute the WM
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ *   - normal (i.e. non-self-refresh)
+ *   - self-refresh (SR) mode
+ *   - lines are large relative to FIFO size (buffer can hold up to 2)
+ *   - lines are small relative to FIFO size (buffer can hold more than 2
+ *     lines), so need to account for TLB latency
+ *
+ *   The normal calculation is:
+ *     watermark = dotclock * bytes per pixel * latency
+ *   where latency is platform & configuration dependent (we assume pessimal
+ *   values here).
+ *
+ *   The SR calculation is:
+ *     watermark = (trunc(latency/line time)+1) * surface width *
+ *       bytes per pixel
+ *   where
+ *     line time = htotal / dotclock
+ *     surface width = hdisplay for normal plane and 64 for cursor
+ *   and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that.  And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+	if (dev_priv->display.update_wm)
+		dev_priv->display.update_wm(dev_priv);
+}
+
 /* returns HPLL frequency in kHz */
 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 406baa49e6ad..4054c6f7a2f9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7132,45 +7132,6 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
-/**
- * intel_update_watermarks - update FIFO watermark values based on current modes
- * @crtc: the #intel_crtc on which to compute the WM
- *
- * Calculate watermark values for the various WM regs based on current mode
- * and plane configuration.
- *
- * There are several cases to deal with here:
- *   - normal (i.e. non-self-refresh)
- *   - self-refresh (SR) mode
- *   - lines are large relative to FIFO size (buffer can hold up to 2)
- *   - lines are small relative to FIFO size (buffer can hold more than 2
- *     lines), so need to account for TLB latency
- *
- *   The normal calculation is:
- *     watermark = dotclock * bytes per pixel * latency
- *   where latency is platform & configuration dependent (we assume pessimal
- *   values here).
- *
- *   The SR calculation is:
- *     watermark = (trunc(latency/line time)+1) * surface width *
- *       bytes per pixel
- *   where
- *     line time = htotal / dotclock
- *     surface width = hdisplay for normal plane and 64 for cursor
- *   and latency is assumed to be high, as above.
- *
- * The final value programmed to the register should always be rounded up,
- * and include an extra 2 entries to account for clock crossings.
- *
- * We don't use the sprite, so we can ignore that.  And on Crestline we have
- * to set the non-SR watermarks to 8.
- */
-void intel_update_watermarks(struct drm_i915_private *dev_priv)
-{
-	if (dev_priv->display.update_wm)
-		dev_priv->display.update_wm(dev_priv);
-}
-
 void intel_enable_ipc(struct drm_i915_private *dev_priv)
 {
 	u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 99bce0b4f5fb..990cdcaf85ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -29,7 +29,6 @@ struct skl_wm_level;
 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
 void intel_suspend_hw(struct drm_i915_private *dev_priv);
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
-void intel_update_watermarks(struct drm_i915_private *dev_priv);
 void intel_init_pm(struct drm_i915_private *dev_priv);
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
 void intel_pm_setup(struct drm_i915_private *dev_priv);
-- 
2.31.1

[Intel-gfx] [PATCH 04/21] drm/i915: split clock gating init from display vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

This function is only used inside intel_pm.c
---
 drivers/gpu/drm/i915/i915_drv.h |  9 ++++++-
 drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++++++++++-----------------
 2 files changed, 32 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef903d70ab0b..b93fa19892b5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
 struct intel_limit;
 struct dpll;
 
+/* functions used internal in intel_pm.c */
+struct drm_i915_cg_funcs {
+	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
 struct drm_i915_display_funcs {
 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
 				    const struct drm_connector_state *old_conn_state);
 	void (*fdi_link_train)(struct intel_crtc *crtc,
 			       const struct intel_crtc_state *crtc_state);
-	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 	/* clock updates for mode set */
 	/* cursor updates */
@@ -969,6 +973,9 @@ struct drm_i915_private {
 	/* unbound hipri wq for page flips/plane updates */
 	struct workqueue_struct *flip_wq;
 
+	/* pm private clock gating functions */
+	struct drm_i915_cg_funcs cg_funcs;
+
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..73549e774881 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	dev_priv->display.init_clock_gating(dev_priv);
+	dev_priv->cg_funcs.init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ALDERLAKE_P(dev_priv))
-		dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
 	else if (IS_DG1(dev_priv))
-		dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 12)
-		dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 11)
-		dev_priv->display.init_clock_gating = icl_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
 	else if (IS_SKYLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = skl_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
 	else if (IS_KABYLAKE(dev_priv))
-		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
 	else if (IS_BROXTON(dev_priv))
-		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
 	else if (IS_GEMINILAKE(dev_priv))
-		dev_priv->display.init_clock_gating = glk_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
 	else if (IS_BROADWELL(dev_priv))
-		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->display.init_clock_gating = chv_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
 	else if (IS_HASWELL(dev_priv))
-		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
 	else if (IS_IVYBRIDGE(dev_priv))
-		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 6)
-		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 5)
-		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
 	else if (IS_G4X(dev_priv))
-		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
 	else if (IS_I965GM(dev_priv))
-		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
 	else if (IS_I965G(dev_priv))
-		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 3)
-		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
 	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
 	else if (GRAPHICS_VER(dev_priv) == 2)
-		dev_priv->display.init_clock_gating = i830_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
 	else {
 		MISSING_CASE(INTEL_DEVID(dev_priv));
-		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
 	}
 }
 
-- 
2.31.1

[Intel-gfx] [PATCH 05/21] drm/i915: split watermark vfuncs from display vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

These are the watermark api between display and pm.
---
 drivers/gpu/drm/i915/display/intel_display.c | 54 ++++++++++----------
 drivers/gpu/drm/i915/i915_drv.h              | 24 ++++++---
 drivers/gpu/drm/i915/intel_pm.c              | 40 +++++++--------
 3 files changed, 63 insertions(+), 55 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b495371c1889..b1202ede3fb0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
  */
 static void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-	if (dev_priv->display.update_wm)
-		dev_priv->display.update_wm(dev_priv);
+	if (dev_priv->wm_disp.update_wm)
+		dev_priv->wm_disp.update_wm(dev_priv);
 }
 
 /* returns HPLL frequency in kHz */
@@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		 * we'll continue to update watermarks the old way, if flags tell
 		 * us to.
 		 */
-		if (dev_priv->display.initial_watermarks)
-			dev_priv->display.initial_watermarks(state, crtc);
+		if (dev_priv->wm_disp.initial_watermarks)
+			dev_priv->wm_disp.initial_watermarks(state, crtc);
 		else if (new_crtc_state->update_wm_pre)
 			intel_update_watermarks(dev_priv);
 	}
@@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp.initial_watermarks)
+		dev_priv->wm_disp.initial_watermarks(state, crtc);
 	intel_enable_pipe(new_crtc_state);
 
 	if (new_crtc_state->has_pch_encoder)
@@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(dev_priv) >= 11)
 		icl_set_pipe_chicken(new_crtc_state);
 
-	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp.initial_watermarks)
+		dev_priv->wm_disp.initial_watermarks(state, crtc);
 
 	if (DISPLAY_VER(dev_priv) >= 11) {
 		const struct intel_dbuf_state *dbuf_state =
@@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	dev_priv->display.initial_watermarks(state, crtc);
+	dev_priv->wm_disp.initial_watermarks(state, crtc);
 	intel_enable_pipe(new_crtc_state);
 
 	intel_crtc_vblank_on(new_crtc_state);
@@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	if (dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp.initial_watermarks)
+		dev_priv->wm_disp.initial_watermarks(state, crtc);
 	else
 		intel_update_watermarks(dev_priv);
 	intel_enable_pipe(new_crtc_state);
@@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(dev_priv) != 2)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (!dev_priv->display.initial_watermarks)
+	if (!dev_priv->wm_disp.initial_watermarks)
 		intel_update_watermarks(dev_priv);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
@@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 			return ret;
 	}
 
-	if (dev_priv->display.compute_pipe_wm) {
-		ret = dev_priv->display.compute_pipe_wm(state, crtc);
+	if (dev_priv->wm_disp.compute_pipe_wm) {
+		ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
 		if (ret) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Target pipe watermarks are invalid\n");
@@ -6800,9 +6800,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 
 	}
 
-	if (dev_priv->display.compute_intermediate_wm) {
+	if (dev_priv->wm_disp.compute_intermediate_wm) {
 		if (drm_WARN_ON(&dev_priv->drm,
-				!dev_priv->display.compute_pipe_wm))
+				!dev_priv->wm_disp.compute_pipe_wm))
 			return 0;
 
 		/*
@@ -6810,7 +6810,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		 * old state and the new state.  We can program these
 		 * immediately.
 		 */
-		ret = dev_priv->display.compute_intermediate_wm(state, crtc);
+		ret = dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
 		if (ret) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "No valid intermediate pipe watermarks are possible\n");
@@ -8919,8 +8919,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/* Is there platform-specific watermark information to calculate? */
-	if (dev_priv->display.compute_global_watermarks)
-		return dev_priv->display.compute_global_watermarks(state);
+	if (dev_priv->wm_disp.compute_global_watermarks)
+		return dev_priv->wm_disp.compute_global_watermarks(state);
 
 	return 0;
 }
@@ -9745,8 +9745,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
 	}
 
-	if (dev_priv->display.atomic_update_watermarks)
-		dev_priv->display.atomic_update_watermarks(state, crtc);
+	if (dev_priv->wm_disp.atomic_update_watermarks)
+		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
 }
 
 static void commit_pipe_post_planes(struct intel_atomic_state *state,
@@ -9874,8 +9874,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	/* FIXME unify this for all platforms */
 	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
-	    dev_priv->display.initial_watermarks)
-		dev_priv->display.initial_watermarks(state, crtc);
+	    dev_priv->wm_disp.initial_watermarks)
+		dev_priv->wm_disp.initial_watermarks(state, crtc);
 }
 
 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -10297,8 +10297,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
 
-		if (dev_priv->display.optimize_watermarks)
-			dev_priv->display.optimize_watermarks(state, crtc);
+		if (dev_priv->wm_disp.optimize_watermarks)
+			dev_priv->wm_disp.optimize_watermarks(state, crtc);
 	}
 
 	intel_dbuf_post_plane_update(state);
@@ -11366,7 +11366,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
 	int i;
 
 	/* Only supported on platforms that use atomic watermark design */
-	if (!dev_priv->display.optimize_watermarks)
+	if (!dev_priv->wm_disp.optimize_watermarks)
 		return;
 
 	state = drm_atomic_state_alloc(&dev_priv->drm);
@@ -11399,7 +11399,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
 	/* Write calculated watermark values back */
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
 		crtc_state->wm.need_postvbl_update = true;
-		dev_priv->display.optimize_watermarks(intel_state, crtc);
+		dev_priv->wm_disp.optimize_watermarks(intel_state, crtc);
 
 		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b93fa19892b5..2beee62bfb91 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -328,13 +328,10 @@ struct drm_i915_cg_funcs {
 	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
 };
 
-struct drm_i915_display_funcs {
-	void (*get_cdclk)(struct drm_i915_private *dev_priv,
-			  struct intel_cdclk_config *cdclk_config);
-	void (*set_cdclk)(struct drm_i915_private *dev_priv,
-			  const struct intel_cdclk_config *cdclk_config,
-			  enum pipe pipe);
-	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
+/* functions used for watermark calcs for display. */
+struct drm_i915_wm_disp_funcs {
+	/* update_wm is for legacy wm management */
+	void (*update_wm)(struct drm_i915_private *dev_priv);
 	int (*compute_pipe_wm)(struct intel_atomic_state *state,
 			       struct intel_crtc *crtc);
 	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
@@ -346,7 +343,15 @@ struct drm_i915_display_funcs {
 	void (*optimize_watermarks)(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc);
 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
-	void (*update_wm)(struct drm_i915_private *dev_priv);
+};
+
+struct drm_i915_display_funcs {
+	void (*get_cdclk)(struct drm_i915_private *dev_priv,
+			  struct intel_cdclk_config *cdclk_config);
+	void (*set_cdclk)(struct drm_i915_private *dev_priv,
+			  const struct intel_cdclk_config *cdclk_config,
+			  enum pipe pipe);
+	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
 	/* Returns the active state of the crtc, and if the crtc is active,
@@ -976,6 +981,9 @@ struct drm_i915_private {
 	/* pm private clock gating functions */
 	struct drm_i915_cg_funcs cg_funcs;
 
+	/* pm display functions */
+	struct drm_i915_wm_disp_funcs wm_disp;
+
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 73549e774881..7a457646fb84 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7962,7 +7962,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	/* For FIFO watermark updates */
 	if (DISPLAY_VER(dev_priv) >= 9) {
 		skl_setup_wm_latency(dev_priv);
-		dev_priv->display.compute_global_watermarks = skl_compute_wm;
+		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_setup_wm_latency(dev_priv);
 
@@ -7970,12 +7970,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
 		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
 		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
-			dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
-			dev_priv->display.compute_intermediate_wm =
+			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
+			dev_priv->wm_disp.compute_intermediate_wm =
 				ilk_compute_intermediate_wm;
-			dev_priv->display.initial_watermarks =
+			dev_priv->wm_disp.initial_watermarks =
 				ilk_initial_watermarks;
-			dev_priv->display.optimize_watermarks =
+			dev_priv->wm_disp.optimize_watermarks =
 				ilk_optimize_watermarks;
 		} else {
 			drm_dbg_kms(&dev_priv->drm,
@@ -7984,17 +7984,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		}
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_setup_wm_latency(dev_priv);
-		dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
-		dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
-		dev_priv->display.initial_watermarks = vlv_initial_watermarks;
-		dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
-		dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
+		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
+		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
+		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
+		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
+		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
 	} else if (IS_G4X(dev_priv)) {
 		g4x_setup_wm_latency(dev_priv);
-		dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
-		dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
-		dev_priv->display.initial_watermarks = g4x_initial_watermarks;
-		dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
+		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
+		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
+		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
+		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
 	} else if (IS_PINEVIEW(dev_priv)) {
 		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 					    dev_priv->is_ddr3,
@@ -8008,18 +8008,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
-			dev_priv->display.update_wm = NULL;
+			dev_priv->wm_disp.update_wm = NULL;
 		} else
-			dev_priv->display.update_wm = pnv_update_wm;
+			dev_priv->wm_disp.update_wm = pnv_update_wm;
 	} else if (DISPLAY_VER(dev_priv) == 4) {
-		dev_priv->display.update_wm = i965_update_wm;
+		dev_priv->wm_disp.update_wm = i965_update_wm;
 	} else if (DISPLAY_VER(dev_priv) == 3) {
-		dev_priv->display.update_wm = i9xx_update_wm;
+		dev_priv->wm_disp.update_wm = i9xx_update_wm;
 	} else if (DISPLAY_VER(dev_priv) == 2) {
 		if (INTEL_NUM_PIPES(dev_priv) == 1)
-			dev_priv->display.update_wm = i845_update_wm;
+			dev_priv->wm_disp.update_wm = i845_update_wm;
 		else
-			dev_priv->display.update_wm = i9xx_update_wm;
+			dev_priv->wm_disp.update_wm = i9xx_update_wm;
 	} else {
 		drm_err(&dev_priv->drm,
 			"unexpected fall-through in %s\n", __func__);
-- 
2.31.1

[Intel-gfx] [PATCH 06/21] drm/i915: split color functions from display vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

These are only used internally in the color module
---
 drivers/gpu/drm/i915/display/intel_color.c | 64 +++++++++++-----------
 drivers/gpu/drm/i915/i915_drv.h            | 39 +++++++------
 2 files changed, 54 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->display.load_luts(crtc_state);
+	dev_priv->color_funcs.load_luts(crtc_state);
 }
 
 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->display.color_commit(crtc_state);
+	dev_priv->color_funcs.color_commit(crtc_state);
 }
 
 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	return dev_priv->display.color_check(crtc_state);
+	return dev_priv->color_funcs.color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (dev_priv->display.read_luts)
-		dev_priv->display.read_luts(crtc_state);
+	if (dev_priv->color_funcs.read_luts)
+		dev_priv->color_funcs.read_luts(crtc_state);
 }
 
 static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
 
 	if (HAS_GMCH(dev_priv)) {
 		if (IS_CHERRYVIEW(dev_priv)) {
-			dev_priv->display.color_check = chv_color_check;
-			dev_priv->display.color_commit = i9xx_color_commit;
-			dev_priv->display.load_luts = chv_load_luts;
-			dev_priv->display.read_luts = chv_read_luts;
+			dev_priv->color_funcs.color_check = chv_color_check;
+			dev_priv->color_funcs.color_commit = i9xx_color_commit;
+			dev_priv->color_funcs.load_luts = chv_load_luts;
+			dev_priv->color_funcs.read_luts = chv_read_luts;
 		} else if (DISPLAY_VER(dev_priv) >= 4) {
-			dev_priv->display.color_check = i9xx_color_check;
-			dev_priv->display.color_commit = i9xx_color_commit;
-			dev_priv->display.load_luts = i965_load_luts;
-			dev_priv->display.read_luts = i965_read_luts;
+			dev_priv->color_funcs.color_check = i9xx_color_check;
+			dev_priv->color_funcs.color_commit = i9xx_color_commit;
+			dev_priv->color_funcs.load_luts = i965_load_luts;
+			dev_priv->color_funcs.read_luts = i965_read_luts;
 		} else {
-			dev_priv->display.color_check = i9xx_color_check;
-			dev_priv->display.color_commit = i9xx_color_commit;
-			dev_priv->display.load_luts = i9xx_load_luts;
-			dev_priv->display.read_luts = i9xx_read_luts;
+			dev_priv->color_funcs.color_check = i9xx_color_check;
+			dev_priv->color_funcs.color_commit = i9xx_color_commit;
+			dev_priv->color_funcs.load_luts = i9xx_load_luts;
+			dev_priv->color_funcs.read_luts = i9xx_read_luts;
 		}
 	} else {
 		if (DISPLAY_VER(dev_priv) >= 11)
-			dev_priv->display.color_check = icl_color_check;
+			dev_priv->color_funcs.color_check = icl_color_check;
 		else if (DISPLAY_VER(dev_priv) >= 10)
-			dev_priv->display.color_check = glk_color_check;
+			dev_priv->color_funcs.color_check = glk_color_check;
 		else if (DISPLAY_VER(dev_priv) >= 7)
-			dev_priv->display.color_check = ivb_color_check;
+			dev_priv->color_funcs.color_check = ivb_color_check;
 		else
-			dev_priv->display.color_check = ilk_color_check;
+			dev_priv->color_funcs.color_check = ilk_color_check;
 
 		if (DISPLAY_VER(dev_priv) >= 9)
-			dev_priv->display.color_commit = skl_color_commit;
+			dev_priv->color_funcs.color_commit = skl_color_commit;
 		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-			dev_priv->display.color_commit = hsw_color_commit;
+			dev_priv->color_funcs.color_commit = hsw_color_commit;
 		else
-			dev_priv->display.color_commit = ilk_color_commit;
+			dev_priv->color_funcs.color_commit = ilk_color_commit;
 
 		if (DISPLAY_VER(dev_priv) >= 11) {
-			dev_priv->display.load_luts = icl_load_luts;
-			dev_priv->display.read_luts = icl_read_luts;
+			dev_priv->color_funcs.load_luts = icl_load_luts;
+			dev_priv->color_funcs.read_luts = icl_read_luts;
 		} else if (DISPLAY_VER(dev_priv) == 10) {
-			dev_priv->display.load_luts = glk_load_luts;
-			dev_priv->display.read_luts = glk_read_luts;
+			dev_priv->color_funcs.load_luts = glk_load_luts;
+			dev_priv->color_funcs.read_luts = glk_read_luts;
 		} else if (DISPLAY_VER(dev_priv) >= 8) {
-			dev_priv->display.load_luts = bdw_load_luts;
+			dev_priv->color_funcs.load_luts = bdw_load_luts;
 		} else if (DISPLAY_VER(dev_priv) >= 7) {
-			dev_priv->display.load_luts = ivb_load_luts;
+			dev_priv->color_funcs.load_luts = ivb_load_luts;
 		} else {
-			dev_priv->display.load_luts = ilk_load_luts;
-			dev_priv->display.read_luts = ilk_read_luts;
+			dev_priv->color_funcs.load_luts = ilk_load_luts;
+			dev_priv->color_funcs.read_luts = ilk_read_luts;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2beee62bfb91..7e5a8b1bbdd8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -345,6 +345,25 @@ struct drm_i915_wm_disp_funcs {
 	int (*compute_global_watermarks)(struct intel_atomic_state *state);
 };
 
+struct drm_i915_display_color_funcs {
+	int (*color_check)(struct intel_crtc_state *crtc_state);
+	/*
+	 * Program double buffered color management registers during
+	 * vblank evasion. The registers should then latch during the
+	 * next vblank start, alongside any other double buffered registers
+	 * involved with the same commit.
+	 */
+	void (*color_commit)(const struct intel_crtc_state *crtc_state);
+	/*
+	 * Load LUTs (and other single buffered color management
+	 * registers). Will (hopefully) be called during the vblank
+	 * following the latching of any double buffered registers
+	 * involved with the same commit.
+	 */
+	void (*load_luts)(const struct intel_crtc_state *crtc_state);
+	void (*read_luts)(struct intel_crtc_state *crtc_state);
+};
+
 struct drm_i915_display_funcs {
 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config);
@@ -381,23 +400,6 @@ struct drm_i915_display_funcs {
 	/* render clock increase/decrease */
 	/* display clock increase/decrease */
 	/* pll clock increase/decrease */
-
-	int (*color_check)(struct intel_crtc_state *crtc_state);
-	/*
-	 * Program double buffered color management registers during
-	 * vblank evasion. The registers should then latch during the
-	 * next vblank start, alongside any other double buffered registers
-	 * involved with the same commit.
-	 */
-	void (*color_commit)(const struct intel_crtc_state *crtc_state);
-	/*
-	 * Load LUTs (and other single buffered color management
-	 * registers). Will (hopefully) be called during the vblank
-	 * following the latching of any double buffered registers
-	 * involved with the same commit.
-	 */
-	void (*load_luts)(const struct intel_crtc_state *crtc_state);
-	void (*read_luts)(struct intel_crtc_state *crtc_state);
 };
 
 
@@ -987,6 +989,9 @@ struct drm_i915_private {
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
+	/* Display internal color functions */
+	struct drm_i915_display_color_funcs color_funcs;
+
 	/* PCH chipset type */
 	enum intel_pch pch_type;
 	unsigned short pch_id;
-- 
2.31.1

[Intel-gfx] [PATCH 07/21] drm/i915: split audio functions from display vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

These are only used internally in the audio code
---
 drivers/gpu/drm/i915/display/intel_audio.c | 24 +++++++++++-----------
 drivers/gpu/drm/i915/i915_drv.h            | 19 +++++++++++------
 2 files changed, 25 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 
 	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 
-	if (dev_priv->display.audio_codec_enable)
-		dev_priv->display.audio_codec_enable(encoder,
+	if (dev_priv->audio_funcs.audio_codec_enable)
+		dev_priv->audio_funcs.audio_codec_enable(encoder,
 						     crtc_state,
 						     conn_state);
 
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 	enum pipe pipe = crtc->pipe;
 
-	if (dev_priv->display.audio_codec_disable)
-		dev_priv->display.audio_codec_disable(encoder,
+	if (dev_priv->audio_funcs.audio_codec_disable)
+		dev_priv->audio_funcs.audio_codec_disable(encoder,
 						      old_crtc_state,
 						      old_conn_state);
 
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_G4X(dev_priv)) {
-		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
-		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+		dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
+		dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
-		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
+		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
 	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
-		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
-		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+		dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
+		dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
-		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
+		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7e5a8b1bbdd8..3e60bf8182e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct drm_i915_display_color_funcs {
 	void (*read_luts)(struct intel_crtc_state *crtc_state);
 };
 
+struct drm_i915_display_audio_funcs {
+	void (*audio_codec_enable)(struct intel_encoder *encoder,
+				   const struct intel_crtc_state *crtc_state,
+				   const struct drm_connector_state *conn_state);
+	void (*audio_codec_disable)(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *old_crtc_state,
+				    const struct drm_connector_state *old_conn_state);
+};
+
 struct drm_i915_display_funcs {
 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
 			     struct intel_crtc *crtc);
 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
 	void (*commit_modeset_disables)(struct intel_atomic_state *state);
-	void (*audio_codec_enable)(struct intel_encoder *encoder,
-				   const struct intel_crtc_state *crtc_state,
-				   const struct drm_connector_state *conn_state);
-	void (*audio_codec_disable)(struct intel_encoder *encoder,
-				    const struct intel_crtc_state *old_crtc_state,
-				    const struct drm_connector_state *old_conn_state);
+
 	void (*fdi_link_train)(struct intel_crtc *crtc,
 			       const struct intel_crtc_state *crtc_state);
 	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
@@ -992,6 +996,9 @@ struct drm_i915_private {
 	/* Display internal color functions */
 	struct drm_i915_display_color_funcs color_funcs;
 
+	/* Display internal audio functions */
+	struct drm_i915_display_audio_funcs audio_funcs;
+
 	/* PCH chipset type */
 	enum intel_pch pch_type;
 	unsigned short pch_id;
-- 
2.31.1

[Intel-gfx] [PATCH 08/21] drm/i915: split cdclk functions from display vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 148 +++++++++---------
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   8 +-
 4 files changed, 83 insertions(+), 77 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 34fa4130d5c4..c12b4e6bf5f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	 * at least what the CDCLK frequency requires.
 	 */
 	cdclk_config->voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
 	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
 	cdclk_config.voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
@@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.cdclk = cdclk_config.bypass;
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level =
-		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
@@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
 		return;
 
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
+	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
 		return;
 
 	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 				     &dev_priv->gmbus_mutex);
 	}
 
-	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+	dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
 
 	for_each_intel_dp(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
 	cdclk_state->logical.cdclk = cdclk;
 	cdclk_state->logical.voltage_level =
 		max_t(int, min_voltage_level,
-		      dev_priv->display.calc_voltage_level(cdclk));
+		      dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
 
 	if (!cdclk_state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
 		cdclk_state->actual.vco = vco;
 		cdclk_state->actual.cdclk = cdclk;
 		cdclk_state->actual.voltage_level =
-			dev_priv->display.calc_voltage_level(cdclk);
+			dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
 	} else {
 		cdclk_state->actual = cdclk_state->logical;
 	}
@@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 	new_cdclk_state->active_pipes =
 		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
 
-	ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
+	ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
 	if (ret)
 		return ret;
 
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_cdclk(struct drm_i915_private *dev_priv)
 {
-	dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
 
 	/*
 	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_DG2(dev_priv)) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
 		dev_priv->cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
 		/* Wa_22011320316:adl-p[a0] */
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
 		else
 			dev_priv->cdclk.table = adlp_cdclk_table;
 	} else if (IS_ROCKETLAKE(dev_priv)) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
 		dev_priv->cdclk.table = rkl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_JSL_EHL(dev_priv)) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = bxt_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
 		if (IS_GEMINILAKE(dev_priv))
 			dev_priv->cdclk.table = glk_cdclk_table;
 		else
 			dev_priv->cdclk.table = bxt_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) == 9) {
-		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = skl_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
 	} else if (IS_BROADWELL(dev_priv)) {
-		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = bdw_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
 	} else if (IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = chv_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
 	} else if (IS_VALLEYVIEW(dev_priv)) {
-		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->display.set_cdclk = vlv_set_cdclk;
-		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
 	} else {
-		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
+		dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
 	}
 
 	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
-		dev_priv->display.get_cdclk = bxt_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
 	else if (DISPLAY_VER(dev_priv) == 9)
-		dev_priv->display.get_cdclk = skl_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
 	else if (IS_BROADWELL(dev_priv))
-		dev_priv->display.get_cdclk = bdw_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
 	else if (IS_HASWELL(dev_priv))
-		dev_priv->display.get_cdclk = hsw_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		dev_priv->display.get_cdclk = vlv_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
 	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
-		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
 	else if (IS_IRONLAKE(dev_priv))
-		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
 	else if (IS_GM45(dev_priv))
-		dev_priv->display.get_cdclk = gm45_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
 	else if (IS_G45(dev_priv))
-		dev_priv->display.get_cdclk = g33_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
 	else if (IS_I965GM(dev_priv))
-		dev_priv->display.get_cdclk = i965gm_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
 	else if (IS_I965G(dev_priv))
-		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
 	else if (IS_PINEVIEW(dev_priv))
-		dev_priv->display.get_cdclk = pnv_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
 	else if (IS_G33(dev_priv))
-		dev_priv->display.get_cdclk = g33_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
 	else if (IS_I945GM(dev_priv))
-		dev_priv->display.get_cdclk = i945gm_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
 	else if (IS_I945G(dev_priv))
-		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
 	else if (IS_I915GM(dev_priv))
-		dev_priv->display.get_cdclk = i915gm_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
 	else if (IS_I915G(dev_priv))
-		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
 	else if (IS_I865G(dev_priv))
-		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
 	else if (IS_I85X(dev_priv))
-		dev_priv->display.get_cdclk = i85x_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
 	else if (IS_I845G(dev_priv))
-		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
 	else if (IS_I830(dev_priv))
-		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
 
-	if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
+	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
 		     "Unknown platform. Assuming 133 MHz CDCLK\n"))
-		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
+		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b1202ede3fb0..ccd0332e7945 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9120,7 +9120,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
 		*need_cdclk_calc = true;
 
-	ret = dev_priv->display.bw_calc_min_cdclk(state);
+	ret = dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index cce1a926fcc1..2cf420c06ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
+	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	drm_WARN_ON(&dev_priv->drm,
 		    intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3e60bf8182e3..fbe92f248d05 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -373,7 +373,7 @@ struct drm_i915_display_audio_funcs {
 				    const struct drm_connector_state *old_conn_state);
 };
 
-struct drm_i915_display_funcs {
+struct drm_i915_display_cdclk_funcs {
 	void (*get_cdclk)(struct drm_i915_private *dev_priv,
 			  struct intel_cdclk_config *cdclk_config);
 	void (*set_cdclk)(struct drm_i915_private *dev_priv,
@@ -382,6 +382,9 @@ struct drm_i915_display_funcs {
 	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
 	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
 	u8 (*calc_voltage_level)(int cdclk);
+};
+
+struct drm_i915_display_funcs {
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
 	bool (*get_pipe_config)(struct intel_crtc *,
@@ -999,6 +1002,9 @@ struct drm_i915_private {
 	/* Display internal audio functions */
 	struct drm_i915_display_audio_funcs audio_funcs;
 
+	/* Display CDCLK functions */
+	struct drm_i915_display_cdclk_funcs cdclk_funcs;
+
 	/* PCH chipset type */
 	enum intel_pch pch_type;
 	unsigned short pch_id;
-- 
2.31.1

[Intel-gfx] [PATCH 09/21] drm/i915: split irq hotplug function from display vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

This provide a service from irq to display, so make it separate
---
 drivers/gpu/drm/i915/display/intel_hotplug.c |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h              |  9 ++++++++-
 drivers/gpu/drm/i915/i915_irq.c              | 14 +++++++-------
 3 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..a06e1e1b33e1 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
 
 static void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-	if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
-		i915->display.hpd_irq_setup(i915);
+	if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
+		i915->irq_funcs.hpd_irq_setup(i915);
 }
 
 static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbe92f248d05..ece23401cb46 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct drm_i915_display_cdclk_funcs {
 	u8 (*calc_voltage_level)(int cdclk);
 };
 
+struct drm_i915_irq_funcs {
+	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
 struct drm_i915_display_funcs {
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
 
 	void (*fdi_link_train)(struct intel_crtc *crtc,
 			       const struct intel_crtc_state *crtc_state);
-	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
@@ -993,6 +997,9 @@ struct drm_i915_private {
 	/* pm display functions */
 	struct drm_i915_wm_disp_funcs wm_disp;
 
+	/* irq display functions */
+	struct drm_i915_irq_funcs irq_funcs;
+
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..f515a3a76a8e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 
 	if (HAS_GMCH(dev_priv)) {
 		if (I915_HAS_HOTPLUG(dev_priv))
-			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
 	} else {
 		if (HAS_PCH_DG1(dev_priv))
-			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
 		else if (DISPLAY_VER(dev_priv) >= 11)
-			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
 		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-			dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
-			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
 		else
-			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+			dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
 	}
 }
 
-- 
2.31.1

[Intel-gfx] [PATCH 10/21] drm/i915: split fdi link training from display vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c     |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h              | 11 ++++++++---
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ccd0332e7945..b981a923cc2f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
 	assert_pch_transcoder_disabled(dev_priv, pipe);
 
 	/* For PCH output, training FDI link */
-	dev_priv->display.fdi_link_train(crtc, crtc_state);
+	dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
 
 	/* We need to program the right clock selection before writing the pixel
 	 * mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..d9f952e0c67f 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -1009,11 +1009,11 @@ void
 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
 {
 	if (IS_IRONLAKE(dev_priv)) {
-		dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+		dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
 	} else if (IS_SANDYBRIDGE(dev_priv)) {
-		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+		dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
 	} else if (IS_IVYBRIDGE(dev_priv)) {
 		/* FIXME: detect B0+ stepping and use auto training */
-		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+		dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ece23401cb46..49b23ea46475 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct drm_i915_irq_funcs {
 	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
 };
 
+struct drm_i915_fdi_link_train_funcs {
+	void (*fdi_link_train)(struct intel_crtc *crtc,
+			       const struct intel_crtc_state *crtc_state);
+};
+
 struct drm_i915_display_funcs {
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
 	void (*commit_modeset_disables)(struct intel_atomic_state *state);
 
-	void (*fdi_link_train)(struct intel_crtc *crtc,
-			       const struct intel_crtc_state *crtc_state);
-
 	/* clock updates for mode set */
 	/* cursor updates */
 	/* render clock increase/decrease */
@@ -1000,6 +1002,9 @@ struct drm_i915_private {
 	/* irq display functions */
 	struct drm_i915_irq_funcs irq_funcs;
 
+	/* fdi display functions */
+	struct drm_i915_fdi_link_train_funcs fdi_funcs;
+
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
-- 
2.31.1

[Intel-gfx] [PATCH 11/21] drm/i915: split the dpll clock compute out from display vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

this could be merged later but for now it's simple to split it out.
---
 drivers/gpu/drm/i915/display/intel_display.c |  6 +++---
 drivers/gpu/drm/i915/display/intel_dpll.c    | 16 ++++++++--------
 drivers/gpu/drm/i915/i915_drv.h              |  8 +++++++-
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b981a923cc2f..87950202f4ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		crtc_state->update_wm_post = true;
 
 	if (mode_changed && crtc_state->hw.enable &&
-	    dev_priv->display.crtc_compute_clock &&
+	    dev_priv->dpll_funcs.crtc_compute_clock &&
 	    !crtc_state->bigjoiner_slave &&
 	    !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
-		ret = dev_priv->display.crtc_compute_clock(crtc_state);
+		ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	if (!dev_priv->display.crtc_compute_clock)
+	if (!dev_priv->dpll_funcs.crtc_compute_clock)
 		return;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..9326c7cbb05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
 {
 	if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
-		dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
 	else if (HAS_PCH_SPLIT(dev_priv))
-		dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
 	else if (IS_G4X(dev_priv))
-		dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
 	else if (IS_PINEVIEW(dev_priv))
-		dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
 	else if (DISPLAY_VER(dev_priv) != 2)
-		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
 	else
-		dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+		dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
 }
 
 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49b23ea46475..461ab0a0f088 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
 			       const struct intel_crtc_state *crtc_state);
 };
 
+struct drm_i915_dpll_funcs {
+	int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
 struct drm_i915_display_funcs {
 	/* Returns the active state of the crtc, and if the crtc is active,
 	 * fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
 				struct intel_crtc_state *);
 	void (*get_initial_plane_config)(struct intel_crtc *,
 					 struct intel_initial_plane_config *);
-	int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
 	void (*crtc_enable)(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc);
 	void (*crtc_disable)(struct intel_atomic_state *state,
@@ -1005,6 +1008,9 @@ struct drm_i915_private {
 	/* fdi display functions */
 	struct drm_i915_fdi_link_train_funcs fdi_funcs;
 
+	/* display pll funcs */
+	struct drm_i915_dpll_funcs dpll_funcs;
+
 	/* Display functions */
 	struct drm_i915_display_funcs display;
 
-- 
2.31.1

[Intel-gfx] [PATCH 12/21] drm/i915: constify fdi link training vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

Avoid having writeable function pointers.
---
 drivers/gpu/drm/i915/display/intel_display.c |  2 +-
 drivers/gpu/drm/i915/display/intel_fdi.c     | 18 +++++++++++++++---
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 87950202f4ce..0ad577aceb9d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
 	assert_pch_transcoder_disabled(dev_priv, pipe);
 
 	/* For PCH output, training FDI link */
-	dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+	dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
 
 	/* We need to program the right clock selection before writing the pixel
 	 * mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index d9f952e0c67f..68aa9c7b18ec 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -1005,15 +1005,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
 	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
 }
 
+static const struct drm_i915_fdi_link_train_funcs ilk_funcs = {
+	.fdi_link_train = ilk_fdi_link_train
+};
+
+static const struct drm_i915_fdi_link_train_funcs gen6_funcs = {
+	.fdi_link_train = gen6_fdi_link_train
+};
+
+static const struct drm_i915_fdi_link_train_funcs ivb_funcs = {
+	.fdi_link_train = ivb_manual_fdi_link_train
+};
+
 void
 intel_fdi_init_hook(struct drm_i915_private *dev_priv)
 {
 	if (IS_IRONLAKE(dev_priv)) {
-		dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+		dev_priv->fdi_funcs = &ilk_funcs;
 	} else if (IS_SANDYBRIDGE(dev_priv)) {
-		dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+		dev_priv->fdi_funcs = &gen6_funcs;
 	} else if (IS_IVYBRIDGE(dev_priv)) {
 		/* FIXME: detect B0+ stepping and use auto training */
-		dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+		dev_priv->fdi_funcs = &ivb_funcs;
 	}
 }
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 461ab0a0f088..b3765222e717 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1006,7 +1006,7 @@ struct drm_i915_private {
 	struct drm_i915_irq_funcs irq_funcs;
 
 	/* fdi display functions */
-	struct drm_i915_fdi_link_train_funcs fdi_funcs;
+	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
 
 	/* display pll funcs */
 	struct drm_i915_dpll_funcs dpll_funcs;
-- 
2.31.1

[Intel-gfx] [PATCH 13/21] drm/i915: constify irq function vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
---
 drivers/gpu/drm/i915/display/intel_hotplug.c |  4 +--
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 drivers/gpu/drm/i915/i915_irq.c              | 27 +++++++++++++++-----
 3 files changed, 23 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index a06e1e1b33e1..97df40107213 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
 
 static void intel_hpd_irq_setup(struct drm_i915_private *i915)
 {
-	if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
-		i915->irq_funcs.hpd_irq_setup(i915);
+	if (i915->display_irqs_enabled && i915->irq_funcs)
+		i915->irq_funcs->hpd_irq_setup(i915);
 }
 
 static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3765222e717..6050bb519b18 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
 	struct drm_i915_wm_disp_funcs wm_disp;
 
 	/* irq display functions */
-	struct drm_i915_irq_funcs irq_funcs;
+	const struct drm_i915_irq_funcs *irq_funcs;
 
 	/* fdi display functions */
 	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f515a3a76a8e..29231daf6057 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,19 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
 	return ret;
 }
 
+#define HPD_FUNCS(platform)					\
+static const struct drm_i915_irq_funcs platform##_hpd_funcs = { \
+	.hpd_irq_setup = platform##_hpd_irq_setup		\
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+
 /**
  * intel_irq_init - initializes irq support
  * @dev_priv: i915 device instance
@@ -4395,20 +4408,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 
 	if (HAS_GMCH(dev_priv)) {
 		if (I915_HAS_HOTPLUG(dev_priv))
-			dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
+			dev_priv->irq_funcs = &i915_hpd_funcs;
 	} else {
 		if (HAS_PCH_DG1(dev_priv))
-			dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
+			dev_priv->irq_funcs = &dg1_hpd_funcs;
 		else if (DISPLAY_VER(dev_priv) >= 11)
-			dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
+			dev_priv->irq_funcs = &gen11_hpd_funcs;
 		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
-			dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
+			dev_priv->irq_funcs = &bxt_hpd_funcs;
 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
-			dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
+			dev_priv->irq_funcs = &icp_hpd_funcs;
 		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
-			dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
+			dev_priv->irq_funcs = &spt_hpd_funcs;
 		else
-			dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
+			dev_priv->irq_funcs = &ilk_hpd_funcs;
 	}
 }
 
-- 
2.31.1

[Intel-gfx] [PATCH 14/21] drm/i915: constify color function vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

---
 drivers/gpu/drm/i915/display/intel_color.c | 138 ++++++++++++++-------
 drivers/gpu/drm/i915/i915_drv.h            |   2 +-
 2 files changed, 93 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..b4e010c7e29d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->color_funcs.load_luts(crtc_state);
+	dev_priv->color_funcs->load_luts(crtc_state);
 }
 
 void intel_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	dev_priv->color_funcs.color_commit(crtc_state);
+	dev_priv->color_funcs->color_commit(crtc_state);
 }
 
 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	return dev_priv->color_funcs.color_check(crtc_state);
+	return dev_priv->color_funcs->color_check(crtc_state);
 }
 
 void intel_color_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 
-	if (dev_priv->color_funcs.read_luts)
-		dev_priv->color_funcs.read_luts(crtc_state);
+	if (dev_priv->color_funcs->read_luts)
+		dev_priv->color_funcs->read_luts(crtc_state);
 }
 
 static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
 	}
 }
 
+static const struct drm_i915_display_color_funcs chv_color_funcs = {
+	.color_check = chv_color_check,
+	.color_commit = i9xx_color_commit,
+	.load_luts = chv_load_luts,
+	.read_luts = chv_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs i965_color_funcs = {
+	.color_check = i9xx_color_check,
+	.color_commit = i9xx_color_commit,
+	.load_luts = i965_load_luts,
+	.read_luts = i965_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs i9xx_color_funcs = {
+	.color_check = i9xx_color_check,
+	.color_commit = i9xx_color_commit,
+	.load_luts = i9xx_load_luts,
+	.read_luts = i9xx_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs icl_color_funcs = {
+	.color_check = icl_color_check,
+	.color_commit = skl_color_commit,
+	.load_luts = icl_load_luts,
+	.read_luts = icl_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs glk_color_funcs = {
+	.color_check = glk_color_check,
+	.color_commit = skl_color_commit,
+	.load_luts = glk_load_luts,
+	.read_luts = glk_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs skl_color_funcs = {
+	.color_check = ivb_color_check,
+	.color_commit = skl_color_commit,
+	.load_luts = bdw_load_luts,
+	.read_luts = NULL,
+};
+
+static const struct drm_i915_display_color_funcs bdw_color_funcs = {
+	.color_check = ivb_color_check,
+	.color_commit = hsw_color_commit,
+	.load_luts = bdw_load_luts,
+	.read_luts = NULL,
+};
+
+static const struct drm_i915_display_color_funcs hsw_color_funcs = {
+	.color_check = ivb_color_check,
+	.color_commit = hsw_color_commit,
+	.load_luts = ivb_load_luts,
+	.read_luts = NULL,
+};
+
+static const struct drm_i915_display_color_funcs ivb_color_funcs = {
+	.color_check = ivb_color_check,
+	.color_commit = ilk_color_commit,
+	.load_luts = ilk_load_luts,
+	.read_luts = ilk_read_luts,
+};
+
+static const struct drm_i915_display_color_funcs ilk_color_funcs = {
+	.color_check = ilk_color_check,
+	.color_commit = ilk_color_commit,
+	.load_luts = ilk_load_luts,
+	.read_luts = ilk_read_luts,
+};
+
 void intel_color_init(struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
 
 	if (HAS_GMCH(dev_priv)) {
 		if (IS_CHERRYVIEW(dev_priv)) {
-			dev_priv->color_funcs.color_check = chv_color_check;
-			dev_priv->color_funcs.color_commit = i9xx_color_commit;
-			dev_priv->color_funcs.load_luts = chv_load_luts;
-			dev_priv->color_funcs.read_luts = chv_read_luts;
+			dev_priv->color_funcs = &chv_color_funcs;
 		} else if (DISPLAY_VER(dev_priv) >= 4) {
-			dev_priv->color_funcs.color_check = i9xx_color_check;
-			dev_priv->color_funcs.color_commit = i9xx_color_commit;
-			dev_priv->color_funcs.load_luts = i965_load_luts;
-			dev_priv->color_funcs.read_luts = i965_read_luts;
+			dev_priv->color_funcs = &i965_color_funcs;
 		} else {
-			dev_priv->color_funcs.color_check = i9xx_color_check;
-			dev_priv->color_funcs.color_commit = i9xx_color_commit;
-			dev_priv->color_funcs.load_luts = i9xx_load_luts;
-			dev_priv->color_funcs.read_luts = i9xx_read_luts;
+			dev_priv->color_funcs = &i9xx_color_funcs;
 		}
 	} else {
 		if (DISPLAY_VER(dev_priv) >= 11)
-			dev_priv->color_funcs.color_check = icl_color_check;
-		else if (DISPLAY_VER(dev_priv) >= 10)
-			dev_priv->color_funcs.color_check = glk_color_check;
-		else if (DISPLAY_VER(dev_priv) >= 7)
-			dev_priv->color_funcs.color_check = ivb_color_check;
-		else
-			dev_priv->color_funcs.color_check = ilk_color_check;
-
-		if (DISPLAY_VER(dev_priv) >= 9)
-			dev_priv->color_funcs.color_commit = skl_color_commit;
-		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
-			dev_priv->color_funcs.color_commit = hsw_color_commit;
-		else
-			dev_priv->color_funcs.color_commit = ilk_color_commit;
-
-		if (DISPLAY_VER(dev_priv) >= 11) {
-			dev_priv->color_funcs.load_luts = icl_load_luts;
-			dev_priv->color_funcs.read_luts = icl_read_luts;
-		} else if (DISPLAY_VER(dev_priv) == 10) {
-			dev_priv->color_funcs.load_luts = glk_load_luts;
-			dev_priv->color_funcs.read_luts = glk_read_luts;
-		} else if (DISPLAY_VER(dev_priv) >= 8) {
-			dev_priv->color_funcs.load_luts = bdw_load_luts;
-		} else if (DISPLAY_VER(dev_priv) >= 7) {
-			dev_priv->color_funcs.load_luts = ivb_load_luts;
-		} else {
-			dev_priv->color_funcs.load_luts = ilk_load_luts;
-			dev_priv->color_funcs.read_luts = ilk_read_luts;
-		}
+			dev_priv->color_funcs = &icl_color_funcs;
+		else if (DISPLAY_VER(dev_priv) == 10)
+			dev_priv->color_funcs = &glk_color_funcs;
+		else if (DISPLAY_VER(dev_priv) == 9)
+			dev_priv->color_funcs = &skl_color_funcs;
+		else if (DISPLAY_VER(dev_priv) == 8)
+			dev_priv->color_funcs = &bdw_color_funcs;
+		else if (DISPLAY_VER(dev_priv) == 7) {
+			if (IS_HASWELL(dev_priv))
+				dev_priv->color_funcs = &hsw_color_funcs;
+			else
+				dev_priv->color_funcs = &ivb_color_funcs;
+		} else
+			dev_priv->color_funcs = &ilk_color_funcs;
 	}
 
 	drm_crtc_enable_color_mgmt(&crtc->base,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6050bb519b18..e82df3bf493b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1015,7 +1015,7 @@ struct drm_i915_private {
 	struct drm_i915_display_funcs display;
 
 	/* Display internal color functions */
-	struct drm_i915_display_color_funcs color_funcs;
+	const struct drm_i915_display_color_funcs *color_funcs;
 
 	/* Display internal audio functions */
 	struct drm_i915_display_audio_funcs audio_funcs;
-- 
2.31.1

[Intel-gfx] [PATCH 15/21] drm/i915: constify the audio function vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

---
 drivers/gpu/drm/i915/display/intel_audio.c | 43 ++++++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h            |  2 +-
 2 files changed, 28 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..4707e1beb763 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
 
 	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
 
-	if (dev_priv->audio_funcs.audio_codec_enable)
-		dev_priv->audio_funcs.audio_codec_enable(encoder,
-						     crtc_state,
-						     conn_state);
+	if (dev_priv->audio_funcs)
+		dev_priv->audio_funcs->audio_codec_enable(encoder,
+							  crtc_state,
+							  conn_state);
 
 	mutex_lock(&dev_priv->av_mutex);
 	encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 	enum port port = encoder->port;
 	enum pipe pipe = crtc->pipe;
 
-	if (dev_priv->audio_funcs.audio_codec_disable)
-		dev_priv->audio_funcs.audio_codec_disable(encoder,
-						      old_crtc_state,
-						      old_conn_state);
+	if (dev_priv->audio_funcs)
+		dev_priv->audio_funcs->audio_codec_disable(encoder,
+							   old_crtc_state,
+							   old_conn_state);
 
 	mutex_lock(&dev_priv->av_mutex);
 	encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 	intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
 }
 
+static const struct drm_i915_display_audio_funcs g4x_audio_funcs = {
+	.audio_codec_enable = g4x_audio_codec_enable,
+	.audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct drm_i915_display_audio_funcs ilk_audio_funcs = {
+	.audio_codec_enable = ilk_audio_codec_enable,
+	.audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct drm_i915_display_audio_funcs hsw_audio_funcs = {
+	.audio_codec_enable = hsw_audio_codec_enable,
+	.audio_codec_disable = hsw_audio_codec_disable,
+};
+
 /**
  * intel_init_audio_hooks - Set up chip specific audio hooks
  * @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_G4X(dev_priv)) {
-		dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
-		dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
+		dev_priv->audio_funcs = &g4x_audio_funcs;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
-		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
+		dev_priv->audio_funcs = &ilk_audio_funcs;
 	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
-		dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
-		dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
+		dev_priv->audio_funcs = &hsw_audio_funcs;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
-		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
+		dev_priv->audio_funcs = &ilk_audio_funcs;
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e82df3bf493b..8d14318c5708 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1018,7 +1018,7 @@ struct drm_i915_private {
 	const struct drm_i915_display_color_funcs *color_funcs;
 
 	/* Display internal audio functions */
-	struct drm_i915_display_audio_funcs audio_funcs;
+	const struct drm_i915_display_audio_funcs *audio_funcs;
 
 	/* Display CDCLK functions */
 	struct drm_i915_display_cdclk_funcs cdclk_funcs;
-- 
2.31.1

[Intel-gfx] [PATCH 16/21] drm/i915: constify the dpll clock vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

---
 drivers/gpu/drm/i915/display/intel_display.c |  6 +--
 drivers/gpu/drm/i915/display/intel_dpll.c    | 49 ++++++++++++++++----
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 3 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0ad577aceb9d..d8a576d1435e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		crtc_state->update_wm_post = true;
 
 	if (mode_changed && crtc_state->hw.enable &&
-	    dev_priv->dpll_funcs.crtc_compute_clock &&
+	    dev_priv->dpll_funcs &&
 	    !crtc_state->bigjoiner_slave &&
 	    !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
-		ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+		ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
 		if (ret)
 			return ret;
 	}
@@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	int i;
 
-	if (!dev_priv->dpll_funcs.crtc_compute_clock)
+	if (!dev_priv->dpll_funcs)
 		return;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9326c7cbb05c..3df10b88e69f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1363,25 +1363,58 @@ static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
 	return 0;
 }
 
+static const struct drm_i915_dpll_funcs hsw_dpll_funcs = {
+	.crtc_compute_clock = hsw_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs ilk_dpll_funcs = {
+	.crtc_compute_clock = ilk_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs chv_dpll_funcs = {
+	.crtc_compute_clock = chv_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs vlv_dpll_funcs = {
+	.crtc_compute_clock = vlv_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs g4x_dpll_funcs = {
+	.crtc_compute_clock = g4x_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs pnv_dpll_funcs = {
+	.crtc_compute_clock = pnv_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs i9xx_dpll_funcs = {
+	.crtc_compute_clock = i9xx_crtc_compute_clock
+};
+
+static const struct drm_i915_dpll_funcs i8xx_dpll_funcs = {
+	.crtc_compute_clock = i8xx_crtc_compute_clock
+};
+
+
 void
 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
 {
 	if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
+		dev_priv->dpll_funcs = &hsw_dpll_funcs;
 	else if (HAS_PCH_SPLIT(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
+		dev_priv->dpll_funcs = &ilk_dpll_funcs;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
+		dev_priv->dpll_funcs = &chv_dpll_funcs;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
+		dev_priv->dpll_funcs = &vlv_dpll_funcs;
 	else if (IS_G4X(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
+		dev_priv->dpll_funcs = &g4x_dpll_funcs;
 	else if (IS_PINEVIEW(dev_priv))
-		dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
+		dev_priv->dpll_funcs = &pnv_dpll_funcs;
 	else if (DISPLAY_VER(dev_priv) != 2)
-		dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
+		dev_priv->dpll_funcs = &i9xx_dpll_funcs;
 	else
-		dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
+		dev_priv->dpll_funcs = &i8xx_dpll_funcs;
 }
 
 static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d14318c5708..a9563730aad5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1009,7 +1009,7 @@ struct drm_i915_private {
 	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
 
 	/* display pll funcs */
-	struct drm_i915_dpll_funcs dpll_funcs;
+	const struct drm_i915_dpll_funcs *dpll_funcs;
 
 	/* Display functions */
 	struct drm_i915_display_funcs display;
-- 
2.31.1

[Intel-gfx] [PATCH 17/21] drm/i915: constify the cdclk vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 306 ++++++++++++------
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 .../drm/i915/display/intel_display_power.c    |   2 +-
 drivers/gpu/drm/i915/i915_drv.h               |   2 +-
 4 files changed, 211 insertions(+), 101 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c12b4e6bf5f5..9ce053bea022 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
 	 * at least what the CDCLK frequency requires.
 	 */
 	cdclk_config->voltage_level =
-		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
+		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config->cdclk);
 }
 
 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
 	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
 	cdclk_config.voltage_level =
-		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
+		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
@@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
 	cdclk_config.cdclk = cdclk_config.bypass;
 	cdclk_config.vco = 0;
 	cdclk_config.voltage_level =
-		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
+		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
 
 	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
 }
@@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
 		return;
 
-	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
 		return;
 
 	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
 				     &dev_priv->gmbus_mutex);
 	}
 
-	dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+	dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
 
 	for_each_intel_dp(&dev_priv->drm, encoder) {
 		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
 	cdclk_state->logical.cdclk = cdclk;
 	cdclk_state->logical.voltage_level =
 		max_t(int, min_voltage_level,
-		      dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
+		      dev_priv->cdclk_funcs->calc_voltage_level(cdclk));
 
 	if (!cdclk_state->active_pipes) {
 		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
 		cdclk_state->actual.vco = vco;
 		cdclk_state->actual.cdclk = cdclk;
 		cdclk_state->actual.voltage_level =
-			dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+			dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
 	} else {
 		cdclk_state->actual = cdclk_state->logical;
 	}
@@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
 	new_cdclk_state->active_pipes =
 		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
 
-	ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
+	ret = dev_priv->cdclk_funcs->modeset_calc_cdclk(new_cdclk_state);
 	if (ret)
 		return ret;
 
@@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
  */
 void intel_update_cdclk(struct drm_i915_private *dev_priv)
 {
-	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+	dev_priv->cdclk_funcs->get_cdclk(dev_priv, &dev_priv->cdclk.hw);
 
 	/*
 	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2845,6 +2845,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 	return freq;
 }
 
+static struct drm_i915_display_cdclk_funcs tgl_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct drm_i915_display_cdclk_funcs ehl_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct drm_i915_display_cdclk_funcs icl_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct drm_i915_display_cdclk_funcs bxt_cdclk_funcs = {
+	.get_cdclk = bxt_get_cdclk,
+	.set_cdclk = bxt_set_cdclk,
+	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+	.calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct drm_i915_display_cdclk_funcs skl_cdclk_funcs = {
+	.get_cdclk = skl_get_cdclk,
+	.set_cdclk = skl_set_cdclk,
+	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs bdw_cdclk_funcs = {
+	.get_cdclk = bdw_get_cdclk,
+	.set_cdclk = bdw_set_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs chv_cdclk_funcs = {
+	.get_cdclk = vlv_get_cdclk,
+	.set_cdclk = chv_set_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs vlv_cdclk_funcs = {
+	.get_cdclk = vlv_get_cdclk,
+	.set_cdclk = vlv_set_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs hsw_cdclk_funcs = {
+	.get_cdclk = hsw_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* SNB, IVB, 965G, 945G */
+static struct drm_i915_display_cdclk_funcs fixed_400mhz_cdclk_funcs = {
+	.get_cdclk = fixed_400mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs ilk_cdclk_funcs = {
+	.get_cdclk = fixed_450mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs gm45_cdclk_funcs = {
+	.get_cdclk = gm45_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* G45 uses G33 */
+
+static struct drm_i915_display_cdclk_funcs i965gm_cdclk_funcs = {
+	.get_cdclk = i965gm_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i965G uses fixed 400 */
+
+static struct drm_i915_display_cdclk_funcs pnv_cdclk_funcs = {
+	.get_cdclk = pnv_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs g33_cdclk_funcs = {
+	.get_cdclk = g33_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i945gm_cdclk_funcs = {
+	.get_cdclk = i945gm_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+/* i945G uses fixed 400 */
+
+static struct drm_i915_display_cdclk_funcs i915gm_cdclk_funcs = {
+	.get_cdclk = i915gm_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i915g_cdclk_funcs = {
+	.get_cdclk = fixed_333mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i865g_cdclk_funcs = {
+	.get_cdclk = fixed_266mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i85x_cdclk_funcs = {
+	.get_cdclk = i85x_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i845g_cdclk_funcs = {
+	.get_cdclk = fixed_200mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
+static struct drm_i915_display_cdclk_funcs i830_cdclk_funcs = {
+	.get_cdclk = fixed_133mhz_get_cdclk,
+	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
+};
+
 /**
  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
  * @dev_priv: i915 device
@@ -2852,119 +3003,78 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_DG2(dev_priv)) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
 		dev_priv->cdclk.table = dg2_cdclk_table;
 	} else if (IS_ALDERLAKE_P(dev_priv)) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
 		/* Wa_22011320316:adl-p[a0] */
 		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
 			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
 		else
 			dev_priv->cdclk.table = adlp_cdclk_table;
 	} else if (IS_ROCKETLAKE(dev_priv)) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
 		dev_priv->cdclk.table = rkl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 12) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_JSL_EHL(dev_priv)) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) >= 11) {
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
+		dev_priv->cdclk_funcs = &icl_cdclk_funcs;
 		dev_priv->cdclk.table = icl_cdclk_table;
 	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
-		dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
+		dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
 		if (IS_GEMINILAKE(dev_priv))
 			dev_priv->cdclk.table = glk_cdclk_table;
 		else
 			dev_priv->cdclk.table = bxt_cdclk_table;
 	} else if (DISPLAY_VER(dev_priv) == 9) {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs = &skl_cdclk_funcs;
 	} else if (IS_BROADWELL(dev_priv)) {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
+	} else if (IS_HASWELL(dev_priv)) {
+		dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
 	} else if (IS_CHERRYVIEW(dev_priv)) {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs = &chv_cdclk_funcs;
 	} else if (IS_VALLEYVIEW(dev_priv)) {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
-	} else {
-		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
-		dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
+		dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
+	} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
+		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+	} else if (IS_IRONLAKE(dev_priv)) {
+		dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
+	} else if (IS_GM45(dev_priv)) {
+		dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
+	} else if (IS_G45(dev_priv)) {
+		dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+	} else if (IS_I965GM(dev_priv)) {
+		dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
+	} else if (IS_I965G(dev_priv)) {
+		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+	} else if (IS_PINEVIEW(dev_priv)) {
+		dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
+	} else if (IS_G33(dev_priv)) {
+		dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+	} else if (IS_I945GM(dev_priv)) {
+		dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
+	} else if (IS_I945G(dev_priv)) {
+		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+	} else if (IS_I915GM(dev_priv)) {
+		dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
+	} else if (IS_I915G(dev_priv)) {
+		dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
+	} else if (IS_I865G(dev_priv)) {
+		dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
+	} else if (IS_I85X(dev_priv)) {
+		dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
+	} else if (IS_I845G(dev_priv)) {
+		dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
+	} else if (IS_I830(dev_priv)) {
+		dev_priv->cdclk_funcs = &i830_cdclk_funcs;
 	}
 
-	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
-	else if (DISPLAY_VER(dev_priv) == 9)
-		dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
-	else if (IS_BROADWELL(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
-	else if (IS_HASWELL(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
-	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
-	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
-	else if (IS_IRONLAKE(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
-	else if (IS_GM45(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
-	else if (IS_G45(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
-	else if (IS_I965GM(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
-	else if (IS_I965G(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
-	else if (IS_PINEVIEW(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
-	else if (IS_G33(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
-	else if (IS_I945GM(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
-	else if (IS_I945G(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
-	else if (IS_I915GM(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
-	else if (IS_I915G(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
-	else if (IS_I865G(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
-	else if (IS_I85X(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
-	else if (IS_I845G(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
-	else if (IS_I830(dev_priv))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
-
-	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
-		     "Unknown platform. Assuming 133 MHz CDCLK\n"))
-		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
+	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
+		     "Unknown platform. Assuming i830\n"))
+		dev_priv->cdclk_funcs = &i830_cdclk_funcs;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d8a576d1435e..09c9dc741026 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9120,7 +9120,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
 	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
 		*need_cdclk_calc = true;
 
-	ret = dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+	ret = dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
 	if (ret)
 		return ret;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 2cf420c06ed6..b6c233039a54 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &cdclk_config);
+	dev_priv->cdclk_funcs->get_cdclk(dev_priv, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	drm_WARN_ON(&dev_priv->drm,
 		    intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a9563730aad5..085012727549 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1021,7 +1021,7 @@ struct drm_i915_private {
 	const struct drm_i915_display_audio_funcs *audio_funcs;
 
 	/* Display CDCLK functions */
-	struct drm_i915_display_cdclk_funcs cdclk_funcs;
+	const struct drm_i915_display_cdclk_funcs *cdclk_funcs;
 
 	/* PCH chipset type */
 	enum intel_pch pch_type;
-- 
2.31.1

[Intel-gfx] [PATCH 18/21] drm/i915: drop unused function ptr and comments.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

There was some excess comments and an unused vtbl ptr.
---
 drivers/gpu/drm/i915/i915_drv.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 085012727549..2231b93c2111 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
 	void (*crtc_disable)(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc);
 	void (*commit_modeset_enables)(struct intel_atomic_state *state);
-	void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
-	/* clock updates for mode set */
-	/* cursor updates */
-	/* render clock increase/decrease */
-	/* display clock increase/decrease */
-	/* pll clock increase/decrease */
 };
 
 
-- 
2.31.1

[Intel-gfx] [PATCH 19/21] drm/i915: constify display function vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

---
 drivers/gpu/drm/i915/display/intel_display.c | 81 ++++++++++++--------
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 2 files changed, 52 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 09c9dc741026..20fd35c6858c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3736,7 +3736,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 
 	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
 
-	dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+	dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
 
 	drm_atomic_state_put(state);
 
@@ -5941,7 +5941,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-	if (!i915->display.get_pipe_config(crtc, crtc_state))
+	if (!i915->display->get_pipe_config(crtc, crtc_state))
 		return false;
 
 	crtc_state->hw.active = true;
@@ -9778,7 +9778,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 
 	intel_crtc_update_active_timings(new_crtc_state);
 
-	dev_priv->display.crtc_enable(state, crtc);
+	dev_priv->display->crtc_enable(state, crtc);
 
 	if (new_crtc_state->bigjoiner_slave)
 		return;
@@ -9866,7 +9866,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	 */
 	intel_crtc_disable_pipe_crc(crtc);
 
-	dev_priv->display.crtc_disable(state, crtc);
+	dev_priv->display->crtc_disable(state, crtc);
 	crtc->active = false;
 	intel_fbc_disable(crtc);
 	intel_disable_shared_dpll(old_crtc_state);
@@ -10246,7 +10246,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	}
 
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
-	dev_priv->display.commit_modeset_enables(state);
+	dev_priv->display->commit_modeset_enables(state);
 
 	if (state->modeset) {
 		intel_encoders_update_complete(state);
@@ -11250,6 +11250,46 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
 	.atomic_state_free = intel_atomic_state_free,
 };
 
+static const struct drm_i915_display_funcs skl_display_funcs = {
+	.get_pipe_config = hsw_get_pipe_config,
+	.crtc_enable = hsw_crtc_enable,
+	.crtc_disable = hsw_crtc_disable,
+	.commit_modeset_enables = skl_commit_modeset_enables,
+	.get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+	.get_pipe_config = hsw_get_pipe_config,
+	.crtc_enable = hsw_crtc_enable,
+	.crtc_disable = hsw_crtc_disable,
+	.commit_modeset_enables = intel_commit_modeset_enables,
+	.get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+	.get_pipe_config = ilk_get_pipe_config,
+	.crtc_enable = ilk_crtc_enable,
+	.crtc_disable = ilk_crtc_disable,
+	.commit_modeset_enables = intel_commit_modeset_enables,
+	.get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+	.get_pipe_config = i9xx_get_pipe_config,
+	.crtc_enable = valleyview_crtc_enable,
+	.crtc_disable = i9xx_crtc_disable,
+	.commit_modeset_enables = intel_commit_modeset_enables,
+	.get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+	.get_pipe_config = i9xx_get_pipe_config,
+	.crtc_enable = i9xx_crtc_enable,
+	.crtc_disable = i9xx_crtc_disable,
+	.commit_modeset_enables = intel_commit_modeset_enables,
+	.get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
 /**
  * intel_init_display_hooks - initialize the display modesetting hooks
  * @dev_priv: device private
@@ -11265,38 +11305,19 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
 	intel_dpll_init_clock_hook(dev_priv);
 
 	if (DISPLAY_VER(dev_priv) >= 9) {
-		dev_priv->display.get_pipe_config = hsw_get_pipe_config;
-		dev_priv->display.crtc_enable = hsw_crtc_enable;
-		dev_priv->display.crtc_disable = hsw_crtc_disable;
+		dev_priv->display = &skl_display_funcs;
 	} else if (HAS_DDI(dev_priv)) {
-		dev_priv->display.get_pipe_config = hsw_get_pipe_config;
-		dev_priv->display.crtc_enable = hsw_crtc_enable;
-		dev_priv->display.crtc_disable = hsw_crtc_disable;
+		dev_priv->display = &ddi_display_funcs;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		dev_priv->display.get_pipe_config = ilk_get_pipe_config;
-		dev_priv->display.crtc_enable = ilk_crtc_enable;
-		dev_priv->display.crtc_disable = ilk_crtc_disable;
+		dev_priv->display = &pch_split_display_funcs;
 	} else if (IS_CHERRYVIEW(dev_priv) ||
 		   IS_VALLEYVIEW(dev_priv)) {
-		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-		dev_priv->display.crtc_enable = valleyview_crtc_enable;
-		dev_priv->display.crtc_disable = i9xx_crtc_disable;
+		dev_priv->display = &vlv_display_funcs;
 	} else {
-		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
-		dev_priv->display.crtc_enable = i9xx_crtc_enable;
-		dev_priv->display.crtc_disable = i9xx_crtc_disable;
+		dev_priv->display = &i9xx_display_funcs;
 	}
 
 	intel_fdi_init_hook(dev_priv);
-
-	if (DISPLAY_VER(dev_priv) >= 9) {
-		dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
-		dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
-	} else {
-		dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
-		dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
-	}
-
 }
 
 void intel_modeset_init_hw(struct drm_i915_private *i915)
@@ -11723,7 +11744,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
 		 * can even allow for smooth boot transitions if the BIOS
 		 * fb is large enough for the active pipe configuration.
 		 */
-		i915->display.get_initial_plane_config(crtc, &plane_config);
+		i915->display->get_initial_plane_config(crtc, &plane_config);
 
 		/*
 		 * If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2231b93c2111..fbcafc7cc075 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1005,7 +1005,7 @@ struct drm_i915_private {
 	const struct drm_i915_dpll_funcs *dpll_funcs;
 
 	/* Display functions */
-	struct drm_i915_display_funcs display;
+	const struct drm_i915_display_funcs *display;
 
 	/* Display internal color functions */
 	const struct drm_i915_display_color_funcs *color_funcs;
-- 
2.31.1

[Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable.

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

I used a macro to avoid making any really silly mistakes here.
---
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
 2 files changed, 54 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fbcafc7cc075..44094a25a110 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -990,7 +990,7 @@ struct drm_i915_private {
 	struct workqueue_struct *flip_wq;
 
 	/* pm private clock gating functions */
-	struct drm_i915_cg_funcs cg_funcs;
+	const struct drm_i915_cg_funcs *cg_funcs;
 
 	/* pm display functions */
 	struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7a457646fb84..44f5582531ac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
 
 void intel_init_clock_gating(struct drm_i915_private *dev_priv)
 {
-	dev_priv->cg_funcs.init_clock_gating(dev_priv);
+	dev_priv->cg_funcs->init_clock_gating(dev_priv);
 }
 
 void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 		    "No clock gating settings or workarounds applied.\n");
 }
 
+#define CG_FUNCS(platform) \
+static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
+	.init_clock_gating = platform##_init_clock_gating     \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+
 /**
  * intel_init_clock_gating_hooks - setup the clock gating hooks
  * @dev_priv: device private
@@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
 	if (IS_ALDERLAKE_P(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
+		dev_priv->cg_funcs = &adlp_cg_funcs;
 	else if (IS_DG1(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
+		dev_priv->cg_funcs = &dg1_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 12)
-		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
+		dev_priv->cg_funcs = &gen12lp_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 11)
-		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
+		dev_priv->cg_funcs = &icl_cg_funcs;
 	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
+		dev_priv->cg_funcs = &cfl_cg_funcs;
 	else if (IS_SKYLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
+		dev_priv->cg_funcs = &skl_cg_funcs;
 	else if (IS_KABYLAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
+		dev_priv->cg_funcs = &kbl_cg_funcs;
 	else if (IS_BROXTON(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
+		dev_priv->cg_funcs = &bxt_cg_funcs;
 	else if (IS_GEMINILAKE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
+		dev_priv->cg_funcs = &glk_cg_funcs;
 	else if (IS_BROADWELL(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
+		dev_priv->cg_funcs = &bdw_cg_funcs;
 	else if (IS_CHERRYVIEW(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
+		dev_priv->cg_funcs = &chv_cg_funcs;
 	else if (IS_HASWELL(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
+		dev_priv->cg_funcs = &hsw_cg_funcs;
 	else if (IS_IVYBRIDGE(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
+		dev_priv->cg_funcs = &ivb_cg_funcs;
 	else if (IS_VALLEYVIEW(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
+		dev_priv->cg_funcs = &vlv_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 6)
-		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
+		dev_priv->cg_funcs = &gen6_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 5)
-		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
+		dev_priv->cg_funcs = &ilk_cg_funcs;
 	else if (IS_G4X(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
+		dev_priv->cg_funcs = &g4x_cg_funcs;
 	else if (IS_I965GM(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
+		dev_priv->cg_funcs = &i965gm_cg_funcs;
 	else if (IS_I965G(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
+		dev_priv->cg_funcs = &i965g_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 3)
-		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
+		dev_priv->cg_funcs = &gen3_cg_funcs;
 	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
-		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
+		dev_priv->cg_funcs = &i85x_cg_funcs;
 	else if (GRAPHICS_VER(dev_priv) == 2)
-		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
+		dev_priv->cg_funcs = &i830_cg_funcs;
 	else {
 		MISSING_CASE(INTEL_DEVID(dev_priv));
-		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
+		dev_priv->cg_funcs = &nop_cg_funcs;
 	}
 }
 
-- 
2.31.1

[Intel-gfx] [PATCH 21/21] drm/i915: constify display wm vtable

[Dave Airlie]

From: Dave Airlie <airlied@redhat.com>

This adds some extra checks for the table pointer being
valid due to some paths not setting it due to failing
CxSR.
---
 drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++-------
 drivers/gpu/drm/i915/i915_drv.h              |  2 +-
 drivers/gpu/drm/i915/intel_pm.c              | 74 ++++++++++++++------
 3 files changed, 81 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 20fd35c6858c..a3d6ab0795a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
  */
 static void intel_update_watermarks(struct drm_i915_private *dev_priv)
 {
-	if (dev_priv->wm_disp.update_wm)
-		dev_priv->wm_disp.update_wm(dev_priv);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->update_wm)
+		dev_priv->wm_disp->update_wm(dev_priv);
 }
 
 /* returns HPLL frequency in kHz */
@@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
 		 * we'll continue to update watermarks the old way, if flags tell
 		 * us to.
 		 */
-		if (dev_priv->wm_disp.initial_watermarks)
-			dev_priv->wm_disp.initial_watermarks(state, crtc);
+		if (dev_priv->wm_disp->initial_watermarks)
+			dev_priv->wm_disp->initial_watermarks(state, crtc);
 		else if (new_crtc_state->update_wm_pre)
 			intel_update_watermarks(dev_priv);
 	}
@@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	if (dev_priv->wm_disp.initial_watermarks)
-		dev_priv->wm_disp.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp->initial_watermarks)
+		dev_priv->wm_disp->initial_watermarks(state, crtc);
 	intel_enable_pipe(new_crtc_state);
 
 	if (new_crtc_state->has_pch_encoder)
@@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(dev_priv) >= 11)
 		icl_set_pipe_chicken(new_crtc_state);
 
-	if (dev_priv->wm_disp.initial_watermarks)
-		dev_priv->wm_disp.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
+		dev_priv->wm_disp->initial_watermarks(state, crtc);
 
 	if (DISPLAY_VER(dev_priv) >= 11) {
 		const struct intel_dbuf_state *dbuf_state =
@@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	dev_priv->wm_disp.initial_watermarks(state, crtc);
+	dev_priv->wm_disp->initial_watermarks(state, crtc);
 	intel_enable_pipe(new_crtc_state);
 
 	intel_crtc_vblank_on(new_crtc_state);
@@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
 	/* update DSPCNTR to configure gamma for pipe bottom color */
 	intel_disable_primary_plane(new_crtc_state);
 
-	if (dev_priv->wm_disp.initial_watermarks)
-		dev_priv->wm_disp.initial_watermarks(state, crtc);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
+		dev_priv->wm_disp->initial_watermarks(state, crtc);
 	else
 		intel_update_watermarks(dev_priv);
 	intel_enable_pipe(new_crtc_state);
@@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
 	if (DISPLAY_VER(dev_priv) != 2)
 		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 
-	if (!dev_priv->wm_disp.initial_watermarks)
+	if (dev_priv->wm_disp && !dev_priv->wm_disp->initial_watermarks)
 		intel_update_watermarks(dev_priv);
 
 	/* clock the pipe down to 640x480@60 to potentially save power */
@@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 			return ret;
 	}
 
-	if (dev_priv->wm_disp.compute_pipe_wm) {
-		ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_pipe_wm) {
+		ret = dev_priv->wm_disp->compute_pipe_wm(state, crtc);
 		if (ret) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Target pipe watermarks are invalid\n");
@@ -6800,9 +6800,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 
 	}
 
-	if (dev_priv->wm_disp.compute_intermediate_wm) {
+	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_intermediate_wm) {
 		if (drm_WARN_ON(&dev_priv->drm,
-				!dev_priv->wm_disp.compute_pipe_wm))
+				!dev_priv->wm_disp->compute_pipe_wm))
 			return 0;
 
 		/*
@@ -6810,7 +6810,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
 		 * old state and the new state.  We can program these
 		 * immediately.
 		 */
-		ret = dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+		ret = dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
 		if (ret) {
 			drm_dbg_kms(&dev_priv->drm,
 				    "No valid intermediate pipe watermarks are possible\n");
@@ -8919,8 +8919,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
 	struct drm_i915_private *dev_priv = to_i915(dev);
 
 	/* Is there platform-specific watermark information to calculate? */
-	if (dev_priv->wm_disp.compute_global_watermarks)
-		return dev_priv->wm_disp.compute_global_watermarks(state);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_global_watermarks)
+		return dev_priv->wm_disp->compute_global_watermarks(state);
 
 	return 0;
 }
@@ -9745,8 +9745,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
 		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
 	}
 
-	if (dev_priv->wm_disp.atomic_update_watermarks)
-		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+	if (dev_priv->wm_disp && dev_priv->wm_disp->atomic_update_watermarks)
+		dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
 }
 
 static void commit_pipe_post_planes(struct intel_atomic_state *state,
@@ -9874,8 +9874,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
 	/* FIXME unify this for all platforms */
 	if (!new_crtc_state->hw.active &&
 	    !HAS_GMCH(dev_priv) &&
-	    dev_priv->wm_disp.initial_watermarks)
-		dev_priv->wm_disp.initial_watermarks(state, crtc);
+	    dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
+		dev_priv->wm_disp->initial_watermarks(state, crtc);
 }
 
 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
@@ -10297,8 +10297,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
 
-		if (dev_priv->wm_disp.optimize_watermarks)
-			dev_priv->wm_disp.optimize_watermarks(state, crtc);
+		if (dev_priv->wm_disp && dev_priv->wm_disp->optimize_watermarks)
+			dev_priv->wm_disp->optimize_watermarks(state, crtc);
 	}
 
 	intel_dbuf_post_plane_update(state);
@@ -11387,7 +11387,9 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
 	int i;
 
 	/* Only supported on platforms that use atomic watermark design */
-	if (!dev_priv->wm_disp.optimize_watermarks)
+	if (!dev_priv->wm_disp)
+		return;
+	if (!dev_priv->wm_disp->optimize_watermarks)
 		return;
 
 	state = drm_atomic_state_alloc(&dev_priv->drm);
@@ -11420,7 +11422,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
 	/* Write calculated watermark values back */
 	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
 		crtc_state->wm.need_postvbl_update = true;
-		dev_priv->wm_disp.optimize_watermarks(intel_state, crtc);
+		dev_priv->wm_disp->optimize_watermarks(intel_state, crtc);
 
 		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
 	}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44094a25a110..eacd30c076a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -993,7 +993,7 @@ struct drm_i915_private {
 	const struct drm_i915_cg_funcs *cg_funcs;
 
 	/* pm display functions */
-	struct drm_i915_wm_disp_funcs wm_disp;
+	const struct drm_i915_wm_disp_funcs *wm_disp;
 
 	/* irq display functions */
 	const struct drm_i915_irq_funcs *irq_funcs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 44f5582531ac..cceeb059f801 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7976,6 +7976,48 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 	}
 }
 
+static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
+	.compute_global_watermarks = skl_compute_wm
+};
+
+static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
+	.compute_pipe_wm = ilk_compute_pipe_wm,
+	.compute_intermediate_wm = ilk_compute_intermediate_wm,
+	.initial_watermarks = ilk_initial_watermarks,
+	.optimize_watermarks = ilk_optimize_watermarks
+};
+
+static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
+	.compute_pipe_wm = vlv_compute_pipe_wm,
+	.compute_intermediate_wm = vlv_compute_intermediate_wm,
+	.initial_watermarks = vlv_initial_watermarks,
+	.optimize_watermarks = vlv_optimize_watermarks,
+	.atomic_update_watermarks = vlv_atomic_update_fifo
+};
+
+static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
+	.compute_pipe_wm = g4x_compute_pipe_wm,
+	.compute_intermediate_wm = g4x_compute_intermediate_wm,
+	.initial_watermarks = g4x_initial_watermarks,
+	.optimize_watermarks = g4x_optimize_watermarks
+};
+
+static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
+	.update_wm = pnv_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
+	.update_wm = i965_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
+	.update_wm = i9xx_update_wm,
+};
+
+static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
+	.update_wm = i845_update_wm,
+};
+
 /* Set up chip specific power management-related functions */
 void intel_init_pm(struct drm_i915_private *dev_priv)
 {
@@ -7991,7 +8033,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 	/* For FIFO watermark updates */
 	if (DISPLAY_VER(dev_priv) >= 9) {
 		skl_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
+		dev_priv->wm_disp = &skl_wm_funcs;
 	} else if (HAS_PCH_SPLIT(dev_priv)) {
 		ilk_setup_wm_latency(dev_priv);
 
@@ -7999,13 +8041,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
 		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
 		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
-			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
-			dev_priv->wm_disp.compute_intermediate_wm =
-				ilk_compute_intermediate_wm;
-			dev_priv->wm_disp.initial_watermarks =
-				ilk_initial_watermarks;
-			dev_priv->wm_disp.optimize_watermarks =
-				ilk_optimize_watermarks;
+			dev_priv->wm_disp = &ilk_wm_funcs;
 		} else {
 			drm_dbg_kms(&dev_priv->drm,
 				    "Failed to read display plane latency. "
@@ -8013,17 +8049,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 		}
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		vlv_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
-		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
-		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
-		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
-		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
+		dev_priv->wm_disp = &vlv_wm_funcs;
 	} else if (IS_G4X(dev_priv)) {
 		g4x_setup_wm_latency(dev_priv);
-		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
-		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
-		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
-		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
+		dev_priv->wm_disp = &g4x_wm_funcs;
 	} else if (IS_PINEVIEW(dev_priv)) {
 		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
 					    dev_priv->is_ddr3,
@@ -8037,18 +8066,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
 				 dev_priv->fsb_freq, dev_priv->mem_freq);
 			/* Disable CxSR and never update its watermark again */
 			intel_set_memory_cxsr(dev_priv, false);
-			dev_priv->wm_disp.update_wm = NULL;
 		} else
-			dev_priv->wm_disp.update_wm = pnv_update_wm;
+			dev_priv->wm_disp = &pnv_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 4) {
-		dev_priv->wm_disp.update_wm = i965_update_wm;
+		dev_priv->wm_disp = &i965_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 3) {
-		dev_priv->wm_disp.update_wm = i9xx_update_wm;
+		dev_priv->wm_disp = &i9xx_wm_funcs;
 	} else if (DISPLAY_VER(dev_priv) == 2) {
 		if (INTEL_NUM_PIPES(dev_priv) == 1)
-			dev_priv->wm_disp.update_wm = i845_update_wm;
+			dev_priv->wm_disp = &i845_wm_funcs;
 		else
-			dev_priv->wm_disp.update_wm = i9xx_update_wm;
+			dev_priv->wm_disp = &i9xx_wm_funcs;
 	} else {
 		drm_err(&dev_priv->drm,
 			"unexpected fall-through in %s\n", __func__);
-- 
2.31.1

Re: [Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[David Airlie]

On Wed, Sep 8, 2021 at 10:39 AM Dave Airlie <airlied@gmail.com> wrote:
>
> From: Dave Airlie <airlied@redhat.com>
>
> The crtc was never being used here.

/me realises I've noobed up the Sob on these,

I've added them to my tree locally and in the branch I posted to the
other thread., if there are comments/no comments I'll add them in a
respin tomorrow.

Dave.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915/display: split and constify vtable

[Patchwork]

== Series Details ==

Series: i915/display: split and constify vtable
URL   : https://patchwork.freedesktop.org/series/94459/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
7166501ad5c5 drm/i915/pm: drop get_fifo_size vfunc.
7d63620c3a3c drm/i915: make update_wm take a dev_priv.
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:145: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 110 lines checked
4f0dcfddaf55 drm/i915/wm: move the update watermark wrapper to display side.
-:25: CHECK:LINE_SPACING: Please don't use multiple blank lines
#25: FILE: drivers/gpu/drm/i915/display/intel_display.c:129:
 
+

-:129: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 1 checks, 98 lines checked
f7fd8b9b66d8 drm/i915: split clock gating init from display vtable
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:130: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 110 lines checked
fa9489128d12 drm/i915: split watermark vfuncs from display vtable.
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:309: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 267 lines checked
8e12abc84eee drm/i915: split color functions from display vtable
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:190: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 169 lines checked
f04a4c66375c drm/i915: split audio functions from display vtable
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:103: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 82 lines checked
38cdd3a1eb3b drm/i915: split cdclk functions from display vtable.
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:335: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 298 lines checked
058f5bcb4112 drm/i915: split irq hotplug function from display vtable
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:88: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 64 lines checked
079b3659abea drm/i915: split fdi link training from display vtable.
-:77: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 51 lines checked
c6679bffd83a drm/i915: split the dpll clock compute out from display vtable.
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:101: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 75 lines checked
a68de81479ab drm/i915: constify fdi link training vtable
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:68: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 46 lines checked
a022a66bdb74 drm/i915: constify irq function vtable.
-:88: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 64 lines checked
8715b614793b drm/i915: constify color function vtable.
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:189: CHECK:BRACES: Unbalanced braces around else statement
#189: FILE: drivers/gpu/drm/i915/display/intel_color.c:2194:
+		} else

-:206: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 1 checks, 187 lines checked
bc7d25d0b5a8 drm/i915: constify the audio function vtable
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:97: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 78 lines checked
7afd7fa26e62 drm/i915: constify the dpll clock vtable
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:73: CHECK:LINE_SPACING: Please don't use multiple blank lines
#73: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1398:
+
+

-:116: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 1 checks, 94 lines checked
19452e67e3f5 drm/i915: constify the cdclk vtable
-:458: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 420 lines checked
cd09b1003483 drm/i915: drop unused function ptr and comments.
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:25: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 13 lines checked
0aa6560d6dc0 drm/i915: constify display function vtable
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:168: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 145 lines checked
c38e95658801 drm/i915: constify clock gating init vtable.
-:9: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

-:145: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 1 warnings, 0 checks, 126 lines checked
ee4bac229f7f drm/i915: constify display wm vtable
-:316: ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 0 checks, 273 lines checked

[Intel-gfx] ✗ Fi.CI.DOCS: warning for i915/display: split and constify vtable

[Patchwork]

== Series Details ==

Series: i915/display: split and constify vtable
URL   : https://patchwork.freedesktop.org/series/94459/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_display.c:164: warning: Excess function parameter 'crtc' description in 'intel_update_watermarks'

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/display: split and constify vtable

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6776 bytes --]

== Series Details ==

Series: i915/display: split and constify vtable
URL   : https://patchwork.freedesktop.org/series/94459/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10560 -> Patchwork_20985
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/index.html

Known issues
------------

  Here are the changes found in Patchwork_20985 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-bwr-2160:        [PASS][2] -> [FAIL][3] ([i915#3194])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_fence@basic-busy@bcs0:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271]) +6 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-skl-guc:         [PASS][6] -> [DMESG-FAIL][7] ([i915#2291] / [i915#541])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-skl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][9] ([fdo#109271]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-bdw-5557u/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
    - fi-kbl-r:           NOTRUN -> [FAIL][13] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-kbl-r/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - fi-snb-2600:        [INCOMPLETE][14] ([i915#3921]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
  [i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541


Participating hosts (47 -> 40)
------------------------------

  Missing    (7): fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10560 -> Patchwork_20985

  CI-20190529: 20190529
  CI_DRM_10560: 63f1c18cef9bcc5b23cd41b9d85399db7d40e3dd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6199: 831085fb82f5b34e17f398a0af8eaa8c509e0fad @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_20985: ee4bac229f7fdb820729075ff3bd23e64709412f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ee4bac229f7f drm/i915: constify display wm vtable
c38e95658801 drm/i915: constify clock gating init vtable.
0aa6560d6dc0 drm/i915: constify display function vtable
cd09b1003483 drm/i915: drop unused function ptr and comments.
19452e67e3f5 drm/i915: constify the cdclk vtable
7afd7fa26e62 drm/i915: constify the dpll clock vtable
bc7d25d0b5a8 drm/i915: constify the audio function vtable
8715b614793b drm/i915: constify color function vtable.
a022a66bdb74 drm/i915: constify irq function vtable.
a68de81479ab drm/i915: constify fdi link training vtable
c6679bffd83a drm/i915: split the dpll clock compute out from display vtable.
079b3659abea drm/i915: split fdi link training from display vtable.
058f5bcb4112 drm/i915: split irq hotplug function from display vtable
38cdd3a1eb3b drm/i915: split cdclk functions from display vtable.
f04a4c66375c drm/i915: split audio functions from display vtable
8e12abc84eee drm/i915: split color functions from display vtable
fa9489128d12 drm/i915: split watermark vfuncs from display vtable.
f7fd8b9b66d8 drm/i915: split clock gating init from display vtable
4f0dcfddaf55 drm/i915/wm: move the update watermark wrapper to display side.
7d63620c3a3c drm/i915: make update_wm take a dev_priv.
7166501ad5c5 drm/i915/pm: drop get_fifo_size vfunc.

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/index.html

[-- Attachment #2: Type: text/html, Size: 8302 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for i915/display: split and constify vtable

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30262 bytes --]

== Series Details ==

Series: i915/display: split and constify vtable
URL   : https://patchwork.freedesktop.org/series/94459/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10560_full -> Patchwork_20985_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_20985_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@psr2:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([i915#658])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@feature_discovery@psr2.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb7/igt@feature_discovery@psr2.html

  * igt@gem_ctx_persistence@engines-hostile:
    - shard-snb:          NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +4 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-snb5/igt@gem_ctx_persistence@engines-hostile.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#2846])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk2/igt@gem_exec_fair@basic-deadline.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk3/igt@gem_exec_fair@basic-deadline.html
    - shard-apl:          NOTRUN -> [FAIL][6] ([i915#2846])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl3/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         NOTRUN -> [FAIL][7] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk4/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb2/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][12] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_params@no-vebox:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([fdo#109283])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_exec_params@no-vebox.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [PASS][16] -> [SKIP][17] ([i915#2190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb2/igt@gem_huc_copy@huc-copy.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb6/igt@gem_huc_copy@huc-copy.html

  * igt@gem_mmap_gtt@cpuset-big-copy-xy:
    - shard-iclb:         [PASS][18] -> [FAIL][19] ([i915#2428])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb5/igt@gem_mmap_gtt@cpuset-big-copy-xy.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb8/igt@gem_mmap_gtt@cpuset-big-copy-xy.html

  * igt@gem_pread@exhaustion:
    - shard-tglb:         NOTRUN -> [WARN][20] ([i915#2658])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-apl:          NOTRUN -> [WARN][21] ([i915#2658])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglb:         NOTRUN -> [SKIP][22] ([fdo#110542])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-skl:          NOTRUN -> [DMESG-WARN][23] ([i915#3002])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@gem_userptr_blits@input-checking.html

  * igt@gem_userptr_blits@vma-merge:
    - shard-apl:          NOTRUN -> [FAIL][24] ([i915#3318])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl8/igt@gem_userptr_blits@vma-merge.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([i915#456])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb8/igt@gem_workarounds@suspend-resume-fd.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen7_exec_parse@basic-rejected:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([fdo#109289]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@gen7_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-snb:          NOTRUN -> [SKIP][28] ([fdo#109271]) +503 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-snb2/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          NOTRUN -> [FAIL][29] ([i915#454])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-apl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#1937])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-tglb:         NOTRUN -> [WARN][31] ([i915#2681] / [i915#2684])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][32] ([fdo#109288])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@forcewake:
    - shard-tglb:         [PASS][33] -> [INCOMPLETE][34] ([i915#2411] / [i915#456]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb5/igt@i915_suspend@forcewake.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@i915_suspend@forcewake.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#111614])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][36] ([i915#3722]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-skl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([fdo#111615]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][40] ([i915#3689]) +7 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +6 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3886]) +18 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl8/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +26 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl7/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium@hdmi-hpd-storm-disable:
    - shard-skl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +7 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@kms_chamelium@hdmi-hpd-storm-disable.html

  * igt@kms_color@pipe-a-ctm-0-75:
    - shard-skl:          [PASS][46] -> [DMESG-WARN][47] ([i915#1982]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl5/igt@kms_color@pipe-a-ctm-0-75.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl8/igt@kms_color@pipe-a-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-d-ctm-limited-range:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([fdo#109284] / [fdo#111827]) +6 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-snb:          NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +29 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-snb5/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#3116])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][51] ([i915#1319]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][52] ([i915#3319])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - shard-skl:          NOTRUN -> [FAIL][53] ([i915#3444])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-snb:          NOTRUN -> [FAIL][54] ([i915#4024])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109278] / [fdo#109279])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb6/igt@kms_cursor_crc@pipe-c-cursor-512x512-onscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][56] ([i915#3359]) +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#109279] / [i915#3359]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][58] ([fdo#111825]) +22 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-skl:          NOTRUN -> [FAIL][59] ([i915#2346] / [i915#533])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-skl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_dsc@xrgb8888-dsc-compression:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#3828])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_dsc@xrgb8888-dsc-compression.html

  * igt@kms_flip@flip-vs-expired-vblank@c-dp1:
    - shard-apl:          NOTRUN -> [FAIL][62] ([i915#79])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl8/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][63] -> [DMESG-WARN][64] ([i915#180]) +4 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][65] -> [DMESG-WARN][66] ([i915#180]) +1 similar issue
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1:
    - shard-glk:          [PASS][67] -> [FAIL][68] ([i915#407])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk2/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk8/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-hdmi-a1.html

  * igt@kms_flip@plain-flip-fb-recreate@b-edp1:
    - shard-skl:          [PASS][69] -> [FAIL][70] ([i915#2122]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
    - shard-skl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#2672])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][72] ([i915#180])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl8/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-skl:          NOTRUN -> [SKIP][73] ([fdo#109271]) +91 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][74] -> [FAIL][75] ([i915#1188])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl5/igt@kms_hdr@bpc-switch-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl8/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][76] ([fdo#108145] / [i915#265]) +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][77] -> [FAIL][78] ([fdo#108145] / [i915#265]) +1 similar issue
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-apl:          NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265]) +2 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_lowres@pipe-a-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][80] ([fdo#112054])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@kms_plane_lowres@pipe-a-tiling-yf.html

  * igt@kms_plane_lowres@pipe-d-tiling-y:
    - shard-tglb:         NOTRUN -> [SKIP][81] ([i915#3536]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_plane_lowres@pipe-d-tiling-y.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#2733])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
    - shard-skl:          NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658]) +2 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
    - shard-apl:          NOTRUN -> [SKIP][84] ([fdo#109271] / [i915#658]) +5 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl1/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2920]) +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][86] -> [SKIP][87] ([fdo#109441]) +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb8/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@psr2_suspend:
    - shard-tglb:         NOTRUN -> [FAIL][88] ([i915#132] / [i915#3467]) +1 similar issue
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_psr@psr2_suspend.html

  * igt@kms_sysfs_edid_timing:
    - shard-apl:          NOTRUN -> [FAIL][89] ([IGT#2])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl2/igt@kms_sysfs_edid_timing.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-apl:          NOTRUN -> [SKIP][90] ([fdo#109271]) +325 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl7/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_writeback@writeback-check-output:
    - shard-skl:          NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl3/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-d-source-outp-inactive:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([i915#2530]) +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@nouveau_crc@pipe-d-source-outp-inactive.html
    - shard-iclb:         NOTRUN -> [SKIP][93] ([fdo#109278] / [i915#2530])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb6/igt@nouveau_crc@pipe-d-source-outp-inactive.html

  * igt@prime_nv_pcopy@test3_3:
    - shard-tglb:         NOTRUN -> [SKIP][94] ([fdo#109291]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@prime_nv_pcopy@test3_3.html

  * igt@sysfs_clients@fair-3:
    - shard-tglb:         NOTRUN -> [SKIP][95] ([i915#2994])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@sysfs_clients@fair-3.html

  * igt@sysfs_clients@recycle-many:
    - shard-skl:          NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@sysfs_clients@recycle-many.html

  * igt@sysfs_clients@sema-50:
    - shard-apl:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994]) +2 similar issues
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl6/igt@sysfs_clients@sema-50.html

  * igt@sysfs_heartbeat_interval@mixed@rcs0:
    - shard-skl:          [PASS][98] -> [FAIL][99] ([i915#1731])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl2/igt@sysfs_heartbeat_interval@mixed@rcs0.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl5/igt@sysfs_heartbeat_interval@mixed@rcs0.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-tglb:         NOTRUN -> [SKIP][100] ([fdo#109307])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb7/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-none@rcs0:
    - shard-kbl:          [FAIL][101] ([i915#2842]) -> [PASS][102] +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-kbl1/igt@gem_exec_fair@basic-none@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][103] ([i915#2842]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][105] ([i915#2849]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_softpin@noreloc-s3:
    - shard-tglb:         [INCOMPLETE][107] ([i915#1373] / [i915#456]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb7/igt@gem_softpin@noreloc-s3.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb1/igt@gem_softpin@noreloc-s3.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-skl:          [DMESG-WARN][109] ([i915#1436] / [i915#716]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl4/igt@gen9_exec_parse@allowed-single.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl2/igt@gen9_exec_parse@allowed-single.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][111] ([i915#118] / [i915#95]) -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk1/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html

  * igt@kms_color@pipe-c-ctm-0-5:
    - shard-skl:          [DMESG-WARN][113] ([i915#1982]) -> [PASS][114] +1 similar issue
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl7/igt@kms_color@pipe-c-ctm-0-5.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl6/igt@kms_color@pipe-c-ctm-0-5.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][115] ([i915#2411] / [i915#456]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][117] ([i915#79]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-apl:          [DMESG-WARN][119] ([i915#180]) -> [PASS][120]
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
    - shard-skl:          [INCOMPLETE][121] ([i915#198]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
    - shard-skl:          [FAIL][123] ([i915#2122]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][125] ([fdo#109441]) -> [PASS][126] +2 similar issues
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb3/igt@kms_psr@psr2_no_drrs.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][127] ([i915#2842]) -> [FAIL][128] ([i915#2852])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][129] ([i915#658]) -> [SKIP][130] ([i915#588])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [FAIL][131] ([i915#3343]) -> [SKIP][132] ([i915#3288])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][133] ([i915#658]) -> [SKIP][134] ([i915#2920]) +1 similar issue
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
    - shard-iclb:         [SKIP][135] ([i915#2920]) -> [SKIP][136] ([i915#658]) +1 similar issue
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-iclb7/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][137], [FAIL][138]) ([i915#3002] / [i915#3363]) -> ([FAIL][139], [FAIL][140], [FAIL][141]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3363])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-kbl4/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10560/shard-kbl2/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-kbl7/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-kbl7/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/shard-kbl7/igt@runner@aborted.html
    - shard-apl:          ([FAIL][142], [FAIL][143], [FAIL][144

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20985/index.html

[-- Attachment #2: Type: text/html, Size: 33629 bytes --]

Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> A vague goal is to have the vfunc table be the api between
> wm and display, not having direction function calls cross
> the boundary.
>
> This aligns the legacy update_wm with the newer vfuncs.
>
> The comment probably needs to live somewhere else, it seems
> like it should live in the pm side though not the display side,
> but I brought it along for the ride.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c              | 39 -------------------
>  drivers/gpu/drm/i915/intel_pm.h              |  1 -
>  3 files changed, 40 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d95283bf2631..b495371c1889 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c

We haven't been axing stuff out of intel_display.c so we could add
somethign else back! ;)

A new file for watermarks or display pm? Ville?

BR,
Jani.



> @@ -125,6 +125,46 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
>  static void intel_modeset_setup_hw_state(struct drm_device *dev,
>  					 struct drm_modeset_acquire_ctx *ctx);
>  
> +
> +/**
> + * intel_update_watermarks - update FIFO watermark values based on current modes
> + * @crtc: the #intel_crtc on which to compute the WM
> + *
> + * Calculate watermark values for the various WM regs based on current mode
> + * and plane configuration.
> + *
> + * There are several cases to deal with here:
> + *   - normal (i.e. non-self-refresh)
> + *   - self-refresh (SR) mode
> + *   - lines are large relative to FIFO size (buffer can hold up to 2)
> + *   - lines are small relative to FIFO size (buffer can hold more than 2
> + *     lines), so need to account for TLB latency
> + *
> + *   The normal calculation is:
> + *     watermark = dotclock * bytes per pixel * latency
> + *   where latency is platform & configuration dependent (we assume pessimal
> + *   values here).
> + *
> + *   The SR calculation is:
> + *     watermark = (trunc(latency/line time)+1) * surface width *
> + *       bytes per pixel
> + *   where
> + *     line time = htotal / dotclock
> + *     surface width = hdisplay for normal plane and 64 for cursor
> + *   and latency is assumed to be high, as above.
> + *
> + * The final value programmed to the register should always be rounded up,
> + * and include an extra 2 entries to account for clock crossings.
> + *
> + * We don't use the sprite, so we can ignore that.  And on Crestline we have
> + * to set the non-SR watermarks to 8.
> + */
> +static void intel_update_watermarks(struct drm_i915_private *dev_priv)
> +{
> +	if (dev_priv->display.update_wm)
> +		dev_priv->display.update_wm(dev_priv);
> +}
> +
>  /* returns HPLL frequency in kHz */
>  int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 406baa49e6ad..4054c6f7a2f9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7132,45 +7132,6 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
>  }
>  
> -/**
> - * intel_update_watermarks - update FIFO watermark values based on current modes
> - * @crtc: the #intel_crtc on which to compute the WM
> - *
> - * Calculate watermark values for the various WM regs based on current mode
> - * and plane configuration.
> - *
> - * There are several cases to deal with here:
> - *   - normal (i.e. non-self-refresh)
> - *   - self-refresh (SR) mode
> - *   - lines are large relative to FIFO size (buffer can hold up to 2)
> - *   - lines are small relative to FIFO size (buffer can hold more than 2
> - *     lines), so need to account for TLB latency
> - *
> - *   The normal calculation is:
> - *     watermark = dotclock * bytes per pixel * latency
> - *   where latency is platform & configuration dependent (we assume pessimal
> - *   values here).
> - *
> - *   The SR calculation is:
> - *     watermark = (trunc(latency/line time)+1) * surface width *
> - *       bytes per pixel
> - *   where
> - *     line time = htotal / dotclock
> - *     surface width = hdisplay for normal plane and 64 for cursor
> - *   and latency is assumed to be high, as above.
> - *
> - * The final value programmed to the register should always be rounded up,
> - * and include an extra 2 entries to account for clock crossings.
> - *
> - * We don't use the sprite, so we can ignore that.  And on Crestline we have
> - * to set the non-SR watermarks to 8.
> - */
> -void intel_update_watermarks(struct drm_i915_private *dev_priv)
> -{
> -	if (dev_priv->display.update_wm)
> -		dev_priv->display.update_wm(dev_priv);
> -}
> -
>  void intel_enable_ipc(struct drm_i915_private *dev_priv)
>  {
>  	u32 val;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 99bce0b4f5fb..990cdcaf85ce 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -29,7 +29,6 @@ struct skl_wm_level;
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv);
>  void intel_suspend_hw(struct drm_i915_private *dev_priv);
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> -void intel_update_watermarks(struct drm_i915_private *dev_priv);
>  void intel_init_pm(struct drm_i915_private *dev_priv);
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>  void intel_pm_setup(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 05/21] drm/i915: split watermark vfuncs from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> These are the watermark api between display and pm.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 54 ++++++++++----------
>  drivers/gpu/drm/i915/i915_drv.h              | 24 ++++++---
>  drivers/gpu/drm/i915/intel_pm.c              | 40 +++++++--------
>  3 files changed, 63 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b495371c1889..b1202ede3fb0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
>   */
>  static void intel_update_watermarks(struct drm_i915_private *dev_priv)
>  {
> -	if (dev_priv->display.update_wm)
> -		dev_priv->display.update_wm(dev_priv);
> +	if (dev_priv->wm_disp.update_wm)
> +		dev_priv->wm_disp.update_wm(dev_priv);
>  }
>  
>  /* returns HPLL frequency in kHz */
> @@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  		 * we'll continue to update watermarks the old way, if flags tell
>  		 * us to.
>  		 */
> -		if (dev_priv->display.initial_watermarks)
> -			dev_priv->display.initial_watermarks(state, crtc);
> +		if (dev_priv->wm_disp.initial_watermarks)
> +			dev_priv->wm_disp.initial_watermarks(state, crtc);
>  		else if (new_crtc_state->update_wm_pre)
>  			intel_update_watermarks(dev_priv);

Having an intel_initial_watermarks() wrapper similar to
intel_update_watermarks() to do the vfunc call would make this patch
nice and tidy.


>  	}
> @@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp.initial_watermarks)
> +		dev_priv->wm_disp.initial_watermarks(state, crtc);
>  	intel_enable_pipe(new_crtc_state);
>  
>  	if (new_crtc_state->has_pch_encoder)
> @@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>  	if (DISPLAY_VER(dev_priv) >= 11)
>  		icl_set_pipe_chicken(new_crtc_state);
>  
> -	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp.initial_watermarks)
> +		dev_priv->wm_disp.initial_watermarks(state, crtc);
>  
>  	if (DISPLAY_VER(dev_priv) >= 11) {
>  		const struct intel_dbuf_state *dbuf_state =
> @@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	dev_priv->display.initial_watermarks(state, crtc);
> +	dev_priv->wm_disp.initial_watermarks(state, crtc);
>  	intel_enable_pipe(new_crtc_state);
>  
>  	intel_crtc_vblank_on(new_crtc_state);
> @@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	if (dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp.initial_watermarks)
> +		dev_priv->wm_disp.initial_watermarks(state, crtc);
>  	else
>  		intel_update_watermarks(dev_priv);
>  	intel_enable_pipe(new_crtc_state);
> @@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
>  	if (DISPLAY_VER(dev_priv) != 2)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> -	if (!dev_priv->display.initial_watermarks)
> +	if (!dev_priv->wm_disp.initial_watermarks)
>  		intel_update_watermarks(dev_priv);
>  
>  	/* clock the pipe down to 640x480@60 to potentially save power */
> @@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  			return ret;
>  	}
>  
> -	if (dev_priv->display.compute_pipe_wm) {
> -		ret = dev_priv->display.compute_pipe_wm(state, crtc);
> +	if (dev_priv->wm_disp.compute_pipe_wm) {
> +		ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
>  		if (ret) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "Target pipe watermarks are invalid\n");
> @@ -6800,9 +6800,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  
>  	}
>  
> -	if (dev_priv->display.compute_intermediate_wm) {
> +	if (dev_priv->wm_disp.compute_intermediate_wm) {
>  		if (drm_WARN_ON(&dev_priv->drm,
> -				!dev_priv->display.compute_pipe_wm))
> +				!dev_priv->wm_disp.compute_pipe_wm))
>  			return 0;
>  
>  		/*
> @@ -6810,7 +6810,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		 * old state and the new state.  We can program these
>  		 * immediately.
>  		 */
> -		ret = dev_priv->display.compute_intermediate_wm(state, crtc);
> +		ret = dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
>  		if (ret) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "No valid intermediate pipe watermarks are possible\n");
> @@ -8919,8 +8919,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	/* Is there platform-specific watermark information to calculate? */
> -	if (dev_priv->display.compute_global_watermarks)
> -		return dev_priv->display.compute_global_watermarks(state);
> +	if (dev_priv->wm_disp.compute_global_watermarks)
> +		return dev_priv->wm_disp.compute_global_watermarks(state);

Ditto all over the place.

As an overall design and style guide, I think I'm starting to lean
towards always requiring a wrapper for calling vfuncs. The one exception
might be calls completely internal to a file, and we do have them a lot
too.

But in this case, everything that gets called from intel_display.c I
think should have a wrapper, so we can hide the implementation details
and maintain a decent API.

>  
>  	return 0;
>  }
> @@ -9745,8 +9745,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
>  		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
>  	}
>  
> -	if (dev_priv->display.atomic_update_watermarks)
> -		dev_priv->display.atomic_update_watermarks(state, crtc);
> +	if (dev_priv->wm_disp.atomic_update_watermarks)
> +		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
>  }
>  
>  static void commit_pipe_post_planes(struct intel_atomic_state *state,
> @@ -9874,8 +9874,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	/* FIXME unify this for all platforms */
>  	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
> -	    dev_priv->display.initial_watermarks)
> -		dev_priv->display.initial_watermarks(state, crtc);
> +	    dev_priv->wm_disp.initial_watermarks)
> +		dev_priv->wm_disp.initial_watermarks(state, crtc);
>  }
>  
>  static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> @@ -10297,8 +10297,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
>  			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>  
> -		if (dev_priv->display.optimize_watermarks)
> -			dev_priv->display.optimize_watermarks(state, crtc);
> +		if (dev_priv->wm_disp.optimize_watermarks)
> +			dev_priv->wm_disp.optimize_watermarks(state, crtc);
>  	}
>  
>  	intel_dbuf_post_plane_update(state);
> @@ -11366,7 +11366,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
>  	int i;
>  
>  	/* Only supported on platforms that use atomic watermark design */
> -	if (!dev_priv->display.optimize_watermarks)
> +	if (!dev_priv->wm_disp.optimize_watermarks)
>  		return;
>  
>  	state = drm_atomic_state_alloc(&dev_priv->drm);
> @@ -11399,7 +11399,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
>  	/* Write calculated watermark values back */
>  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>  		crtc_state->wm.need_postvbl_update = true;
> -		dev_priv->display.optimize_watermarks(intel_state, crtc);
> +		dev_priv->wm_disp.optimize_watermarks(intel_state, crtc);
>  
>  		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b93fa19892b5..2beee62bfb91 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -328,13 +328,10 @@ struct drm_i915_cg_funcs {
>  	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
>  };
>  
> -struct drm_i915_display_funcs {
> -	void (*get_cdclk)(struct drm_i915_private *dev_priv,
> -			  struct intel_cdclk_config *cdclk_config);
> -	void (*set_cdclk)(struct drm_i915_private *dev_priv,
> -			  const struct intel_cdclk_config *cdclk_config,
> -			  enum pipe pipe);
> -	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
> +/* functions used for watermark calcs for display. */
> +struct drm_i915_wm_disp_funcs {
> +	/* update_wm is for legacy wm management */
> +	void (*update_wm)(struct drm_i915_private *dev_priv);
>  	int (*compute_pipe_wm)(struct intel_atomic_state *state,
>  			       struct intel_crtc *crtc);
>  	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
> @@ -346,7 +343,15 @@ struct drm_i915_display_funcs {
>  	void (*optimize_watermarks)(struct intel_atomic_state *state,
>  				    struct intel_crtc *crtc);
>  	int (*compute_global_watermarks)(struct intel_atomic_state *state);
> -	void (*update_wm)(struct drm_i915_private *dev_priv);
> +};
> +
> +struct drm_i915_display_funcs {
> +	void (*get_cdclk)(struct drm_i915_private *dev_priv,
> +			  struct intel_cdclk_config *cdclk_config);
> +	void (*set_cdclk)(struct drm_i915_private *dev_priv,
> +			  const struct intel_cdclk_config *cdclk_config,
> +			  enum pipe pipe);
> +	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
>  	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>  	u8 (*calc_voltage_level)(int cdclk);
>  	/* Returns the active state of the crtc, and if the crtc is active,
> @@ -976,6 +981,9 @@ struct drm_i915_private {
>  	/* pm private clock gating functions */
>  	struct drm_i915_cg_funcs cg_funcs;
>  
> +	/* pm display functions */
> +	struct drm_i915_wm_disp_funcs wm_disp;
> +
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 73549e774881..7a457646fb84 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7962,7 +7962,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  	/* For FIFO watermark updates */
>  	if (DISPLAY_VER(dev_priv) >= 9) {
>  		skl_setup_wm_latency(dev_priv);
> -		dev_priv->display.compute_global_watermarks = skl_compute_wm;
> +		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		ilk_setup_wm_latency(dev_priv);
>  
> @@ -7970,12 +7970,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
>  		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
>  		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> -			dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> -			dev_priv->display.compute_intermediate_wm =
> +			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
> +			dev_priv->wm_disp.compute_intermediate_wm =
>  				ilk_compute_intermediate_wm;
> -			dev_priv->display.initial_watermarks =
> +			dev_priv->wm_disp.initial_watermarks =
>  				ilk_initial_watermarks;
> -			dev_priv->display.optimize_watermarks =
> +			dev_priv->wm_disp.optimize_watermarks =
>  				ilk_optimize_watermarks;
>  		} else {
>  			drm_dbg_kms(&dev_priv->drm,
> @@ -7984,17 +7984,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		}
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		vlv_setup_wm_latency(dev_priv);
> -		dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;
> -		dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;
> -		dev_priv->display.initial_watermarks = vlv_initial_watermarks;
> -		dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;
> -		dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;
> +		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
> +		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
> +		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
> +		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
> +		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
>  	} else if (IS_G4X(dev_priv)) {
>  		g4x_setup_wm_latency(dev_priv);
> -		dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;
> -		dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;
> -		dev_priv->display.initial_watermarks = g4x_initial_watermarks;
> -		dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;
> +		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
> +		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
> +		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
> +		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
>  	} else if (IS_PINEVIEW(dev_priv)) {
>  		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
>  					    dev_priv->is_ddr3,
> @@ -8008,18 +8008,18 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  				 dev_priv->fsb_freq, dev_priv->mem_freq);
>  			/* Disable CxSR and never update its watermark again */
>  			intel_set_memory_cxsr(dev_priv, false);
> -			dev_priv->display.update_wm = NULL;
> +			dev_priv->wm_disp.update_wm = NULL;
>  		} else
> -			dev_priv->display.update_wm = pnv_update_wm;
> +			dev_priv->wm_disp.update_wm = pnv_update_wm;
>  	} else if (DISPLAY_VER(dev_priv) == 4) {
> -		dev_priv->display.update_wm = i965_update_wm;
> +		dev_priv->wm_disp.update_wm = i965_update_wm;
>  	} else if (DISPLAY_VER(dev_priv) == 3) {
> -		dev_priv->display.update_wm = i9xx_update_wm;
> +		dev_priv->wm_disp.update_wm = i9xx_update_wm;
>  	} else if (DISPLAY_VER(dev_priv) == 2) {
>  		if (INTEL_NUM_PIPES(dev_priv) == 1)
> -			dev_priv->display.update_wm = i845_update_wm;
> +			dev_priv->wm_disp.update_wm = i845_update_wm;
>  		else
> -			dev_priv->display.update_wm = i9xx_update_wm;
> +			dev_priv->wm_disp.update_wm = i9xx_update_wm;
>  	} else {
>  		drm_err(&dev_priv->drm,
>  			"unexpected fall-through in %s\n", __func__);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 06/21] drm/i915: split color functions from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> These are only used internally in the color module

I think this patch is a testament to my comment on wrappers for calling
vfuncs. It's all intel_color.c implementation details.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

I might nitpick on the choice of naming for the struct
drm_i915_display_color_funcs; generally display stuff (for whatever
historical reasons) uses intel_ prefix all over the place. And in this
case, I don't think there's any need to emphasize display, so I'd just
make it struct intel_color_funcs.

*shrug*


BR,
Jani.

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 64 +++++++++++-----------
>  drivers/gpu/drm/i915/i915_drv.h            | 39 +++++++------
>  2 files changed, 54 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index afcb4bf3826c..ed79075158dd 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	dev_priv->display.load_luts(crtc_state);
> +	dev_priv->color_funcs.load_luts(crtc_state);
>  }
>  
>  void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	dev_priv->display.color_commit(crtc_state);
> +	dev_priv->color_funcs.color_commit(crtc_state);
>  }
>  
>  static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
> @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	return dev_priv->display.color_check(crtc_state);
> +	return dev_priv->color_funcs.color_check(crtc_state);
>  }
>  
>  void intel_color_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	if (dev_priv->display.read_luts)
> -		dev_priv->display.read_luts(crtc_state);
> +	if (dev_priv->color_funcs.read_luts)
> +		dev_priv->color_funcs.read_luts(crtc_state);
>  }
>  
>  static bool need_plane_update(struct intel_plane *plane,
> @@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>  	if (HAS_GMCH(dev_priv)) {
>  		if (IS_CHERRYVIEW(dev_priv)) {
> -			dev_priv->display.color_check = chv_color_check;
> -			dev_priv->display.color_commit = i9xx_color_commit;
> -			dev_priv->display.load_luts = chv_load_luts;
> -			dev_priv->display.read_luts = chv_read_luts;
> +			dev_priv->color_funcs.color_check = chv_color_check;
> +			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> +			dev_priv->color_funcs.load_luts = chv_load_luts;
> +			dev_priv->color_funcs.read_luts = chv_read_luts;
>  		} else if (DISPLAY_VER(dev_priv) >= 4) {
> -			dev_priv->display.color_check = i9xx_color_check;
> -			dev_priv->display.color_commit = i9xx_color_commit;
> -			dev_priv->display.load_luts = i965_load_luts;
> -			dev_priv->display.read_luts = i965_read_luts;
> +			dev_priv->color_funcs.color_check = i9xx_color_check;
> +			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> +			dev_priv->color_funcs.load_luts = i965_load_luts;
> +			dev_priv->color_funcs.read_luts = i965_read_luts;
>  		} else {
> -			dev_priv->display.color_check = i9xx_color_check;
> -			dev_priv->display.color_commit = i9xx_color_commit;
> -			dev_priv->display.load_luts = i9xx_load_luts;
> -			dev_priv->display.read_luts = i9xx_read_luts;
> +			dev_priv->color_funcs.color_check = i9xx_color_check;
> +			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> +			dev_priv->color_funcs.load_luts = i9xx_load_luts;
> +			dev_priv->color_funcs.read_luts = i9xx_read_luts;
>  		}
>  	} else {
>  		if (DISPLAY_VER(dev_priv) >= 11)
> -			dev_priv->display.color_check = icl_color_check;
> +			dev_priv->color_funcs.color_check = icl_color_check;
>  		else if (DISPLAY_VER(dev_priv) >= 10)
> -			dev_priv->display.color_check = glk_color_check;
> +			dev_priv->color_funcs.color_check = glk_color_check;
>  		else if (DISPLAY_VER(dev_priv) >= 7)
> -			dev_priv->display.color_check = ivb_color_check;
> +			dev_priv->color_funcs.color_check = ivb_color_check;
>  		else
> -			dev_priv->display.color_check = ilk_color_check;
> +			dev_priv->color_funcs.color_check = ilk_color_check;
>  
>  		if (DISPLAY_VER(dev_priv) >= 9)
> -			dev_priv->display.color_commit = skl_color_commit;
> +			dev_priv->color_funcs.color_commit = skl_color_commit;
>  		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -			dev_priv->display.color_commit = hsw_color_commit;
> +			dev_priv->color_funcs.color_commit = hsw_color_commit;
>  		else
> -			dev_priv->display.color_commit = ilk_color_commit;
> +			dev_priv->color_funcs.color_commit = ilk_color_commit;
>  
>  		if (DISPLAY_VER(dev_priv) >= 11) {
> -			dev_priv->display.load_luts = icl_load_luts;
> -			dev_priv->display.read_luts = icl_read_luts;
> +			dev_priv->color_funcs.load_luts = icl_load_luts;
> +			dev_priv->color_funcs.read_luts = icl_read_luts;
>  		} else if (DISPLAY_VER(dev_priv) == 10) {
> -			dev_priv->display.load_luts = glk_load_luts;
> -			dev_priv->display.read_luts = glk_read_luts;
> +			dev_priv->color_funcs.load_luts = glk_load_luts;
> +			dev_priv->color_funcs.read_luts = glk_read_luts;
>  		} else if (DISPLAY_VER(dev_priv) >= 8) {
> -			dev_priv->display.load_luts = bdw_load_luts;
> +			dev_priv->color_funcs.load_luts = bdw_load_luts;
>  		} else if (DISPLAY_VER(dev_priv) >= 7) {
> -			dev_priv->display.load_luts = ivb_load_luts;
> +			dev_priv->color_funcs.load_luts = ivb_load_luts;
>  		} else {
> -			dev_priv->display.load_luts = ilk_load_luts;
> -			dev_priv->display.read_luts = ilk_read_luts;
> +			dev_priv->color_funcs.load_luts = ilk_load_luts;
> +			dev_priv->color_funcs.read_luts = ilk_read_luts;
>  		}
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2beee62bfb91..7e5a8b1bbdd8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -345,6 +345,25 @@ struct drm_i915_wm_disp_funcs {
>  	int (*compute_global_watermarks)(struct intel_atomic_state *state);
>  };
>  
> +struct drm_i915_display_color_funcs {
> +	int (*color_check)(struct intel_crtc_state *crtc_state);
> +	/*
> +	 * Program double buffered color management registers during
> +	 * vblank evasion. The registers should then latch during the
> +	 * next vblank start, alongside any other double buffered registers
> +	 * involved with the same commit.
> +	 */
> +	void (*color_commit)(const struct intel_crtc_state *crtc_state);
> +	/*
> +	 * Load LUTs (and other single buffered color management
> +	 * registers). Will (hopefully) be called during the vblank
> +	 * following the latching of any double buffered registers
> +	 * involved with the same commit.
> +	 */
> +	void (*load_luts)(const struct intel_crtc_state *crtc_state);
> +	void (*read_luts)(struct intel_crtc_state *crtc_state);
> +};
> +
>  struct drm_i915_display_funcs {
>  	void (*get_cdclk)(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config);
> @@ -381,23 +400,6 @@ struct drm_i915_display_funcs {
>  	/* render clock increase/decrease */
>  	/* display clock increase/decrease */
>  	/* pll clock increase/decrease */
> -
> -	int (*color_check)(struct intel_crtc_state *crtc_state);
> -	/*
> -	 * Program double buffered color management registers during
> -	 * vblank evasion. The registers should then latch during the
> -	 * next vblank start, alongside any other double buffered registers
> -	 * involved with the same commit.
> -	 */
> -	void (*color_commit)(const struct intel_crtc_state *crtc_state);
> -	/*
> -	 * Load LUTs (and other single buffered color management
> -	 * registers). Will (hopefully) be called during the vblank
> -	 * following the latching of any double buffered registers
> -	 * involved with the same commit.
> -	 */
> -	void (*load_luts)(const struct intel_crtc_state *crtc_state);
> -	void (*read_luts)(struct intel_crtc_state *crtc_state);
>  };
>  
>  
> @@ -987,6 +989,9 @@ struct drm_i915_private {
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;
>  
> +	/* Display internal color functions */
> +	struct drm_i915_display_color_funcs color_funcs;
> +
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;
>  	unsigned short pch_id;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 07/21] drm/i915: split audio functions from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> These are only used internally in the audio code
> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 24 +++++++++++-----------
>  drivers/gpu/drm/i915/i915_drv.h            | 19 +++++++++++------
>  2 files changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index 532237588511..f539826c0424 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>  
>  	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
>  
> -	if (dev_priv->display.audio_codec_enable)
> -		dev_priv->display.audio_codec_enable(encoder,
> +	if (dev_priv->audio_funcs.audio_codec_enable)
> +		dev_priv->audio_funcs.audio_codec_enable(encoder,
>  						     crtc_state,
>  						     conn_state);
>  
> @@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	enum pipe pipe = crtc->pipe;
>  
> -	if (dev_priv->display.audio_codec_disable)
> -		dev_priv->display.audio_codec_disable(encoder,
> +	if (dev_priv->audio_funcs.audio_codec_disable)
> +		dev_priv->audio_funcs.audio_codec_disable(encoder,
>  						      old_crtc_state,
>  						      old_conn_state);

Again, nice isolation here. :)

>  
> @@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_G4X(dev_priv)) {
> -		dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
> -		dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
> +		dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
> +		dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> -		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> +		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
> +		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
>  	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> -		dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
> -		dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
> +		dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
> +		dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> -		dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
> -		dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
> +		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
> +		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7e5a8b1bbdd8..3e60bf8182e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -364,6 +364,15 @@ struct drm_i915_display_color_funcs {
>  	void (*read_luts)(struct intel_crtc_state *crtc_state);
>  };
>  
> +struct drm_i915_display_audio_funcs {

Nitpick, I'd make it struct intel_audio_funcs.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> +	void (*audio_codec_enable)(struct intel_encoder *encoder,
> +				   const struct intel_crtc_state *crtc_state,
> +				   const struct drm_connector_state *conn_state);
> +	void (*audio_codec_disable)(struct intel_encoder *encoder,
> +				    const struct intel_crtc_state *old_crtc_state,
> +				    const struct drm_connector_state *old_conn_state);
> +};
> +
>  struct drm_i915_display_funcs {
>  	void (*get_cdclk)(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config);
> @@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
>  			     struct intel_crtc *crtc);
>  	void (*commit_modeset_enables)(struct intel_atomic_state *state);
>  	void (*commit_modeset_disables)(struct intel_atomic_state *state);
> -	void (*audio_codec_enable)(struct intel_encoder *encoder,
> -				   const struct intel_crtc_state *crtc_state,
> -				   const struct drm_connector_state *conn_state);
> -	void (*audio_codec_disable)(struct intel_encoder *encoder,
> -				    const struct intel_crtc_state *old_crtc_state,
> -				    const struct drm_connector_state *old_conn_state);
> +
>  	void (*fdi_link_train)(struct intel_crtc *crtc,
>  			       const struct intel_crtc_state *crtc_state);
>  	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> @@ -992,6 +996,9 @@ struct drm_i915_private {
>  	/* Display internal color functions */
>  	struct drm_i915_display_color_funcs color_funcs;
>  
> +	/* Display internal audio functions */
> +	struct drm_i915_display_audio_funcs audio_funcs;
> +
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;
>  	unsigned short pch_id;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 08/21] drm/i915: split cdclk functions from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>

Commit message.

>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 148 +++++++++---------
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_power.c    |   2 +-
>  drivers/gpu/drm/i915/i915_drv.h               |   8 +-
>  4 files changed, 83 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 34fa4130d5c4..c12b4e6bf5f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	 * at least what the CDCLK frequency requires.
>  	 */
>  	cdclk_config->voltage_level =
> -		dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
> +		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
>  }
>  
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
>  	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
>  	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
>  	cdclk_config.voltage_level =
> -		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> +		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  	cdclk_config.cdclk = cdclk_config.bypass;
>  	cdclk_config.vco = 0;
>  	cdclk_config.voltage_level =
> -		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
> +		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
>  		return;
>  
> -	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
> +	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
>  		return;
>  
>  	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> @@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  				     &dev_priv->gmbus_mutex);
>  	}
>  
> -	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
> +	dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
>  
>  	for_each_intel_dp(&dev_priv->drm, encoder) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
>  	cdclk_state->logical.cdclk = cdclk;
>  	cdclk_state->logical.voltage_level =
>  		max_t(int, min_voltage_level,
> -		      dev_priv->display.calc_voltage_level(cdclk));
> +		      dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
>  
>  	if (!cdclk_state->active_pipes) {
>  		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> @@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
>  		cdclk_state->actual.vco = vco;
>  		cdclk_state->actual.cdclk = cdclk;
>  		cdclk_state->actual.voltage_level =
> -			dev_priv->display.calc_voltage_level(cdclk);
> +			dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
>  	} else {
>  		cdclk_state->actual = cdclk_state->logical;
>  	}
> @@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	new_cdclk_state->active_pipes =
>  		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
>  
> -	ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
> +	ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
>  	if (ret)
>  		return ret;
>  
> @@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
> +	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>  
>  	/*
>  	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -2852,119 +2852,119 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_DG2(dev_priv)) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
>  		dev_priv->cdclk.table = dg2_cdclk_table;
>  	} else if (IS_ALDERLAKE_P(dev_priv)) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
>  		/* Wa_22011320316:adl-p[a0] */
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
>  		else
>  			dev_priv->cdclk.table = adlp_cdclk_table;
>  	} else if (IS_ROCKETLAKE(dev_priv)) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
>  		dev_priv->cdclk.table = rkl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_JSL_EHL(dev_priv)) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = bxt_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
>  		if (IS_GEMINILAKE(dev_priv))
>  			dev_priv->cdclk.table = glk_cdclk_table;
>  		else
>  			dev_priv->cdclk.table = bxt_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) == 9) {
> -		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = skl_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
>  	} else if (IS_BROADWELL(dev_priv)) {
> -		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = bdw_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = chv_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
> -		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->display.set_cdclk = vlv_set_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
>  	} else {
> -		dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> +		dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
>  	}
>  
>  	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
> -		dev_priv->display.get_cdclk = bxt_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
>  	else if (DISPLAY_VER(dev_priv) == 9)
> -		dev_priv->display.get_cdclk = skl_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
>  	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->display.get_cdclk = bdw_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
>  	else if (IS_HASWELL(dev_priv))
> -		dev_priv->display.get_cdclk = hsw_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
>  	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display.get_cdclk = vlv_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
>  	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
>  	else if (IS_IRONLAKE(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
>  	else if (IS_GM45(dev_priv))
> -		dev_priv->display.get_cdclk = gm45_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
>  	else if (IS_G45(dev_priv))
> -		dev_priv->display.get_cdclk = g33_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
>  	else if (IS_I965GM(dev_priv))
> -		dev_priv->display.get_cdclk = i965gm_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
>  	else if (IS_I965G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
>  	else if (IS_PINEVIEW(dev_priv))
> -		dev_priv->display.get_cdclk = pnv_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
>  	else if (IS_G33(dev_priv))
> -		dev_priv->display.get_cdclk = g33_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
>  	else if (IS_I945GM(dev_priv))
> -		dev_priv->display.get_cdclk = i945gm_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
>  	else if (IS_I945G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
>  	else if (IS_I915GM(dev_priv))
> -		dev_priv->display.get_cdclk = i915gm_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
>  	else if (IS_I915G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
>  	else if (IS_I865G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
>  	else if (IS_I85X(dev_priv))
> -		dev_priv->display.get_cdclk = i85x_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
>  	else if (IS_I845G(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
>  	else if (IS_I830(dev_priv))
> -		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
>  
> -	if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
> +	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
>  		     "Unknown platform. Assuming 133 MHz CDCLK\n"))
> -		dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
> +		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b1202ede3fb0..ccd0332e7945 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9120,7 +9120,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
>  	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
>  		*need_cdclk_calc = true;
>  
> -	ret = dev_priv->display.bw_calc_min_cdclk(state);
> +	ret = dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index cce1a926fcc1..2cf420c06ed6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	dev_priv->display.get_cdclk(dev_priv, &cdclk_config);
> +	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &cdclk_config);
>  	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
>  	drm_WARN_ON(&dev_priv->drm,
>  		    intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3e60bf8182e3..fbe92f248d05 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -373,7 +373,7 @@ struct drm_i915_display_audio_funcs {
>  				    const struct drm_connector_state *old_conn_state);
>  };
>  
> -struct drm_i915_display_funcs {
> +struct drm_i915_display_cdclk_funcs {

Nitpick, struct intel_cdclk_funcs.

intel_cdclk_*() wrappers for ->get_cdclk and ->bw_calc_min_cdclk would
be nice, as those are the ones that get called outside of intel_cdclk.c.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>  	void (*get_cdclk)(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config);
>  	void (*set_cdclk)(struct drm_i915_private *dev_priv,
> @@ -382,6 +382,9 @@ struct drm_i915_display_funcs {
>  	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
>  	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>  	u8 (*calc_voltage_level)(int cdclk);
> +};
> +
> +struct drm_i915_display_funcs {
>  	/* Returns the active state of the crtc, and if the crtc is active,
>  	 * fills out the pipe-config with the hw state. */
>  	bool (*get_pipe_config)(struct intel_crtc *,
> @@ -999,6 +1002,9 @@ struct drm_i915_private {
>  	/* Display internal audio functions */
>  	struct drm_i915_display_audio_funcs audio_funcs;
>  
> +	/* Display CDCLK functions */
> +	struct drm_i915_display_cdclk_funcs cdclk_funcs;
> +
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;
>  	unsigned short pch_id;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 09/21] drm/i915: split irq hotplug function from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> This provide a service from irq to display, so make it separate
> ---
>  drivers/gpu/drm/i915/display/intel_hotplug.c |  4 ++--
>  drivers/gpu/drm/i915/i915_drv.h              |  9 ++++++++-
>  drivers/gpu/drm/i915/i915_irq.c              | 14 +++++++-------
>  3 files changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index 47c85ac97c87..a06e1e1b33e1 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
>  
>  static void intel_hpd_irq_setup(struct drm_i915_private *i915)
>  {
> -	if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
> -		i915->display.hpd_irq_setup(i915);
> +	if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
> +		i915->irq_funcs.hpd_irq_setup(i915);
>  }
>  
>  static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fbe92f248d05..ece23401cb46 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -384,6 +384,10 @@ struct drm_i915_display_cdclk_funcs {
>  	u8 (*calc_voltage_level)(int cdclk);
>  };
>  
> +struct drm_i915_irq_funcs {

Here, I'm a bit divided with the naming, irqs being more of i915 core,
even if serving display. I could go with intel_hotplug_funcs. *shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> +};
> +
>  struct drm_i915_display_funcs {
>  	/* Returns the active state of the crtc, and if the crtc is active,
>  	 * fills out the pipe-config with the hw state. */
> @@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
>  
>  	void (*fdi_link_train)(struct intel_crtc *crtc,
>  			       const struct intel_crtc_state *crtc_state);
> -	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
> +
>  	/* clock updates for mode set */
>  	/* cursor updates */
>  	/* render clock increase/decrease */
> @@ -993,6 +997,9 @@ struct drm_i915_private {
>  	/* pm display functions */
>  	struct drm_i915_wm_disp_funcs wm_disp;
>  
> +	/* irq display functions */
> +	struct drm_i915_irq_funcs irq_funcs;
> +
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;
>  
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 0a1681384c84..f515a3a76a8e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  
>  	if (HAS_GMCH(dev_priv)) {
>  		if (I915_HAS_HOTPLUG(dev_priv))
> -			dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
>  	} else {
>  		if (HAS_PCH_DG1(dev_priv))
> -			dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
> -			dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
>  		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> -			dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
>  		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> -			dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
>  		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> -			dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
>  		else
> -			dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
> +			dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 10/21] drm/i915: split fdi link training from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> It may make sense to merge this with display again later,
> however the fdi use of the vtable is limited to only a
> few generations.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c     |  6 +++---
>  drivers/gpu/drm/i915/i915_drv.h              | 11 ++++++++---
>  3 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ccd0332e7945..b981a923cc2f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
>  	assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>  	/* For PCH output, training FDI link */
> -	dev_priv->display.fdi_link_train(crtc, crtc_state);
> +	dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);

Nitpick, I'd add a wrapper intel_fdi_link_train to call this.

>  
>  	/* We need to program the right clock selection before writing the pixel
>  	 * mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index fc09b781f15f..d9f952e0c67f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1009,11 +1009,11 @@ void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_IRONLAKE(dev_priv)) {
> -		dev_priv->display.fdi_link_train = ilk_fdi_link_train;
> +		dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
>  	} else if (IS_SANDYBRIDGE(dev_priv)) {
> -		dev_priv->display.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
>  	} else if (IS_IVYBRIDGE(dev_priv)) {
>  		/* FIXME: detect B0+ stepping and use auto training */
> -		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ece23401cb46..49b23ea46475 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -388,6 +388,11 @@ struct drm_i915_irq_funcs {
>  	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
>  };
>  
> +struct drm_i915_fdi_link_train_funcs {

Nitpick, intel_fdi_funcs.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> +	void (*fdi_link_train)(struct intel_crtc *crtc,
> +			       const struct intel_crtc_state *crtc_state);
> +};
> +
>  struct drm_i915_display_funcs {
>  	/* Returns the active state of the crtc, and if the crtc is active,
>  	 * fills out the pipe-config with the hw state. */
> @@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
>  	void (*commit_modeset_enables)(struct intel_atomic_state *state);
>  	void (*commit_modeset_disables)(struct intel_atomic_state *state);
>  
> -	void (*fdi_link_train)(struct intel_crtc *crtc,
> -			       const struct intel_crtc_state *crtc_state);
> -
>  	/* clock updates for mode set */
>  	/* cursor updates */
>  	/* render clock increase/decrease */
> @@ -1000,6 +1002,9 @@ struct drm_i915_private {
>  	/* irq display functions */
>  	struct drm_i915_irq_funcs irq_funcs;
>  
> +	/* fdi display functions */
> +	struct drm_i915_fdi_link_train_funcs fdi_funcs;
> +
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 11/21] drm/i915: split the dpll clock compute out from display vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> this could be merged later but for now it's simple to split it out.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dpll.c    | 16 ++++++++--------
>  drivers/gpu/drm/i915/i915_drv.h              |  8 +++++++-
>  3 files changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b981a923cc2f..87950202f4ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		crtc_state->update_wm_post = true;
>  
>  	if (mode_changed && crtc_state->hw.enable &&
> -	    dev_priv->display.crtc_compute_clock &&
> +	    dev_priv->dpll_funcs.crtc_compute_clock &&
>  	    !crtc_state->bigjoiner_slave &&
>  	    !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> -		ret = dev_priv->display.crtc_compute_clock(crtc_state);
> +		ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
>  		if (ret)
>  			return ret;

It was there before, but yuck. Conditions like this with checks on the
existence of a vfunc are really ugly. Could benefit from a wrapper - but
that requires figuring out what the condition actually is. *facepalm*.

>  	}
> @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	int i;
>  
> -	if (!dev_priv->display.crtc_compute_clock)
> +	if (!dev_priv->dpll_funcs.crtc_compute_clock)
>  		return;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 210f91f4a576..9326c7cbb05c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1367,21 +1367,21 @@ void
>  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> -		dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
>  	else if (IS_G4X(dev_priv))
> -		dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
>  	else if (IS_PINEVIEW(dev_priv))
> -		dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
>  	else if (DISPLAY_VER(dev_priv) != 2)
> -		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
>  	else
> -		dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
> +		dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
>  }
>  
>  static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 49b23ea46475..461ab0a0f088 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
>  			       const struct intel_crtc_state *crtc_state);
>  };
>  
> +struct drm_i915_dpll_funcs {

Nitpick, intel_dpll_funcs. Starting to spot the pattern? ;D

Part of the point is that I think these may eventually move to their own
headers, and I like to drive naming structs and functions after the file
name. So, you'd find intel_dpll_* stuff in intel_dpll.[ch]. Or if they
stay in i915_drv.h, at least that's the chrystal clear context.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
> +};
> +
>  struct drm_i915_display_funcs {
>  	/* Returns the active state of the crtc, and if the crtc is active,
>  	 * fills out the pipe-config with the hw state. */
> @@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
>  				struct intel_crtc_state *);
>  	void (*get_initial_plane_config)(struct intel_crtc *,
>  					 struct intel_initial_plane_config *);
> -	int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
>  	void (*crtc_enable)(struct intel_atomic_state *state,
>  			    struct intel_crtc *crtc);
>  	void (*crtc_disable)(struct intel_atomic_state *state,
> @@ -1005,6 +1008,9 @@ struct drm_i915_private {
>  	/* fdi display functions */
>  	struct drm_i915_fdi_link_train_funcs fdi_funcs;
>  
> +	/* display pll funcs */
> +	struct drm_i915_dpll_funcs dpll_funcs;
> +
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 12/21] drm/i915: constify fdi link training vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Avoid having writeable function pointers.

Would benefit from the call wrapper and naming.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c     | 18 +++++++++++++++---
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  3 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 87950202f4ce..0ad577aceb9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
>  	assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>  	/* For PCH output, training FDI link */
> -	dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
> +	dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
>  
>  	/* We need to program the right clock selection before writing the pixel
>  	 * mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index d9f952e0c67f..68aa9c7b18ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1005,15 +1005,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
>  	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
>  }
>  
> +static const struct drm_i915_fdi_link_train_funcs ilk_funcs = {
> +	.fdi_link_train = ilk_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs gen6_funcs = {
> +	.fdi_link_train = gen6_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs ivb_funcs = {
> +	.fdi_link_train = ivb_manual_fdi_link_train
> +};
> +
>  void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_IRONLAKE(dev_priv)) {
> -		dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
> +		dev_priv->fdi_funcs = &ilk_funcs;
>  	} else if (IS_SANDYBRIDGE(dev_priv)) {
> -		dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->fdi_funcs = &gen6_funcs;
>  	} else if (IS_IVYBRIDGE(dev_priv)) {
>  		/* FIXME: detect B0+ stepping and use auto training */
> -		dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->fdi_funcs = &ivb_funcs;
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 461ab0a0f088..b3765222e717 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1006,7 +1006,7 @@ struct drm_i915_private {
>  	struct drm_i915_irq_funcs irq_funcs;
>  
>  	/* fdi display functions */
> -	struct drm_i915_fdi_link_train_funcs fdi_funcs;
> +	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>  	/* display pll funcs */
>  	struct drm_i915_dpll_funcs dpll_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 13/21] drm/i915: constify irq function vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Use a macro to avoid mistakes, this type of macro is only used
> in a couple of places.
> ---
>  drivers/gpu/drm/i915/display/intel_hotplug.c |  4 +--
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  drivers/gpu/drm/i915/i915_irq.c              | 27 +++++++++++++++-----
>  3 files changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
> index a06e1e1b33e1..97df40107213 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
> @@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
>  
>  static void intel_hpd_irq_setup(struct drm_i915_private *i915)
>  {
> -	if (i915->display_irqs_enabled && i915->irq_funcs.hpd_irq_setup)
> -		i915->irq_funcs.hpd_irq_setup(i915);
> +	if (i915->display_irqs_enabled && i915->irq_funcs)
> +		i915->irq_funcs->hpd_irq_setup(i915);
>  }
>  
>  static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b3765222e717..6050bb519b18 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1003,7 +1003,7 @@ struct drm_i915_private {
>  	struct drm_i915_wm_disp_funcs wm_disp;
>  
>  	/* irq display functions */
> -	struct drm_i915_irq_funcs irq_funcs;
> +	const struct drm_i915_irq_funcs *irq_funcs;
>  
>  	/* fdi display functions */
>  	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f515a3a76a8e..29231daf6057 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4345,6 +4345,19 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
>  	return ret;
>  }
>  
> +#define HPD_FUNCS(platform)					\
> +static const struct drm_i915_irq_funcs platform##_hpd_funcs = { \
> +	.hpd_irq_setup = platform##_hpd_irq_setup		\
> +}
> +
> +HPD_FUNCS(i915);
> +HPD_FUNCS(dg1);
> +HPD_FUNCS(gen11);
> +HPD_FUNCS(bxt);
> +HPD_FUNCS(icp);
> +HPD_FUNCS(spt);
> +HPD_FUNCS(ilk);
> +

#undef HPD_FUNCS

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>  /**
>   * intel_irq_init - initializes irq support
>   * @dev_priv: i915 device instance
> @@ -4395,20 +4408,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  
>  	if (HAS_GMCH(dev_priv)) {
>  		if (I915_HAS_HOTPLUG(dev_priv))
> -			dev_priv->irq_funcs.hpd_irq_setup = i915_hpd_irq_setup;
> +			dev_priv->irq_funcs = &i915_hpd_funcs;
>  	} else {
>  		if (HAS_PCH_DG1(dev_priv))
> -			dev_priv->irq_funcs.hpd_irq_setup = dg1_hpd_irq_setup;
> +			dev_priv->irq_funcs = &dg1_hpd_funcs;
>  		else if (DISPLAY_VER(dev_priv) >= 11)
> -			dev_priv->irq_funcs.hpd_irq_setup = gen11_hpd_irq_setup;
> +			dev_priv->irq_funcs = &gen11_hpd_funcs;
>  		else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> -			dev_priv->irq_funcs.hpd_irq_setup = bxt_hpd_irq_setup;
> +			dev_priv->irq_funcs = &bxt_hpd_funcs;
>  		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> -			dev_priv->irq_funcs.hpd_irq_setup = icp_hpd_irq_setup;
> +			dev_priv->irq_funcs = &icp_hpd_funcs;
>  		else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> -			dev_priv->irq_funcs.hpd_irq_setup = spt_hpd_irq_setup;
> +			dev_priv->irq_funcs = &spt_hpd_funcs;
>  		else
> -			dev_priv->irq_funcs.hpd_irq_setup = ilk_hpd_irq_setup;
> +			dev_priv->irq_funcs = &ilk_hpd_funcs;
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 14/21] drm/i915: constify color function vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>

The commit message could contain some words about how ugly this used to
be and how beautiful it is now. Awesome.

One bug, comment inline.

>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 138 ++++++++++++++-------
>  drivers/gpu/drm/i915/i915_drv.h            |   2 +-
>  2 files changed, 93 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index ed79075158dd..b4e010c7e29d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	dev_priv->color_funcs.load_luts(crtc_state);
> +	dev_priv->color_funcs->load_luts(crtc_state);
>  }
>  
>  void intel_color_commit(const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	dev_priv->color_funcs.color_commit(crtc_state);
> +	dev_priv->color_funcs->color_commit(crtc_state);
>  }
>  
>  static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
> @@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	return dev_priv->color_funcs.color_check(crtc_state);
> +	return dev_priv->color_funcs->color_check(crtc_state);
>  }
>  
>  void intel_color_get_config(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  
> -	if (dev_priv->color_funcs.read_luts)
> -		dev_priv->color_funcs.read_luts(crtc_state);
> +	if (dev_priv->color_funcs->read_luts)
> +		dev_priv->color_funcs->read_luts(crtc_state);
>  }
>  
>  static bool need_plane_update(struct intel_plane *plane,
> @@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> +static const struct drm_i915_display_color_funcs chv_color_funcs = {
> +	.color_check = chv_color_check,
> +	.color_commit = i9xx_color_commit,
> +	.load_luts = chv_load_luts,
> +	.read_luts = chv_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs i965_color_funcs = {
> +	.color_check = i9xx_color_check,
> +	.color_commit = i9xx_color_commit,
> +	.load_luts = i965_load_luts,
> +	.read_luts = i965_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs i9xx_color_funcs = {
> +	.color_check = i9xx_color_check,
> +	.color_commit = i9xx_color_commit,
> +	.load_luts = i9xx_load_luts,
> +	.read_luts = i9xx_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs icl_color_funcs = {
> +	.color_check = icl_color_check,
> +	.color_commit = skl_color_commit,
> +	.load_luts = icl_load_luts,
> +	.read_luts = icl_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs glk_color_funcs = {
> +	.color_check = glk_color_check,
> +	.color_commit = skl_color_commit,
> +	.load_luts = glk_load_luts,
> +	.read_luts = glk_read_luts,
> +};
> +
> +static const struct drm_i915_display_color_funcs skl_color_funcs = {
> +	.color_check = ivb_color_check,
> +	.color_commit = skl_color_commit,
> +	.load_luts = bdw_load_luts,
> +	.read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs bdw_color_funcs = {
> +	.color_check = ivb_color_check,
> +	.color_commit = hsw_color_commit,
> +	.load_luts = bdw_load_luts,
> +	.read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs hsw_color_funcs = {
> +	.color_check = ivb_color_check,
> +	.color_commit = hsw_color_commit,
> +	.load_luts = ivb_load_luts,
> +	.read_luts = NULL,
> +};
> +
> +static const struct drm_i915_display_color_funcs ivb_color_funcs = {
> +	.color_check = ivb_color_check,
> +	.color_commit = ilk_color_commit,
> +	.load_luts = ilk_load_luts,

Should be ivb_load_luts.

> +	.read_luts = ilk_read_luts,

Should be NULL.

Old code for ivb i.e. non-hsw gen 7 was:

 -		} else if (DISPLAY_VER(dev_priv) >= 7) {
 -			dev_priv->color_funcs.load_luts = ivb_load_luts;
 -		} else {

Right? It's a nightmare to review this because the old code was a
nightmare to read.

I think with that fixed this is good, and,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +};
> +
> +static const struct drm_i915_display_color_funcs ilk_color_funcs = {
> +	.color_check = ilk_color_check,
> +	.color_commit = ilk_color_commit,
> +	.load_luts = ilk_load_luts,
> +	.read_luts = ilk_read_luts,
> +};
> +
>  void intel_color_init(struct intel_crtc *crtc)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
>  
>  	if (HAS_GMCH(dev_priv)) {
>  		if (IS_CHERRYVIEW(dev_priv)) {
> -			dev_priv->color_funcs.color_check = chv_color_check;
> -			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> -			dev_priv->color_funcs.load_luts = chv_load_luts;
> -			dev_priv->color_funcs.read_luts = chv_read_luts;
> +			dev_priv->color_funcs = &chv_color_funcs;
>  		} else if (DISPLAY_VER(dev_priv) >= 4) {
> -			dev_priv->color_funcs.color_check = i9xx_color_check;
> -			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> -			dev_priv->color_funcs.load_luts = i965_load_luts;
> -			dev_priv->color_funcs.read_luts = i965_read_luts;
> +			dev_priv->color_funcs = &i965_color_funcs;
>  		} else {
> -			dev_priv->color_funcs.color_check = i9xx_color_check;
> -			dev_priv->color_funcs.color_commit = i9xx_color_commit;
> -			dev_priv->color_funcs.load_luts = i9xx_load_luts;
> -			dev_priv->color_funcs.read_luts = i9xx_read_luts;
> +			dev_priv->color_funcs = &i9xx_color_funcs;
>  		}
>  	} else {
>  		if (DISPLAY_VER(dev_priv) >= 11)
> -			dev_priv->color_funcs.color_check = icl_color_check;
> -		else if (DISPLAY_VER(dev_priv) >= 10)
> -			dev_priv->color_funcs.color_check = glk_color_check;
> -		else if (DISPLAY_VER(dev_priv) >= 7)
> -			dev_priv->color_funcs.color_check = ivb_color_check;
> -		else
> -			dev_priv->color_funcs.color_check = ilk_color_check;
> -
> -		if (DISPLAY_VER(dev_priv) >= 9)
> -			dev_priv->color_funcs.color_commit = skl_color_commit;
> -		else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> -			dev_priv->color_funcs.color_commit = hsw_color_commit;
> -		else
> -			dev_priv->color_funcs.color_commit = ilk_color_commit;
> -
> -		if (DISPLAY_VER(dev_priv) >= 11) {
> -			dev_priv->color_funcs.load_luts = icl_load_luts;
> -			dev_priv->color_funcs.read_luts = icl_read_luts;
> -		} else if (DISPLAY_VER(dev_priv) == 10) {
> -			dev_priv->color_funcs.load_luts = glk_load_luts;
> -			dev_priv->color_funcs.read_luts = glk_read_luts;
> -		} else if (DISPLAY_VER(dev_priv) >= 8) {
> -			dev_priv->color_funcs.load_luts = bdw_load_luts;
> -		} else if (DISPLAY_VER(dev_priv) >= 7) {
> -			dev_priv->color_funcs.load_luts = ivb_load_luts;
> -		} else {
> -			dev_priv->color_funcs.load_luts = ilk_load_luts;
> -			dev_priv->color_funcs.read_luts = ilk_read_luts;
> -		}
> +			dev_priv->color_funcs = &icl_color_funcs;
> +		else if (DISPLAY_VER(dev_priv) == 10)
> +			dev_priv->color_funcs = &glk_color_funcs;
> +		else if (DISPLAY_VER(dev_priv) == 9)
> +			dev_priv->color_funcs = &skl_color_funcs;
> +		else if (DISPLAY_VER(dev_priv) == 8)
> +			dev_priv->color_funcs = &bdw_color_funcs;
> +		else if (DISPLAY_VER(dev_priv) == 7) {
> +			if (IS_HASWELL(dev_priv))
> +				dev_priv->color_funcs = &hsw_color_funcs;
> +			else
> +				dev_priv->color_funcs = &ivb_color_funcs;
> +		} else
> +			dev_priv->color_funcs = &ilk_color_funcs;
>  	}
>  
>  	drm_crtc_enable_color_mgmt(&crtc->base,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6050bb519b18..e82df3bf493b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1015,7 +1015,7 @@ struct drm_i915_private {
>  	struct drm_i915_display_funcs display;
>  
>  	/* Display internal color functions */
> -	struct drm_i915_display_color_funcs color_funcs;
> +	const struct drm_i915_display_color_funcs *color_funcs;
>  
>  	/* Display internal audio functions */
>  	struct drm_i915_display_audio_funcs audio_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 15/21] drm/i915: constify the audio function vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_audio.c | 43 ++++++++++++++--------
>  drivers/gpu/drm/i915/i915_drv.h            |  2 +-
>  2 files changed, 28 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
> index f539826c0424..4707e1beb763 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>  
>  	connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
>  
> -	if (dev_priv->audio_funcs.audio_codec_enable)
> -		dev_priv->audio_funcs.audio_codec_enable(encoder,
> -						     crtc_state,
> -						     conn_state);
> +	if (dev_priv->audio_funcs)
> +		dev_priv->audio_funcs->audio_codec_enable(encoder,
> +							  crtc_state,
> +							  conn_state);
>  
>  	mutex_lock(&dev_priv->av_mutex);
>  	encoder->audio_connector = connector;
> @@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  	enum port port = encoder->port;
>  	enum pipe pipe = crtc->pipe;
>  
> -	if (dev_priv->audio_funcs.audio_codec_disable)
> -		dev_priv->audio_funcs.audio_codec_disable(encoder,
> -						      old_crtc_state,
> -						      old_conn_state);
> +	if (dev_priv->audio_funcs)
> +		dev_priv->audio_funcs->audio_codec_disable(encoder,
> +							   old_crtc_state,
> +							   old_conn_state);
>  
>  	mutex_lock(&dev_priv->av_mutex);
>  	encoder->audio_connector = NULL;
> @@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  	intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
>  }
>  
> +static const struct drm_i915_display_audio_funcs g4x_audio_funcs = {
> +	.audio_codec_enable = g4x_audio_codec_enable,
> +	.audio_codec_disable = g4x_audio_codec_disable,
> +};
> +
> +static const struct drm_i915_display_audio_funcs ilk_audio_funcs = {
> +	.audio_codec_enable = ilk_audio_codec_enable,
> +	.audio_codec_disable = ilk_audio_codec_disable,
> +};
> +
> +static const struct drm_i915_display_audio_funcs hsw_audio_funcs = {
> +	.audio_codec_enable = hsw_audio_codec_enable,
> +	.audio_codec_disable = hsw_audio_codec_disable,
> +};
> +
>  /**
>   * intel_init_audio_hooks - Set up chip specific audio hooks
>   * @dev_priv: device private
> @@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
>  void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_G4X(dev_priv)) {
> -		dev_priv->audio_funcs.audio_codec_enable = g4x_audio_codec_enable;
> -		dev_priv->audio_funcs.audio_codec_disable = g4x_audio_codec_disable;
> +		dev_priv->audio_funcs = &g4x_audio_funcs;
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
> -		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
> +		dev_priv->audio_funcs = &ilk_audio_funcs;
>  	} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> -		dev_priv->audio_funcs.audio_codec_enable = hsw_audio_codec_enable;
> -		dev_priv->audio_funcs.audio_codec_disable = hsw_audio_codec_disable;
> +		dev_priv->audio_funcs = &hsw_audio_funcs;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> -		dev_priv->audio_funcs.audio_codec_enable = ilk_audio_codec_enable;
> -		dev_priv->audio_funcs.audio_codec_disable = ilk_audio_codec_disable;
> +		dev_priv->audio_funcs = &ilk_audio_funcs;
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e82df3bf493b..8d14318c5708 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1018,7 +1018,7 @@ struct drm_i915_private {
>  	const struct drm_i915_display_color_funcs *color_funcs;
>  
>  	/* Display internal audio functions */
> -	struct drm_i915_display_audio_funcs audio_funcs;
> +	const struct drm_i915_display_audio_funcs *audio_funcs;
>  
>  	/* Display CDCLK functions */
>  	struct drm_i915_display_cdclk_funcs cdclk_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 16/21] drm/i915: constify the dpll clock vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  6 +--
>  drivers/gpu/drm/i915/display/intel_dpll.c    | 49 ++++++++++++++++----
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  3 files changed, 45 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ad577aceb9d..d8a576d1435e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		crtc_state->update_wm_post = true;
>  
>  	if (mode_changed && crtc_state->hw.enable &&
> -	    dev_priv->dpll_funcs.crtc_compute_clock &&
> +	    dev_priv->dpll_funcs &&
>  	    !crtc_state->bigjoiner_slave &&
>  	    !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> -		ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
> +		ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
>  		if (ret)
>  			return ret;
>  	}
> @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	int i;
>  
> -	if (!dev_priv->dpll_funcs.crtc_compute_clock)
> +	if (!dev_priv->dpll_funcs)
>  		return;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 9326c7cbb05c..3df10b88e69f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1363,25 +1363,58 @@ static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state)
>  	return 0;
>  }
>  
> +static const struct drm_i915_dpll_funcs hsw_dpll_funcs = {
> +	.crtc_compute_clock = hsw_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs ilk_dpll_funcs = {
> +	.crtc_compute_clock = ilk_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs chv_dpll_funcs = {
> +	.crtc_compute_clock = chv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs vlv_dpll_funcs = {
> +	.crtc_compute_clock = vlv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs g4x_dpll_funcs = {
> +	.crtc_compute_clock = g4x_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs pnv_dpll_funcs = {
> +	.crtc_compute_clock = pnv_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs i9xx_dpll_funcs = {
> +	.crtc_compute_clock = i9xx_crtc_compute_clock
> +};
> +
> +static const struct drm_i915_dpll_funcs i8xx_dpll_funcs = {
> +	.crtc_compute_clock = i8xx_crtc_compute_clock
> +};
> +
> +
>  void
>  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
>  {
>  	if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &hsw_dpll_funcs;
>  	else if (HAS_PCH_SPLIT(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &ilk_dpll_funcs;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &chv_dpll_funcs;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &vlv_dpll_funcs;
>  	else if (IS_G4X(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &g4x_dpll_funcs;
>  	else if (IS_PINEVIEW(dev_priv))
> -		dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &pnv_dpll_funcs;
>  	else if (DISPLAY_VER(dev_priv) != 2)
> -		dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &i9xx_dpll_funcs;
>  	else
> -		dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
> +		dev_priv->dpll_funcs = &i8xx_dpll_funcs;
>  }
>  
>  static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8d14318c5708..a9563730aad5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1009,7 +1009,7 @@ struct drm_i915_private {
>  	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>  	/* display pll funcs */
> -	struct drm_i915_dpll_funcs dpll_funcs;
> +	const struct drm_i915_dpll_funcs *dpll_funcs;
>  
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 01/21] drm/i915/pm: drop get_fifo_size vfunc.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> The i845_update_wm code was always calling the i845 variant,
> and the i9xx_update_wm had only a choice between i830 and i9xx
> paths, hardly worth the vfunc overhead.
>
> Signed-off-by: Dave Airlie <airlied@redhat.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 --
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++---------
>  2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index be2392bbcecc..6511ec674c23 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
>  			  const struct intel_cdclk_config *cdclk_config,
>  			  enum pipe pipe);
>  	int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
> -	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
> -			     enum i9xx_plane_id i9xx_plane);
>  	int (*compute_pipe_wm)(struct intel_atomic_state *state,
>  			       struct intel_crtc *crtc);
>  	int (*compute_intermediate_wm)(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index cfc41f8fa74a..d9993eb3730d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	else
>  		wm_info = &i830_a_wm_info;
>  
> -	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
> +	if (DISPLAY_VER(dev_priv) == 2)
> +		fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
> +	else
> +		fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *pipe_mode =
> @@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  	if (DISPLAY_VER(dev_priv) == 2)
>  		wm_info = &i830_bc_wm_info;
>  
> -	fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
> +	if (DISPLAY_VER(dev_priv) == 2)
> +		fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
> +	else
> +		fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
>  	crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
>  	if (intel_crtc_active(crtc)) {
>  		const struct drm_display_mode *pipe_mode =
> @@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
>  	pipe_mode = &crtc->config->hw.pipe_mode;
>  	planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
>  				       &i845_wm_info,
> -				       dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
> +				       i845_get_fifo_size(dev_priv, PLANE_A),
>  				       4, pessimal_latency_ns);
>  	fwater_lo = intel_uncore_read(&dev_priv->uncore, FW_BLC) & ~0xfff;
>  	fwater_lo |= (3<<8) | planea_wm;
> @@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		dev_priv->display.update_wm = i965_update_wm;
>  	} else if (DISPLAY_VER(dev_priv) == 3) {
>  		dev_priv->display.update_wm = i9xx_update_wm;
> -		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
>  	} else if (DISPLAY_VER(dev_priv) == 2) {
> -		if (INTEL_NUM_PIPES(dev_priv) == 1) {
> +		if (INTEL_NUM_PIPES(dev_priv) == 1)
>  			dev_priv->display.update_wm = i845_update_wm;
> -			dev_priv->display.get_fifo_size = i845_get_fifo_size;
> -		} else {
> +		else
>  			dev_priv->display.update_wm = i9xx_update_wm;
> -			dev_priv->display.get_fifo_size = i830_get_fifo_size;
> -		}
>  	} else {
>  		drm_err(&dev_priv->drm,
>  			"unexpected fall-through in %s\n", __func__);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[Jani Nikula]

On Wed, 08 Sep 2021, David Airlie <airlied@redhat.com> wrote:
> On Wed, Sep 8, 2021 at 10:39 AM Dave Airlie <airlied@gmail.com> wrote:
>>
>> From: Dave Airlie <airlied@redhat.com>
>>
>> The crtc was never being used here.
>
> /me realises I've noobed up the Sob on these,
>
> I've added them to my tree locally and in the branch I posted to the
> other thread., if there are comments/no comments I'll add them in a
> respin tomorrow.

Please also add commit messages to the ones that lack one.

Thanks,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 02/21] drm/i915: make update_wm take a dev_priv.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> The crtc was never being used here.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c              | 18 ++++++------------
>  drivers/gpu/drm/i915/intel_pm.h              |  2 +-
>  4 files changed, 13 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1f447ba776c7..d95283bf2631 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2373,7 +2373,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state,
>  	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
>  
>  	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
> -		intel_update_watermarks(crtc);
> +		intel_update_watermarks(dev_priv);
>  
>  	if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
>  		hsw_enable_ips(new_crtc_state);
> @@ -2529,7 +2529,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  		if (dev_priv->display.initial_watermarks)
>  			dev_priv->display.initial_watermarks(state, crtc);
>  		else if (new_crtc_state->update_wm_pre)
> -			intel_update_watermarks(crtc);
> +			intel_update_watermarks(dev_priv);
>  	}
>  
>  	/*
> @@ -3576,7 +3576,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
>  	if (dev_priv->display.initial_watermarks)
>  		dev_priv->display.initial_watermarks(state, crtc);
>  	else
> -		intel_update_watermarks(crtc);
> +		intel_update_watermarks(dev_priv);
>  	intel_enable_pipe(new_crtc_state);
>  
>  	intel_crtc_vblank_on(new_crtc_state);
> @@ -3643,7 +3643,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
>  	if (!dev_priv->display.initial_watermarks)
> -		intel_update_watermarks(crtc);
> +		intel_update_watermarks(dev_priv);
>  
>  	/* clock the pipe down to 640x480@60 to potentially save power */
>  	if (IS_I830(dev_priv))
> @@ -3719,7 +3719,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
>  		encoder->base.crtc = NULL;
>  
>  	intel_fbc_disable(crtc);
> -	intel_update_watermarks(crtc);
> +	intel_update_watermarks(dev_priv);
>  	intel_disable_shared_dpll(crtc_state);
>  
>  	intel_display_power_put_all_in_set(dev_priv, &crtc->enabled_power_domains);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6511ec674c23..ef903d70ab0b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
>  	void (*optimize_watermarks)(struct intel_atomic_state *state,
>  				    struct intel_crtc *crtc);
>  	int (*compute_global_watermarks)(struct intel_atomic_state *state);
> -	void (*update_wm)(struct intel_crtc *crtc);
> +	void (*update_wm)(struct drm_i915_private *dev_priv);
>  	int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
>  	u8 (*calc_voltage_level)(int cdclk);
>  	/* Returns the active state of the crtc, and if the crtc is active,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d9993eb3730d..406baa49e6ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
>  	return enabled;
>  }
>  
> -static void pnv_update_wm(struct intel_crtc *unused_crtc)
> +static void pnv_update_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>  	struct intel_crtc *crtc;
>  	const struct cxsr_latency *latency;
>  	u32 reg;
> @@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
>  	mutex_unlock(&dev_priv->wm.wm_mutex);
>  }
>  
> -static void i965_update_wm(struct intel_crtc *unused_crtc)
> +static void i965_update_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>  	struct intel_crtc *crtc;
>  	int srwm = 1;
>  	int cursor_sr = 16;
> @@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
>  
>  #undef FW_WM
>  
> -static void i9xx_update_wm(struct intel_crtc *unused_crtc)
> +static void i9xx_update_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>  	const struct intel_watermark_params *wm_info;
>  	u32 fwater_lo;
>  	u32 fwater_hi;
> @@ -2481,9 +2478,8 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc)
>  		intel_set_memory_cxsr(dev_priv, true);
>  }
>  
> -static void i845_update_wm(struct intel_crtc *unused_crtc)
> +static void i845_update_wm(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
>  	struct intel_crtc *crtc;
>  	const struct drm_display_mode *pipe_mode;
>  	u32 fwater_lo;
> @@ -7169,12 +7165,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
>   * We don't use the sprite, so we can ignore that.  And on Crestline we have
>   * to set the non-SR watermarks to 8.
>   */
> -void intel_update_watermarks(struct intel_crtc *crtc)
> +void intel_update_watermarks(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -
>  	if (dev_priv->display.update_wm)
> -		dev_priv->display.update_wm(crtc);
> +		dev_priv->display.update_wm(dev_priv);
>  }
>  
>  void intel_enable_ipc(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 941b3ae555c8..99bce0b4f5fb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -29,7 +29,7 @@ struct skl_wm_level;
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv);
>  void intel_suspend_hw(struct drm_i915_private *dev_priv);
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
> -void intel_update_watermarks(struct intel_crtc *crtc);
> +void intel_update_watermarks(struct drm_i915_private *dev_priv);
>  void intel_init_pm(struct drm_i915_private *dev_priv);
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>  void intel_pm_setup(struct drm_i915_private *dev_priv);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 04/21] drm/i915: split clock gating init from display vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> This function is only used inside intel_pm.c
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  9 ++++++-
>  drivers/gpu/drm/i915/intel_pm.c | 48 ++++++++++++++++-----------------
>  2 files changed, 32 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index ef903d70ab0b..b93fa19892b5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -323,6 +323,11 @@ struct intel_crtc;
>  struct intel_limit;
>  struct dpll;
>  
> +/* functions used internal in intel_pm.c */
> +struct drm_i915_cg_funcs {

Nitpick, cg here is a bit terse.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
> +};
> +
>  struct drm_i915_display_funcs {
>  	void (*get_cdclk)(struct drm_i915_private *dev_priv,
>  			  struct intel_cdclk_config *cdclk_config);
> @@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
>  				    const struct drm_connector_state *old_conn_state);
>  	void (*fdi_link_train)(struct intel_crtc *crtc,
>  			       const struct intel_crtc_state *crtc_state);
> -	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
>  	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
>  	/* clock updates for mode set */
>  	/* cursor updates */
> @@ -969,6 +973,9 @@ struct drm_i915_private {
>  	/* unbound hipri wq for page flips/plane updates */
>  	struct workqueue_struct *flip_wq;
>  
> +	/* pm private clock gating functions */
> +	struct drm_i915_cg_funcs cg_funcs;
> +
>  	/* Display functions */
>  	struct drm_i915_display_funcs display;
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 4054c6f7a2f9..73549e774881 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->display.init_clock_gating(dev_priv);
> +	dev_priv->cg_funcs.init_clock_gating(dev_priv);
>  }
>  
>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ALDERLAKE_P(dev_priv))
> -		dev_priv->display.init_clock_gating = adlp_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
>  	else if (IS_DG1(dev_priv))
> -		dev_priv->display.init_clock_gating = dg1_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 12)
> -		dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 11)
> -		dev_priv->display.init_clock_gating = icl_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
>  	else if (IS_SKYLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = skl_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
>  	else if (IS_KABYLAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = kbl_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
>  	else if (IS_BROXTON(dev_priv))
> -		dev_priv->display.init_clock_gating = bxt_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
>  	else if (IS_GEMINILAKE(dev_priv))
> -		dev_priv->display.init_clock_gating = glk_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
>  	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->display.init_clock_gating = bdw_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->display.init_clock_gating = chv_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
>  	else if (IS_HASWELL(dev_priv))
> -		dev_priv->display.init_clock_gating = hsw_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
>  	else if (IS_IVYBRIDGE(dev_priv))
> -		dev_priv->display.init_clock_gating = ivb_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->display.init_clock_gating = vlv_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 6)
> -		dev_priv->display.init_clock_gating = gen6_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 5)
> -		dev_priv->display.init_clock_gating = ilk_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
>  	else if (IS_G4X(dev_priv))
> -		dev_priv->display.init_clock_gating = g4x_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
>  	else if (IS_I965GM(dev_priv))
> -		dev_priv->display.init_clock_gating = i965gm_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
>  	else if (IS_I965G(dev_priv))
> -		dev_priv->display.init_clock_gating = i965g_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 3)
> -		dev_priv->display.init_clock_gating = gen3_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> -		dev_priv->display.init_clock_gating = i85x_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
>  	else if (GRAPHICS_VER(dev_priv) == 2)
> -		dev_priv->display.init_clock_gating = i830_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
>  	else {
>  		MISSING_CASE(INTEL_DEVID(dev_priv));
> -		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 18/21] drm/i915: drop unused function ptr and comments.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> There was some excess comments and an unused vtbl ptr.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_drv.h | 7 -------
>  1 file changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 085012727549..2231b93c2111 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
>  	void (*crtc_disable)(struct intel_atomic_state *state,
>  			     struct intel_crtc *crtc);
>  	void (*commit_modeset_enables)(struct intel_atomic_state *state);
> -	void (*commit_modeset_disables)(struct intel_atomic_state *state);
> -
> -	/* clock updates for mode set */
> -	/* cursor updates */
> -	/* render clock increase/decrease */
> -	/* display clock increase/decrease */
> -	/* pll clock increase/decrease */
>  };

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 17/21] drm/i915: constify the cdclk vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> This is a bit of a twisty one since each platform is slightly
> different, so might take some more review care.

Yes, it was a PITA to review. But the end result is good.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 306 ++++++++++++------
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_power.c    |   2 +-
>  drivers/gpu/drm/i915/i915_drv.h               |   2 +-
>  4 files changed, 211 insertions(+), 101 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c12b4e6bf5f5..9ce053bea022 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1466,7 +1466,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
>  	 * at least what the CDCLK frequency requires.
>  	 */
>  	cdclk_config->voltage_level =
> -		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config->cdclk);
> +		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config->cdclk);
>  }
>  
>  static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1777,7 +1777,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
>  	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
>  	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
>  	cdclk_config.voltage_level =
> -		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
> +		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1789,7 +1789,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
>  	cdclk_config.cdclk = cdclk_config.bypass;
>  	cdclk_config.vco = 0;
>  	cdclk_config.voltage_level =
> -		dev_priv->cdclk_funcs.calc_voltage_level(cdclk_config.cdclk);
> +		dev_priv->cdclk_funcs->calc_voltage_level(cdclk_config.cdclk);
>  
>  	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>  }
> @@ -1932,7 +1932,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  	if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
>  		return;
>  
> -	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
> +	if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
>  		return;
>  
>  	intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
> @@ -1956,7 +1956,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>  				     &dev_priv->gmbus_mutex);
>  	}
>  
> -	dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
> +	dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
>  
>  	for_each_intel_dp(&dev_priv->drm, encoder) {
>  		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> @@ -2414,7 +2414,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
>  	cdclk_state->logical.cdclk = cdclk;
>  	cdclk_state->logical.voltage_level =
>  		max_t(int, min_voltage_level,
> -		      dev_priv->cdclk_funcs.calc_voltage_level(cdclk));
> +		      dev_priv->cdclk_funcs->calc_voltage_level(cdclk));
>  
>  	if (!cdclk_state->active_pipes) {
>  		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
> @@ -2423,7 +2423,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
>  		cdclk_state->actual.vco = vco;
>  		cdclk_state->actual.cdclk = cdclk;
>  		cdclk_state->actual.voltage_level =
> -			dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
> +			dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
>  	} else {
>  		cdclk_state->actual = cdclk_state->logical;
>  	}
> @@ -2515,7 +2515,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
>  	new_cdclk_state->active_pipes =
>  		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
>  
> -	ret = dev_priv->cdclk_funcs.modeset_calc_cdclk(new_cdclk_state);
> +	ret = dev_priv->cdclk_funcs->modeset_calc_cdclk(new_cdclk_state);
>  	if (ret)
>  		return ret;
>  
> @@ -2695,7 +2695,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
>   */
>  void intel_update_cdclk(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
> +	dev_priv->cdclk_funcs->get_cdclk(dev_priv, &dev_priv->cdclk.hw);
>  
>  	/*
>  	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
> @@ -2845,6 +2845,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  	return freq;
>  }
>  
> +static struct drm_i915_display_cdclk_funcs tgl_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = tgl_calc_voltage_level,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs ehl_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = ehl_calc_voltage_level,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs icl_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = icl_calc_voltage_level,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs bxt_cdclk_funcs = {
> +	.get_cdclk = bxt_get_cdclk,
> +	.set_cdclk = bxt_set_cdclk,
> +	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
> +	.calc_voltage_level = bxt_calc_voltage_level,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs skl_cdclk_funcs = {
> +	.get_cdclk = skl_get_cdclk,
> +	.set_cdclk = skl_set_cdclk,
> +	.bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs bdw_cdclk_funcs = {
> +	.get_cdclk = bdw_get_cdclk,
> +	.set_cdclk = bdw_set_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs chv_cdclk_funcs = {
> +	.get_cdclk = vlv_get_cdclk,
> +	.set_cdclk = chv_set_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs vlv_cdclk_funcs = {
> +	.get_cdclk = vlv_get_cdclk,
> +	.set_cdclk = vlv_set_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs hsw_cdclk_funcs = {
> +	.get_cdclk = hsw_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +/* SNB, IVB, 965G, 945G */
> +static struct drm_i915_display_cdclk_funcs fixed_400mhz_cdclk_funcs = {
> +	.get_cdclk = fixed_400mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs ilk_cdclk_funcs = {
> +	.get_cdclk = fixed_450mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs gm45_cdclk_funcs = {
> +	.get_cdclk = gm45_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +/* G45 uses G33 */
> +
> +static struct drm_i915_display_cdclk_funcs i965gm_cdclk_funcs = {
> +	.get_cdclk = i965gm_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +/* i965G uses fixed 400 */
> +
> +static struct drm_i915_display_cdclk_funcs pnv_cdclk_funcs = {
> +	.get_cdclk = pnv_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs g33_cdclk_funcs = {
> +	.get_cdclk = g33_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i945gm_cdclk_funcs = {
> +	.get_cdclk = i945gm_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +/* i945G uses fixed 400 */
> +
> +static struct drm_i915_display_cdclk_funcs i915gm_cdclk_funcs = {
> +	.get_cdclk = i915gm_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i915g_cdclk_funcs = {
> +	.get_cdclk = fixed_333mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i865g_cdclk_funcs = {
> +	.get_cdclk = fixed_266mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i85x_cdclk_funcs = {
> +	.get_cdclk = i85x_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i845g_cdclk_funcs = {
> +	.get_cdclk = fixed_200mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
> +static struct drm_i915_display_cdclk_funcs i830_cdclk_funcs = {
> +	.get_cdclk = fixed_133mhz_get_cdclk,
> +	.bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
> +	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
> +};
> +
>  /**
>   * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
>   * @dev_priv: i915 device
> @@ -2852,119 +3003,78 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
>  void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_DG2(dev_priv)) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
>  		dev_priv->cdclk.table = dg2_cdclk_table;
>  	} else if (IS_ALDERLAKE_P(dev_priv)) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
>  		/* Wa_22011320316:adl-p[a0] */
>  		if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>  			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
>  		else
>  			dev_priv->cdclk.table = adlp_cdclk_table;
>  	} else if (IS_ROCKETLAKE(dev_priv)) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
>  		dev_priv->cdclk.table = rkl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 12) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = tgl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_JSL_EHL(dev_priv)) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = ehl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) >= 11) {
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = icl_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &icl_cdclk_funcs;
>  		dev_priv->cdclk.table = icl_cdclk_table;
>  	} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
> -		dev_priv->cdclk_funcs.calc_voltage_level = bxt_calc_voltage_level;
> +		dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
>  		if (IS_GEMINILAKE(dev_priv))
>  			dev_priv->cdclk.table = glk_cdclk_table;
>  		else
>  			dev_priv->cdclk.table = bxt_cdclk_table;
>  	} else if (DISPLAY_VER(dev_priv) == 9) {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.set_cdclk = skl_set_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = skl_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs = &skl_cdclk_funcs;
>  	} else if (IS_BROADWELL(dev_priv)) {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.set_cdclk = bdw_set_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
> +	} else if (IS_HASWELL(dev_priv)) {
> +		dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.set_cdclk = chv_set_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs = &chv_cdclk_funcs;
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.set_cdclk = vlv_set_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
> -	} else {
> -		dev_priv->cdclk_funcs.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
> -		dev_priv->cdclk_funcs.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
> +		dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
> +	} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> +		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> +	} else if (IS_IRONLAKE(dev_priv)) {
> +		dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
> +	} else if (IS_GM45(dev_priv)) {
> +		dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
> +	} else if (IS_G45(dev_priv)) {
> +		dev_priv->cdclk_funcs = &g33_cdclk_funcs;
> +	} else if (IS_I965GM(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
> +	} else if (IS_I965G(dev_priv)) {
> +		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> +	} else if (IS_PINEVIEW(dev_priv)) {
> +		dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
> +	} else if (IS_G33(dev_priv)) {
> +		dev_priv->cdclk_funcs = &g33_cdclk_funcs;
> +	} else if (IS_I945GM(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
> +	} else if (IS_I945G(dev_priv)) {
> +		dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> +	} else if (IS_I915GM(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
> +	} else if (IS_I915G(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
> +	} else if (IS_I865G(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
> +	} else if (IS_I85X(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
> +	} else if (IS_I845G(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
> +	} else if (IS_I830(dev_priv)) {
> +		dev_priv->cdclk_funcs = &i830_cdclk_funcs;
>  	}
>  
> -	if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = bxt_get_cdclk;
> -	else if (DISPLAY_VER(dev_priv) == 9)
> -		dev_priv->cdclk_funcs.get_cdclk = skl_get_cdclk;
> -	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = bdw_get_cdclk;
> -	else if (IS_HASWELL(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = hsw_get_cdclk;
> -	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = vlv_get_cdclk;
> -	else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_IRONLAKE(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_450mhz_get_cdclk;
> -	else if (IS_GM45(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = gm45_get_cdclk;
> -	else if (IS_G45(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
> -	else if (IS_I965GM(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = i965gm_get_cdclk;
> -	else if (IS_I965G(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_PINEVIEW(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = pnv_get_cdclk;
> -	else if (IS_G33(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = g33_get_cdclk;
> -	else if (IS_I945GM(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = i945gm_get_cdclk;
> -	else if (IS_I945G(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_400mhz_get_cdclk;
> -	else if (IS_I915GM(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = i915gm_get_cdclk;
> -	else if (IS_I915G(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_333mhz_get_cdclk;
> -	else if (IS_I865G(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_266mhz_get_cdclk;
> -	else if (IS_I85X(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = i85x_get_cdclk;
> -	else if (IS_I845G(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_200mhz_get_cdclk;
> -	else if (IS_I830(dev_priv))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
> -
> -	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs.get_cdclk,
> -		     "Unknown platform. Assuming 133 MHz CDCLK\n"))
> -		dev_priv->cdclk_funcs.get_cdclk = fixed_133mhz_get_cdclk;
> +	if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
> +		     "Unknown platform. Assuming i830\n"))
> +		dev_priv->cdclk_funcs = &i830_cdclk_funcs;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d8a576d1435e..09c9dc741026 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9120,7 +9120,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state,
>  	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
>  		*need_cdclk_calc = true;
>  
> -	ret = dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
> +	ret = dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 2cf420c06ed6..b6c233039a54 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	dev_priv->cdclk_funcs.get_cdclk(dev_priv, &cdclk_config);
> +	dev_priv->cdclk_funcs->get_cdclk(dev_priv, &cdclk_config);
>  	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
>  	drm_WARN_ON(&dev_priv->drm,
>  		    intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a9563730aad5..085012727549 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1021,7 +1021,7 @@ struct drm_i915_private {
>  	const struct drm_i915_display_audio_funcs *audio_funcs;
>  
>  	/* Display CDCLK functions */
> -	struct drm_i915_display_cdclk_funcs cdclk_funcs;
> +	const struct drm_i915_display_cdclk_funcs *cdclk_funcs;
>  
>  	/* PCH chipset type */
>  	enum intel_pch pch_type;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 19/21] drm/i915: constify display function vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 81 ++++++++++++--------
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  2 files changed, 52 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 09c9dc741026..20fd35c6858c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3736,7 +3736,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
>  
>  	drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret);
>  
> -	dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
> +	dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
>  
>  	drm_atomic_state_put(state);
>  
> @@ -5941,7 +5941,7 @@ static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  
> -	if (!i915->display.get_pipe_config(crtc, crtc_state))
> +	if (!i915->display->get_pipe_config(crtc, crtc_state))
>  		return false;
>  
>  	crtc_state->hw.active = true;
> @@ -9778,7 +9778,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>  
>  	intel_crtc_update_active_timings(new_crtc_state);
>  
> -	dev_priv->display.crtc_enable(state, crtc);
> +	dev_priv->display->crtc_enable(state, crtc);
>  
>  	if (new_crtc_state->bigjoiner_slave)
>  		return;
> @@ -9866,7 +9866,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	 */
>  	intel_crtc_disable_pipe_crc(crtc);
>  
> -	dev_priv->display.crtc_disable(state, crtc);
> +	dev_priv->display->crtc_disable(state, crtc);
>  	crtc->active = false;
>  	intel_fbc_disable(crtc);
>  	intel_disable_shared_dpll(old_crtc_state);
> @@ -10246,7 +10246,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	}
>  
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
> -	dev_priv->display.commit_modeset_enables(state);
> +	dev_priv->display->commit_modeset_enables(state);
>  
>  	if (state->modeset) {
>  		intel_encoders_update_complete(state);
> @@ -11250,6 +11250,46 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
>  	.atomic_state_free = intel_atomic_state_free,
>  };
>  
> +static const struct drm_i915_display_funcs skl_display_funcs = {
> +	.get_pipe_config = hsw_get_pipe_config,
> +	.crtc_enable = hsw_crtc_enable,
> +	.crtc_disable = hsw_crtc_disable,
> +	.commit_modeset_enables = skl_commit_modeset_enables,
> +	.get_initial_plane_config = skl_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs ddi_display_funcs = {
> +	.get_pipe_config = hsw_get_pipe_config,
> +	.crtc_enable = hsw_crtc_enable,
> +	.crtc_disable = hsw_crtc_disable,
> +	.commit_modeset_enables = intel_commit_modeset_enables,
> +	.get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs pch_split_display_funcs = {
> +	.get_pipe_config = ilk_get_pipe_config,
> +	.crtc_enable = ilk_crtc_enable,
> +	.crtc_disable = ilk_crtc_disable,
> +	.commit_modeset_enables = intel_commit_modeset_enables,
> +	.get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs vlv_display_funcs = {
> +	.get_pipe_config = i9xx_get_pipe_config,
> +	.crtc_enable = valleyview_crtc_enable,
> +	.crtc_disable = i9xx_crtc_disable,
> +	.commit_modeset_enables = intel_commit_modeset_enables,
> +	.get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
> +static const struct drm_i915_display_funcs i9xx_display_funcs = {
> +	.get_pipe_config = i9xx_get_pipe_config,
> +	.crtc_enable = i9xx_crtc_enable,
> +	.crtc_disable = i9xx_crtc_disable,
> +	.commit_modeset_enables = intel_commit_modeset_enables,
> +	.get_initial_plane_config = i9xx_get_initial_plane_config,
> +};
> +
>  /**
>   * intel_init_display_hooks - initialize the display modesetting hooks
>   * @dev_priv: device private
> @@ -11265,38 +11305,19 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>  	intel_dpll_init_clock_hook(dev_priv);
>  
>  	if (DISPLAY_VER(dev_priv) >= 9) {
> -		dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> -		dev_priv->display.crtc_enable = hsw_crtc_enable;
> -		dev_priv->display.crtc_disable = hsw_crtc_disable;
> +		dev_priv->display = &skl_display_funcs;
>  	} else if (HAS_DDI(dev_priv)) {
> -		dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> -		dev_priv->display.crtc_enable = hsw_crtc_enable;
> -		dev_priv->display.crtc_disable = hsw_crtc_disable;
> +		dev_priv->display = &ddi_display_funcs;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
> -		dev_priv->display.get_pipe_config = ilk_get_pipe_config;
> -		dev_priv->display.crtc_enable = ilk_crtc_enable;
> -		dev_priv->display.crtc_disable = ilk_crtc_disable;
> +		dev_priv->display = &pch_split_display_funcs;
>  	} else if (IS_CHERRYVIEW(dev_priv) ||
>  		   IS_VALLEYVIEW(dev_priv)) {
> -		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> -		dev_priv->display.crtc_enable = valleyview_crtc_enable;
> -		dev_priv->display.crtc_disable = i9xx_crtc_disable;
> +		dev_priv->display = &vlv_display_funcs;
>  	} else {
> -		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
> -		dev_priv->display.crtc_enable = i9xx_crtc_enable;
> -		dev_priv->display.crtc_disable = i9xx_crtc_disable;
> +		dev_priv->display = &i9xx_display_funcs;
>  	}
>  
>  	intel_fdi_init_hook(dev_priv);
> -
> -	if (DISPLAY_VER(dev_priv) >= 9) {
> -		dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables;
> -		dev_priv->display.get_initial_plane_config = skl_get_initial_plane_config;
> -	} else {
> -		dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables;
> -		dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config;
> -	}
> -
>  }
>  
>  void intel_modeset_init_hw(struct drm_i915_private *i915)
> @@ -11723,7 +11744,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
>  		 * can even allow for smooth boot transitions if the BIOS
>  		 * fb is large enough for the active pipe configuration.
>  		 */
> -		i915->display.get_initial_plane_config(crtc, &plane_config);
> +		i915->display->get_initial_plane_config(crtc, &plane_config);
>  
>  		/*
>  		 * If the fb is shared between multiple heads, we'll
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 2231b93c2111..fbcafc7cc075 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1005,7 +1005,7 @@ struct drm_i915_private {
>  	const struct drm_i915_dpll_funcs *dpll_funcs;
>  
>  	/* Display functions */
> -	struct drm_i915_display_funcs display;
> +	const struct drm_i915_display_funcs *display;
>  
>  	/* Display internal color functions */
>  	const struct drm_i915_display_color_funcs *color_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> I used a macro to avoid making any really silly mistakes here.
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
>  2 files changed, 54 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fbcafc7cc075..44094a25a110 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -990,7 +990,7 @@ struct drm_i915_private {
>  	struct workqueue_struct *flip_wq;
>  
>  	/* pm private clock gating functions */
> -	struct drm_i915_cg_funcs cg_funcs;
> +	const struct drm_i915_cg_funcs *cg_funcs;
>  
>  	/* pm display functions */
>  	struct drm_i915_wm_disp_funcs wm_disp;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7a457646fb84..44f5582531ac 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>  {
> -	dev_priv->cg_funcs.init_clock_gating(dev_priv);
> +	dev_priv->cg_funcs->init_clock_gating(dev_priv);
>  }
>  
>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  		    "No clock gating settings or workarounds applied.\n");
>  }
>  
> +#define CG_FUNCS(platform) \
> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
> +	.init_clock_gating = platform##_init_clock_gating     \
> +}
> +
> +CG_FUNCS(adlp);
> +CG_FUNCS(dg1);
> +CG_FUNCS(gen12lp);
> +CG_FUNCS(icl);
> +CG_FUNCS(cfl);
> +CG_FUNCS(skl);
> +CG_FUNCS(kbl);
> +CG_FUNCS(bxt);
> +CG_FUNCS(glk);
> +CG_FUNCS(bdw);
> +CG_FUNCS(chv);
> +CG_FUNCS(hsw);
> +CG_FUNCS(ivb);
> +CG_FUNCS(vlv);
> +CG_FUNCS(gen6);
> +CG_FUNCS(ilk);
> +CG_FUNCS(g4x);
> +CG_FUNCS(i965gm);
> +CG_FUNCS(i965g);
> +CG_FUNCS(gen3);
> +CG_FUNCS(i85x);
> +CG_FUNCS(i830);
> +CG_FUNCS(nop);

#undef CF_FUNCS

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> +
>  /**
>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>   * @dev_priv: device private
> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_ALDERLAKE_P(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
> +		dev_priv->cg_funcs = &adlp_cg_funcs;
>  	else if (IS_DG1(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
> +		dev_priv->cg_funcs = &dg1_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 12)
> -		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
> +		dev_priv->cg_funcs = &gen12lp_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 11)
> -		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
> +		dev_priv->cg_funcs = &icl_cg_funcs;
>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
> +		dev_priv->cg_funcs = &cfl_cg_funcs;
>  	else if (IS_SKYLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
> +		dev_priv->cg_funcs = &skl_cg_funcs;
>  	else if (IS_KABYLAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
> +		dev_priv->cg_funcs = &kbl_cg_funcs;
>  	else if (IS_BROXTON(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
> +		dev_priv->cg_funcs = &bxt_cg_funcs;
>  	else if (IS_GEMINILAKE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
> +		dev_priv->cg_funcs = &glk_cg_funcs;
>  	else if (IS_BROADWELL(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
> +		dev_priv->cg_funcs = &bdw_cg_funcs;
>  	else if (IS_CHERRYVIEW(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
> +		dev_priv->cg_funcs = &chv_cg_funcs;
>  	else if (IS_HASWELL(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
> +		dev_priv->cg_funcs = &hsw_cg_funcs;
>  	else if (IS_IVYBRIDGE(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
> +		dev_priv->cg_funcs = &ivb_cg_funcs;
>  	else if (IS_VALLEYVIEW(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
> +		dev_priv->cg_funcs = &vlv_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 6)
> -		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
> +		dev_priv->cg_funcs = &gen6_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 5)
> -		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
> +		dev_priv->cg_funcs = &ilk_cg_funcs;
>  	else if (IS_G4X(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
> +		dev_priv->cg_funcs = &g4x_cg_funcs;
>  	else if (IS_I965GM(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
> +		dev_priv->cg_funcs = &i965gm_cg_funcs;
>  	else if (IS_I965G(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
> +		dev_priv->cg_funcs = &i965g_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 3)
> -		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
> +		dev_priv->cg_funcs = &gen3_cg_funcs;
>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> -		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
> +		dev_priv->cg_funcs = &i85x_cg_funcs;
>  	else if (GRAPHICS_VER(dev_priv) == 2)
> -		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
> +		dev_priv->cg_funcs = &i830_cg_funcs;
>  	else {
>  		MISSING_CASE(INTEL_DEVID(dev_priv));
> -		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
> +		dev_priv->cg_funcs = &nop_cg_funcs;
>  	}
>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 20/21] drm/i915: constify clock gating init vtable.

[Jani Nikula]

On Wed, 08 Sep 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
>> From: Dave Airlie <airlied@redhat.com>
>>
>> I used a macro to avoid making any really silly mistakes here.
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c | 77 +++++++++++++++++++++++----------
>>  2 files changed, 54 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index fbcafc7cc075..44094a25a110 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -990,7 +990,7 @@ struct drm_i915_private {
>>  	struct workqueue_struct *flip_wq;
>>  
>>  	/* pm private clock gating functions */
>> -	struct drm_i915_cg_funcs cg_funcs;
>> +	const struct drm_i915_cg_funcs *cg_funcs;
>>  
>>  	/* pm display functions */
>>  	struct drm_i915_wm_disp_funcs wm_disp;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 7a457646fb84..44f5582531ac 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
>>  
>>  void intel_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	dev_priv->cg_funcs.init_clock_gating(dev_priv);
>> +	dev_priv->cg_funcs->init_clock_gating(dev_priv);
>>  }
>>  
>>  void intel_suspend_hw(struct drm_i915_private *dev_priv)
>> @@ -7886,6 +7886,35 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>  		    "No clock gating settings or workarounds applied.\n");
>>  }
>>  
>> +#define CG_FUNCS(platform) \
>> +static const struct drm_i915_cg_funcs platform##_cg_funcs = { \
>> +	.init_clock_gating = platform##_init_clock_gating     \
>> +}
>> +
>> +CG_FUNCS(adlp);
>> +CG_FUNCS(dg1);
>> +CG_FUNCS(gen12lp);
>> +CG_FUNCS(icl);
>> +CG_FUNCS(cfl);
>> +CG_FUNCS(skl);
>> +CG_FUNCS(kbl);
>> +CG_FUNCS(bxt);
>> +CG_FUNCS(glk);
>> +CG_FUNCS(bdw);
>> +CG_FUNCS(chv);
>> +CG_FUNCS(hsw);
>> +CG_FUNCS(ivb);
>> +CG_FUNCS(vlv);
>> +CG_FUNCS(gen6);
>> +CG_FUNCS(ilk);
>> +CG_FUNCS(g4x);
>> +CG_FUNCS(i965gm);
>> +CG_FUNCS(i965g);
>> +CG_FUNCS(gen3);
>> +CG_FUNCS(i85x);
>> +CG_FUNCS(i830);
>> +CG_FUNCS(nop);
>
> #undef CF_FUNCS

#undef CG_FUNCS, obviously.

>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
>> +
>>  /**
>>   * intel_init_clock_gating_hooks - setup the clock gating hooks
>>   * @dev_priv: device private
>> @@ -7898,52 +7927,52 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>  {
>>  	if (IS_ALDERLAKE_P(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = adlp_init_clock_gating;
>> +		dev_priv->cg_funcs = &adlp_cg_funcs;
>>  	else if (IS_DG1(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = dg1_init_clock_gating;
>> +		dev_priv->cg_funcs = &dg1_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 12)
>> -		dev_priv->cg_funcs.init_clock_gating = gen12lp_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen12lp_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 11)
>> -		dev_priv->cg_funcs.init_clock_gating = icl_init_clock_gating;
>> +		dev_priv->cg_funcs = &icl_cg_funcs;
>>  	else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = cfl_init_clock_gating;
>> +		dev_priv->cg_funcs = &cfl_cg_funcs;
>>  	else if (IS_SKYLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = skl_init_clock_gating;
>> +		dev_priv->cg_funcs = &skl_cg_funcs;
>>  	else if (IS_KABYLAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = kbl_init_clock_gating;
>> +		dev_priv->cg_funcs = &kbl_cg_funcs;
>>  	else if (IS_BROXTON(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = bxt_init_clock_gating;
>> +		dev_priv->cg_funcs = &bxt_cg_funcs;
>>  	else if (IS_GEMINILAKE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = glk_init_clock_gating;
>> +		dev_priv->cg_funcs = &glk_cg_funcs;
>>  	else if (IS_BROADWELL(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = bdw_init_clock_gating;
>> +		dev_priv->cg_funcs = &bdw_cg_funcs;
>>  	else if (IS_CHERRYVIEW(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = chv_init_clock_gating;
>> +		dev_priv->cg_funcs = &chv_cg_funcs;
>>  	else if (IS_HASWELL(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = hsw_init_clock_gating;
>> +		dev_priv->cg_funcs = &hsw_cg_funcs;
>>  	else if (IS_IVYBRIDGE(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = ivb_init_clock_gating;
>> +		dev_priv->cg_funcs = &ivb_cg_funcs;
>>  	else if (IS_VALLEYVIEW(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = vlv_init_clock_gating;
>> +		dev_priv->cg_funcs = &vlv_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 6)
>> -		dev_priv->cg_funcs.init_clock_gating = gen6_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen6_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 5)
>> -		dev_priv->cg_funcs.init_clock_gating = ilk_init_clock_gating;
>> +		dev_priv->cg_funcs = &ilk_cg_funcs;
>>  	else if (IS_G4X(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = g4x_init_clock_gating;
>> +		dev_priv->cg_funcs = &g4x_cg_funcs;
>>  	else if (IS_I965GM(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i965gm_init_clock_gating;
>> +		dev_priv->cg_funcs = &i965gm_cg_funcs;
>>  	else if (IS_I965G(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i965g_init_clock_gating;
>> +		dev_priv->cg_funcs = &i965g_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 3)
>> -		dev_priv->cg_funcs.init_clock_gating = gen3_init_clock_gating;
>> +		dev_priv->cg_funcs = &gen3_cg_funcs;
>>  	else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
>> -		dev_priv->cg_funcs.init_clock_gating = i85x_init_clock_gating;
>> +		dev_priv->cg_funcs = &i85x_cg_funcs;
>>  	else if (GRAPHICS_VER(dev_priv) == 2)
>> -		dev_priv->cg_funcs.init_clock_gating = i830_init_clock_gating;
>> +		dev_priv->cg_funcs = &i830_cg_funcs;
>>  	else {
>>  		MISSING_CASE(INTEL_DEVID(dev_priv));
>> -		dev_priv->cg_funcs.init_clock_gating = nop_init_clock_gating;
>> +		dev_priv->cg_funcs = &nop_cg_funcs;
>>  	}
>>  }

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 12/21] drm/i915: constify fdi link training vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> Avoid having writeable function pointers.
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_fdi.c     | 18 +++++++++++++++---
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  3 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 87950202f4ce..0ad577aceb9d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2100,7 +2100,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state,
>  	assert_pch_transcoder_disabled(dev_priv, pipe);
>  
>  	/* For PCH output, training FDI link */
> -	dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
> +	dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
>  
>  	/* We need to program the right clock selection before writing the pixel
>  	 * mutliplier into the DPLL. */
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index d9f952e0c67f..68aa9c7b18ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -1005,15 +1005,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private *dev_priv)
>  	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
>  }
>  
> +static const struct drm_i915_fdi_link_train_funcs ilk_funcs = {
> +	.fdi_link_train = ilk_fdi_link_train

Oh, I guess we could add , at the end of all of these, across all
patches, even if some of them currently hold only one member. It's just
so much cleaner if ever you need to add another member.

BR,
Jani.


> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs gen6_funcs = {
> +	.fdi_link_train = gen6_fdi_link_train
> +};
> +
> +static const struct drm_i915_fdi_link_train_funcs ivb_funcs = {
> +	.fdi_link_train = ivb_manual_fdi_link_train
> +};
> +
>  void
>  intel_fdi_init_hook(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_IRONLAKE(dev_priv)) {
> -		dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
> +		dev_priv->fdi_funcs = &ilk_funcs;
>  	} else if (IS_SANDYBRIDGE(dev_priv)) {
> -		dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
> +		dev_priv->fdi_funcs = &gen6_funcs;
>  	} else if (IS_IVYBRIDGE(dev_priv)) {
>  		/* FIXME: detect B0+ stepping and use auto training */
> -		dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
> +		dev_priv->fdi_funcs = &ivb_funcs;
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 461ab0a0f088..b3765222e717 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1006,7 +1006,7 @@ struct drm_i915_private {
>  	struct drm_i915_irq_funcs irq_funcs;
>  
>  	/* fdi display functions */
> -	struct drm_i915_fdi_link_train_funcs fdi_funcs;
> +	const struct drm_i915_fdi_link_train_funcs *fdi_funcs;
>  
>  	/* display pll funcs */
>  	struct drm_i915_dpll_funcs dpll_funcs;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] ✗ Fi.CI.DOCS: warning for i915/display: split and constify vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: i915/display: split and constify vtable
> URL   : https://patchwork.freedesktop.org/series/94459/
> State : warning
>
> == Summary ==
>
> $ make htmldocs 2>&1 > /dev/null | grep i915
> ./drivers/gpu/drm/i915/display/intel_display.c:164: warning: Excess function parameter 'crtc' description in 'intel_update_watermarks'

Seems legit, please update the kernel-doc.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 21/21] drm/i915: constify display wm vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> From: Dave Airlie <airlied@redhat.com>
>
> This adds some extra checks for the table pointer being
> valid due to some paths not setting it due to failing
> CxSR.

Can we just add a

static const struct drm_i915_wm_disp_funcs nop_wm_funcs = {
};

and point dev_priv->wm_disp at that so we can avoid the double checks?


Other than that,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 56 ++++++++-------
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c              | 74 ++++++++++++++------
>  3 files changed, 81 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 20fd35c6858c..a3d6ab0795a3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -161,8 +161,8 @@ static void intel_modeset_setup_hw_state(struct drm_device *dev,
>   */
>  static void intel_update_watermarks(struct drm_i915_private *dev_priv)
>  {
> -	if (dev_priv->wm_disp.update_wm)
> -		dev_priv->wm_disp.update_wm(dev_priv);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->update_wm)
> +		dev_priv->wm_disp->update_wm(dev_priv);
>  }
>  
>  /* returns HPLL frequency in kHz */
> @@ -2566,8 +2566,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state,
>  		 * we'll continue to update watermarks the old way, if flags tell
>  		 * us to.
>  		 */
> -		if (dev_priv->wm_disp.initial_watermarks)
> -			dev_priv->wm_disp.initial_watermarks(state, crtc);
> +		if (dev_priv->wm_disp->initial_watermarks)
> +			dev_priv->wm_disp->initial_watermarks(state, crtc);
>  		else if (new_crtc_state->update_wm_pre)
>  			intel_update_watermarks(dev_priv);
>  	}
> @@ -2941,8 +2941,8 @@ static void ilk_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	if (dev_priv->wm_disp.initial_watermarks)
> -		dev_priv->wm_disp.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp->initial_watermarks)
> +		dev_priv->wm_disp->initial_watermarks(state, crtc);
>  	intel_enable_pipe(new_crtc_state);
>  
>  	if (new_crtc_state->has_pch_encoder)
> @@ -3152,8 +3152,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state,
>  	if (DISPLAY_VER(dev_priv) >= 11)
>  		icl_set_pipe_chicken(new_crtc_state);
>  
> -	if (dev_priv->wm_disp.initial_watermarks)
> -		dev_priv->wm_disp.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
> +		dev_priv->wm_disp->initial_watermarks(state, crtc);
>  
>  	if (DISPLAY_VER(dev_priv) >= 11) {
>  		const struct intel_dbuf_state *dbuf_state =
> @@ -3570,7 +3570,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	dev_priv->wm_disp.initial_watermarks(state, crtc);
> +	dev_priv->wm_disp->initial_watermarks(state, crtc);
>  	intel_enable_pipe(new_crtc_state);
>  
>  	intel_crtc_vblank_on(new_crtc_state);
> @@ -3613,8 +3613,8 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state,
>  	/* update DSPCNTR to configure gamma for pipe bottom color */
>  	intel_disable_primary_plane(new_crtc_state);
>  
> -	if (dev_priv->wm_disp.initial_watermarks)
> -		dev_priv->wm_disp.initial_watermarks(state, crtc);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
> +		dev_priv->wm_disp->initial_watermarks(state, crtc);
>  	else
>  		intel_update_watermarks(dev_priv);
>  	intel_enable_pipe(new_crtc_state);
> @@ -3682,7 +3682,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
>  	if (DISPLAY_VER(dev_priv) != 2)
>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>  
> -	if (!dev_priv->wm_disp.initial_watermarks)
> +	if (dev_priv->wm_disp && !dev_priv->wm_disp->initial_watermarks)
>  		intel_update_watermarks(dev_priv);
>  
>  	/* clock the pipe down to 640x480@60 to potentially save power */
> @@ -6790,8 +6790,8 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  			return ret;
>  	}
>  
> -	if (dev_priv->wm_disp.compute_pipe_wm) {
> -		ret = dev_priv->wm_disp.compute_pipe_wm(state, crtc);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_pipe_wm) {
> +		ret = dev_priv->wm_disp->compute_pipe_wm(state, crtc);
>  		if (ret) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "Target pipe watermarks are invalid\n");
> @@ -6800,9 +6800,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  
>  	}
>  
> -	if (dev_priv->wm_disp.compute_intermediate_wm) {
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_intermediate_wm) {
>  		if (drm_WARN_ON(&dev_priv->drm,
> -				!dev_priv->wm_disp.compute_pipe_wm))
> +				!dev_priv->wm_disp->compute_pipe_wm))
>  			return 0;
>  
>  		/*
> @@ -6810,7 +6810,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
>  		 * old state and the new state.  We can program these
>  		 * immediately.
>  		 */
> -		ret = dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
> +		ret = dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
>  		if (ret) {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "No valid intermediate pipe watermarks are possible\n");
> @@ -8919,8 +8919,8 @@ static int calc_watermark_data(struct intel_atomic_state *state)
>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  
>  	/* Is there platform-specific watermark information to calculate? */
> -	if (dev_priv->wm_disp.compute_global_watermarks)
> -		return dev_priv->wm_disp.compute_global_watermarks(state);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->compute_global_watermarks)
> +		return dev_priv->wm_disp->compute_global_watermarks(state);
>  
>  	return 0;
>  }
> @@ -9745,8 +9745,8 @@ static void commit_pipe_pre_planes(struct intel_atomic_state *state,
>  		intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
>  	}
>  
> -	if (dev_priv->wm_disp.atomic_update_watermarks)
> -		dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
> +	if (dev_priv->wm_disp && dev_priv->wm_disp->atomic_update_watermarks)
> +		dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
>  }
>  
>  static void commit_pipe_post_planes(struct intel_atomic_state *state,
> @@ -9874,8 +9874,8 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>  	/* FIXME unify this for all platforms */
>  	if (!new_crtc_state->hw.active &&
>  	    !HAS_GMCH(dev_priv) &&
> -	    dev_priv->wm_disp.initial_watermarks)
> -		dev_priv->wm_disp.initial_watermarks(state, crtc);
> +	    dev_priv->wm_disp && dev_priv->wm_disp->initial_watermarks)
> +		dev_priv->wm_disp->initial_watermarks(state, crtc);
>  }
>  
>  static void intel_commit_modeset_disables(struct intel_atomic_state *state)
> @@ -10297,8 +10297,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
>  			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
>  
> -		if (dev_priv->wm_disp.optimize_watermarks)
> -			dev_priv->wm_disp.optimize_watermarks(state, crtc);
> +		if (dev_priv->wm_disp && dev_priv->wm_disp->optimize_watermarks)
> +			dev_priv->wm_disp->optimize_watermarks(state, crtc);
>  	}
>  
>  	intel_dbuf_post_plane_update(state);
> @@ -11387,7 +11387,9 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
>  	int i;
>  
>  	/* Only supported on platforms that use atomic watermark design */
> -	if (!dev_priv->wm_disp.optimize_watermarks)
> +	if (!dev_priv->wm_disp)
> +		return;
> +	if (!dev_priv->wm_disp->optimize_watermarks)
>  		return;
>  
>  	state = drm_atomic_state_alloc(&dev_priv->drm);
> @@ -11420,7 +11422,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
>  	/* Write calculated watermark values back */
>  	for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
>  		crtc_state->wm.need_postvbl_update = true;
> -		dev_priv->wm_disp.optimize_watermarks(intel_state, crtc);
> +		dev_priv->wm_disp->optimize_watermarks(intel_state, crtc);
>  
>  		to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
>  	}
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44094a25a110..eacd30c076a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -993,7 +993,7 @@ struct drm_i915_private {
>  	const struct drm_i915_cg_funcs *cg_funcs;
>  
>  	/* pm display functions */
> -	struct drm_i915_wm_disp_funcs wm_disp;
> +	const struct drm_i915_wm_disp_funcs *wm_disp;
>  
>  	/* irq display functions */
>  	const struct drm_i915_irq_funcs *irq_funcs;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 44f5582531ac..cceeb059f801 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7976,6 +7976,48 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  	}
>  }
>  
> +static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
> +	.compute_global_watermarks = skl_compute_wm
> +};
> +
> +static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
> +	.compute_pipe_wm = ilk_compute_pipe_wm,
> +	.compute_intermediate_wm = ilk_compute_intermediate_wm,
> +	.initial_watermarks = ilk_initial_watermarks,
> +	.optimize_watermarks = ilk_optimize_watermarks
> +};
> +
> +static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
> +	.compute_pipe_wm = vlv_compute_pipe_wm,
> +	.compute_intermediate_wm = vlv_compute_intermediate_wm,
> +	.initial_watermarks = vlv_initial_watermarks,
> +	.optimize_watermarks = vlv_optimize_watermarks,
> +	.atomic_update_watermarks = vlv_atomic_update_fifo
> +};
> +
> +static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
> +	.compute_pipe_wm = g4x_compute_pipe_wm,
> +	.compute_intermediate_wm = g4x_compute_intermediate_wm,
> +	.initial_watermarks = g4x_initial_watermarks,
> +	.optimize_watermarks = g4x_optimize_watermarks
> +};
> +
> +static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
> +	.update_wm = pnv_update_wm,
> +};
> +
> +static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
> +	.update_wm = i965_update_wm,
> +};
> +
> +static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
> +	.update_wm = i9xx_update_wm,
> +};
> +
> +static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
> +	.update_wm = i845_update_wm,
> +};
> +
>  /* Set up chip specific power management-related functions */
>  void intel_init_pm(struct drm_i915_private *dev_priv)
>  {
> @@ -7991,7 +8033,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  	/* For FIFO watermark updates */
>  	if (DISPLAY_VER(dev_priv) >= 9) {
>  		skl_setup_wm_latency(dev_priv);
> -		dev_priv->wm_disp.compute_global_watermarks = skl_compute_wm;
> +		dev_priv->wm_disp = &skl_wm_funcs;
>  	} else if (HAS_PCH_SPLIT(dev_priv)) {
>  		ilk_setup_wm_latency(dev_priv);
>  
> @@ -7999,13 +8041,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
>  		    (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
>  		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> -			dev_priv->wm_disp.compute_pipe_wm = ilk_compute_pipe_wm;
> -			dev_priv->wm_disp.compute_intermediate_wm =
> -				ilk_compute_intermediate_wm;
> -			dev_priv->wm_disp.initial_watermarks =
> -				ilk_initial_watermarks;
> -			dev_priv->wm_disp.optimize_watermarks =
> -				ilk_optimize_watermarks;
> +			dev_priv->wm_disp = &ilk_wm_funcs;
>  		} else {
>  			drm_dbg_kms(&dev_priv->drm,
>  				    "Failed to read display plane latency. "
> @@ -8013,17 +8049,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  		}
>  	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		vlv_setup_wm_latency(dev_priv);
> -		dev_priv->wm_disp.compute_pipe_wm = vlv_compute_pipe_wm;
> -		dev_priv->wm_disp.compute_intermediate_wm = vlv_compute_intermediate_wm;
> -		dev_priv->wm_disp.initial_watermarks = vlv_initial_watermarks;
> -		dev_priv->wm_disp.optimize_watermarks = vlv_optimize_watermarks;
> -		dev_priv->wm_disp.atomic_update_watermarks = vlv_atomic_update_fifo;
> +		dev_priv->wm_disp = &vlv_wm_funcs;
>  	} else if (IS_G4X(dev_priv)) {
>  		g4x_setup_wm_latency(dev_priv);
> -		dev_priv->wm_disp.compute_pipe_wm = g4x_compute_pipe_wm;
> -		dev_priv->wm_disp.compute_intermediate_wm = g4x_compute_intermediate_wm;
> -		dev_priv->wm_disp.initial_watermarks = g4x_initial_watermarks;
> -		dev_priv->wm_disp.optimize_watermarks = g4x_optimize_watermarks;
> +		dev_priv->wm_disp = &g4x_wm_funcs;
>  	} else if (IS_PINEVIEW(dev_priv)) {
>  		if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
>  					    dev_priv->is_ddr3,
> @@ -8037,18 +8066,17 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
>  				 dev_priv->fsb_freq, dev_priv->mem_freq);
>  			/* Disable CxSR and never update its watermark again */
>  			intel_set_memory_cxsr(dev_priv, false);
> -			dev_priv->wm_disp.update_wm = NULL;
>  		} else
> -			dev_priv->wm_disp.update_wm = pnv_update_wm;
> +			dev_priv->wm_disp = &pnv_wm_funcs;
>  	} else if (DISPLAY_VER(dev_priv) == 4) {
> -		dev_priv->wm_disp.update_wm = i965_update_wm;
> +		dev_priv->wm_disp = &i965_wm_funcs;
>  	} else if (DISPLAY_VER(dev_priv) == 3) {
> -		dev_priv->wm_disp.update_wm = i9xx_update_wm;
> +		dev_priv->wm_disp = &i9xx_wm_funcs;
>  	} else if (DISPLAY_VER(dev_priv) == 2) {
>  		if (INTEL_NUM_PIPES(dev_priv) == 1)
> -			dev_priv->wm_disp.update_wm = i845_update_wm;
> +			dev_priv->wm_disp = &i845_wm_funcs;
>  		else
> -			dev_priv->wm_disp.update_wm = i9xx_update_wm;
> +			dev_priv->wm_disp = &i9xx_wm_funcs;
>  	} else {
>  		drm_err(&dev_priv->drm,
>  			"unexpected fall-through in %s\n", __func__);

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 00/21] i915/display: split and constify vtable

[Jani Nikula]

On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> This is orthogonal to my display ptr refactoring and should probably
> be applied first.

Yeah, overall nice cleanups, and a much easier bandwagon to jump onto
than the other one. ;)

Nothing too bad, a few bugs had crept in, and I had some nitpicks.

> The display funcs vtable was a bit of mess, lots of intermixing of
> internal display functionality and interfaces to watermarks/irqs.
>
> It's also considered not great security practice to leave writeable
> function pointers around for exploits to get into.

On the one hand I get this, but on the other hand the pointers to the
structs do remain writable. I suppose it increases the complexity of an
exploit by some margin?

In any case, I think this is cleaner in general, and that's enough merit
for the change, regardless of the security aspect.

BR,
Jani.

>
> This series attempts to address both problems, first there are a
> few cleanups, then it splits the function table into multiple pieces.
> Some of the splits might be bikesheds but I think we should apply first
> and merge things later if there is good reason.
>
> The second half converts all the vtables to static const structs,
> I've used macros in some of them to make it less messy, the cdclk
> one is probably the worst one.
>
> Dave.
>
>

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

[Dave Airlie]

On Wed, 8 Sept 2021 at 19:33, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > A vague goal is to have the vfunc table be the api between
> > wm and display, not having direction function calls cross
> > the boundary.
> >
> > This aligns the legacy update_wm with the newer vfuncs.
> >
> > The comment probably needs to live somewhere else, it seems
> > like it should live in the pm side though not the display side,
> > but I brought it along for the ride.
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_pm.c              | 39 -------------------
> >  drivers/gpu/drm/i915/intel_pm.h              |  1 -
> >  3 files changed, 40 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index d95283bf2631..b495371c1889 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>
> We haven't been axing stuff out of intel_display.c so we could add
> somethign else back! ;)
>
> A new file for watermarks or display pm? Ville?

The main reason I landed it there, was because all the other calls to
the wm funcs are in intel_display, and this wrapper is very small and
ends up being a static, the comment on the other hand, I've no idea
where it should have landed.

Dave.

Re: [Intel-gfx] [PATCH 11/21] drm/i915: split the dpll clock compute out from display vtable.

[Dave Airlie]

On Wed, 8 Sept 2021 at 20:09, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>
> On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > From: Dave Airlie <airlied@redhat.com>
> >
> > this could be merged later but for now it's simple to split it out.
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c |  6 +++---
> >  drivers/gpu/drm/i915/display/intel_dpll.c    | 16 ++++++++--------
> >  drivers/gpu/drm/i915/i915_drv.h              |  8 +++++++-
> >  3 files changed, 18 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index b981a923cc2f..87950202f4ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6768,10 +6768,10 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
> >               crtc_state->update_wm_post = true;
> >
> >       if (mode_changed && crtc_state->hw.enable &&
> > -         dev_priv->display.crtc_compute_clock &&
> > +         dev_priv->dpll_funcs.crtc_compute_clock &&
> >           !crtc_state->bigjoiner_slave &&
> >           !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) {
> > -             ret = dev_priv->display.crtc_compute_clock(crtc_state);
> > +             ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
> >               if (ret)
> >                       return ret;
>
> It was there before, but yuck. Conditions like this with checks on the
> existence of a vfunc are really ugly. Could benefit from a wrapper - but
> that requires figuring out what the condition actually is. *facepalm*.
>
> >       }
> > @@ -8807,7 +8807,7 @@ static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> >       struct intel_crtc *crtc;
> >       int i;
> >
> > -     if (!dev_priv->display.crtc_compute_clock)
> > +     if (!dev_priv->dpll_funcs.crtc_compute_clock)
> >               return;
> >
> >       for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index 210f91f4a576..9326c7cbb05c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1367,21 +1367,21 @@ void
> >  intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
> >  {
> >       if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = hsw_crtc_compute_clock;
> >       else if (HAS_PCH_SPLIT(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = ilk_crtc_compute_clock;
> >       else if (IS_CHERRYVIEW(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = chv_crtc_compute_clock;
> >       else if (IS_VALLEYVIEW(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = vlv_crtc_compute_clock;
> >       else if (IS_G4X(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = g4x_crtc_compute_clock;
> >       else if (IS_PINEVIEW(dev_priv))
> > -             dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = pnv_crtc_compute_clock;
> >       else if (DISPLAY_VER(dev_priv) != 2)
> > -             dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = i9xx_crtc_compute_clock;
> >       else
> > -             dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
> > +             dev_priv->dpll_funcs.crtc_compute_clock = i8xx_crtc_compute_clock;
> >  }
> >
> >  static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 49b23ea46475..461ab0a0f088 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -393,6 +393,10 @@ struct drm_i915_fdi_link_train_funcs {
> >                              const struct intel_crtc_state *crtc_state);
> >  };
> >
> > +struct drm_i915_dpll_funcs {
>
> Nitpick, intel_dpll_funcs. Starting to spot the pattern? ;D
>
> Part of the point is that I think these may eventually move to their own
> headers, and I like to drive naming structs and functions after the file
> name. So, you'd find intel_dpll_* stuff in intel_dpll.[ch]. Or if they
> stay in i915_drv.h, at least that's the chrystal clear context.

I've got a follow up series to move some of them as an RFC locally,
so I'm quite happy to rename them all!

Dave.

Re: [Intel-gfx] [PATCH 03/21] drm/i915/wm: move the update watermark wrapper to display side.

[Ville Syrjälä]

On Thu, Sep 09, 2021 at 06:40:59AM +1000, Dave Airlie wrote:
> On Wed, 8 Sept 2021 at 19:33, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >
> > On Wed, 08 Sep 2021, Dave Airlie <airlied@gmail.com> wrote:
> > > From: Dave Airlie <airlied@redhat.com>
> > >
> > > A vague goal is to have the vfunc table be the api between
> > > wm and display, not having direction function calls cross
> > > the boundary.
> > >
> > > This aligns the legacy update_wm with the newer vfuncs.
> > >
> > > The comment probably needs to live somewhere else, it seems
> > > like it should live in the pm side though not the display side,
> > > but I brought it along for the ride.
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c | 40 ++++++++++++++++++++
> > >  drivers/gpu/drm/i915/intel_pm.c              | 39 -------------------
> > >  drivers/gpu/drm/i915/intel_pm.h              |  1 -
> > >  3 files changed, 40 insertions(+), 40 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index d95283bf2631..b495371c1889 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> >
> > We haven't been axing stuff out of intel_display.c so we could add
> > somethign else back! ;)
> >
> > A new file for watermarks or display pm? Ville?

We need multiple files. But I've been hoping to land more watermark
refactoring first so I'd not have to rebase tons of stuff across
massive code motion patches. Unfortunatley review for that stuff
is hard to come by.

Regarding the .update_wm() hook in particular, it's just an ancient
thing that is not meant to exist once all the wm code gets atomized.
So no real point in polishing it any further in its current form IMO.

> 
> The main reason I landed it there, was because all the other calls to
> the wm funcs are in intel_display, and this wrapper is very small and
> ends up being a static, the comment on the other hand, I've no idea
> where it should have landed.
> 
> Dave.

-- 
Ville Syrjälä
Intel