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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Jani Nikula" <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: dp 2.0 enabling prep work (rev3)
Date: Thu, 09 Sep 2021 13:48:21 -0000	[thread overview]
Message-ID: <163119530190.16812.4888865882867263924@emeril.freedesktop.org> (raw)
In-Reply-To: <cover.1631191763.git.jani.nikula@intel.com>

== Series Details ==

Series: drm/i915/dp: dp 2.0 enabling prep work (rev3)
URL   : https://patchwork.freedesktop.org/series/93800/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a3665dc8b3d2 drm/dp: add DP 2.0 UHBR link rate and bw code conversions
68ec9d98ee90 drm/dp: use more of the extended receiver cap
48940950af3c drm/dp: add LTTPR DP 2.0 DPCD addresses
a2c94be7e9b9 drm/dp: add helper for extracting adjust 128b/132b TX FFE preset
c762623aaaba drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode
e99cd06140c4 drm/i915/dp: add helper for checking for UHBR link rate
9334d33d2624 drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
13bcc2d6e808 drm/i915/dp: select 128b/132b channel encoding for UHBR rates
1fc3c6d399c1 drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0
23ec558b7af4 drm/i915/dp: add HAS_DP20 macro
fcf2455de71f drm/i915/dg2: use 128b/132b transcoder DDI mode
5a7810bd5e6f drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b
c586238887e7 drm/i915/dg2: update link training for 128b/132b
-:27: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#27: FILE: drivers/gpu/drm/i915/display/intel_ddi.c:1404:
+		return intel_dp->train_set[0] & DP_TX_FFE_PRESET_VALUE_MASK;
+	} else {

total: 0 errors, 1 warnings, 0 checks, 139 lines checked



  parent reply	other threads:[~2021-09-09 13:48 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-09 12:51 [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-09 12:51 ` [Intel-gfx] " Jani Nikula
2021-09-09 12:51 ` [PATCH v3 01/13] drm/dp: add DP 2.0 UHBR link rate and bw code conversions Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:40   ` Ville Syrjälä
2021-09-17 12:40     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 02/13] drm/dp: use more of the extended receiver cap Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 16:18   ` Lyude Paul
2021-09-09 16:18     ` Lyude Paul
2021-09-09 16:18     ` Lyude Paul
2021-09-09 16:18       ` [Intel-gfx] " Lyude Paul
2021-09-09 12:51 ` [PATCH v3 03/13] drm/dp: add LTTPR DP 2.0 DPCD addresses Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-21 22:58   ` Nathan Chancellor
2021-09-22  0:45     ` Stephen Rothwell
2021-09-22 11:10     ` Jani Nikula
2021-09-22 13:49       ` Alex Deucher
2021-09-22 13:49         ` Alex Deucher
2021-09-22 17:32         ` [PATCH] drm/amd/display: Only define DP 2.0 symbols if not already defined Harry Wentland
2021-09-22 17:32           ` [Intel-gfx] " Harry Wentland
2021-09-09 12:51 ` [PATCH v3 04/13] drm/dp: add helper for extracting adjust 128b/132b TX FFE preset Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:51 ` [PATCH v3 05/13] drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b mode Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:54   ` Ville Syrjälä
2021-09-17 12:54     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 06/13] drm/i915/dp: add helper for checking for UHBR link rate Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:41   ` Ville Syrjälä
2021-09-17 12:41     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:51 ` [PATCH v3 07/13] drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates Jani Nikula
2021-09-09 12:51   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 08/13] drm/i915/dp: select 128b/132b channel encoding for UHBR rates Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 09/13] drm/i915/dg2: configure TRANS_DP2_CTL for DP 2.0 Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 10/13] drm/i915/dp: add HAS_DP20 macro Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:42   ` Ville Syrjälä
2021-09-17 12:42     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:52 ` [PATCH v3 11/13] drm/i915/dg2: use 128b/132b transcoder DDI mode Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:51   ` Ville Syrjälä
2021-09-17 12:51     ` [Intel-gfx] " Ville Syrjälä
2021-09-09 12:52 ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-17 12:53   ` [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} " Ville Syrjälä
2021-09-17 12:53     ` [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} " Ville Syrjälä
2021-09-21  8:44     ` Jani Nikula
2021-09-21  8:44       ` [Intel-gfx] " Jani Nikula
2021-09-09 12:52 ` [PATCH v3 13/13] drm/i915/dg2: update link training " Jani Nikula
2021-09-09 12:52   ` [Intel-gfx] " Jani Nikula
2021-09-09 13:48 ` Patchwork [this message]
2021-09-09 13:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dp: dp 2.0 enabling prep work (rev3) Patchwork
2021-09-09 14:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-09 16:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-17 12:54 ` [PATCH v3 00/13] drm/i915/dp: dp 2.0 enabling prep work Jani Nikula
2021-09-17 12:54   ` [Intel-gfx] " Jani Nikula
2021-09-17 16:56   ` Maxime Ripard
2021-09-17 16:56     ` [Intel-gfx] " Maxime Ripard
2021-09-21  8:44     ` Jani Nikula
2021-09-21  8:44       ` [Intel-gfx] " Jani Nikula
2021-09-22 12:54 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev4) Patchwork
2021-09-22 18:24 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dp: dp 2.0 enabling prep work (rev5) Patchwork

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