From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com, philmd@redhat.com,
richard.henderson@linaro.org, laurent@vivier.eu,
peterx@redhat.com, gaosong@loongson.cn, yangxiaojuan@loongson.cn,
alistair.francis@wdc.com, maobibo@loongson.cn,
pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org,
chenhuacai@loongson.cn
Subject: [PATCH v5 14/21] target/loongarch: Add floating point load/store instruction translation
Date: Tue, 14 Sep 2021 21:00:24 +0800 [thread overview]
Message-ID: <1631624431-30658-15-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1631624431-30658-1-git-send-email-gaosong@loongson.cn>
This patch implement floating point load/store instruction translation.
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: XiaoJuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/insn_trans/trans_fmemory.c | 187 ++++++++++++++++++++++++++++
target/loongarch/insns.decode | 24 ++++
target/loongarch/translate.c | 1 +
3 files changed, 212 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_fmemory.c
diff --git a/target/loongarch/insn_trans/trans_fmemory.c b/target/loongarch/insn_trans/trans_fmemory.c
new file mode 100644
index 0000000..eca2b8b
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_fmemory.c
@@ -0,0 +1,187 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+static bool gen_fload_imm(DisasContext *ctx, arg_fmt_fdrjsi12 *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->si12) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->si12);
+ addr = temp;
+ }
+
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+ return true;
+}
+
+static bool gen_fstore_imm(DisasContext *ctx, arg_fmt_fdrjsi12 *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv temp = NULL;
+
+ if (a->si12) {
+ temp = tcg_temp_new();
+ tcg_gen_addi_tl(temp, addr, a->si12);
+ addr = temp;
+ }
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (temp) {
+ tcg_temp_free(temp);
+ }
+ return true;
+}
+
+static bool gen_fload_tl(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool gen_fstore_tl(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ tcg_gen_add_tl(addr, src1, src2);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool gen_fload_gt(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool gen_fstore_gt(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtgt_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool gen_fload_le(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+ tcg_gen_qemu_ld_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+static bool gen_fstore_le(DisasContext *ctx, arg_fmt_fdrjrk *a,
+ MemOp mop, bool nanbox)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
+ TCGv addr = tcg_temp_new();
+
+ gen_helper_asrtle_d(cpu_env, src1, src2);
+ tcg_gen_add_tl(addr, src1, src2);
+
+ if (nanbox) {
+ gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
+ }
+
+ tcg_gen_qemu_st_tl(cpu_fpr[a->fd], addr, ctx->mem_idx, mop);
+
+ tcg_temp_free(addr);
+ return true;
+}
+
+TRANS(fld_s, gen_fload_imm, MO_TESL, true)
+TRANS(fst_s, gen_fstore_imm, MO_TEUL, true)
+TRANS(fld_d, gen_fload_imm, MO_TEQ, false)
+TRANS(fst_d, gen_fstore_imm, MO_TEQ, false)
+TRANS(fldx_s, gen_fload_tl, MO_TESL, true)
+TRANS(fldx_d, gen_fload_tl, MO_TEQ, false)
+TRANS(fstx_s, gen_fstore_tl, MO_TEUL, true)
+TRANS(fstx_d, gen_fstore_tl, MO_TEQ, false)
+TRANS(fldgt_s, gen_fload_gt, MO_TESL, true)
+TRANS(fldgt_d, gen_fload_gt, MO_TEQ, false)
+TRANS(fldle_s, gen_fload_le, MO_TESL, true)
+TRANS(fldle_d, gen_fload_le, MO_TEQ, false)
+TRANS(fstgt_s, gen_fstore_gt, MO_TEUL, true)
+TRANS(fstgt_d, gen_fstore_gt, MO_TEQ, false)
+TRANS(fstle_s, gen_fstore_le, MO_TEUL, true)
+TRANS(fstle_d, gen_fstore_le, MO_TEQ, false)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index febf89a..ea776c2 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -72,6 +72,8 @@
&fmt_fdcj fd cj
&fmt_cdrj cd rj
&fmt_rdcj rd cj
+&fmt_fdrjrk fd rj rk
+&fmt_fdrjsi12 fd rj si12
#
# Formats
@@ -106,6 +108,8 @@
@fmt_fdcj .... ........ ..... ..... .. ... ..... &fmt_fdcj %fd %cj
@fmt_cdrj .... ........ ..... ..... ..... .. ... &fmt_cdrj %cd %rj
@fmt_rdcj .... ........ ..... ..... .. ... ..... &fmt_rdcj %rd %cj
+@fmt_fdrjrk .... ........ ..... ..... ..... ..... &fmt_fdrjrk %fd %rj %rk
+@fmt_fdrjsi12 .... ...... ............ ..... ..... &fmt_fdrjsi12 %fd %rj %si12
#
# Fixed point arithmetic operation instruction
@@ -424,3 +428,23 @@ movfr2cf 0000 00010001 01001 10100 ..... 00 ... @fmt_cdfj
movcf2fr 0000 00010001 01001 10101 00 ... ..... @fmt_fdcj
movgr2cf 0000 00010001 01001 10110 ..... 00 ... @fmt_cdrj
movcf2gr 0000 00010001 01001 10111 00 ... ..... @fmt_rdcj
+
+#
+# Floating point load/store instruction
+#
+fld_s 0010 101100 ............ ..... ..... @fmt_fdrjsi12
+fst_s 0010 101101 ............ ..... ..... @fmt_fdrjsi12
+fld_d 0010 101110 ............ ..... ..... @fmt_fdrjsi12
+fst_d 0010 101111 ............ ..... ..... @fmt_fdrjsi12
+fldx_s 0011 10000011 00000 ..... ..... ..... @fmt_fdrjrk
+fldx_d 0011 10000011 01000 ..... ..... ..... @fmt_fdrjrk
+fstx_s 0011 10000011 10000 ..... ..... ..... @fmt_fdrjrk
+fstx_d 0011 10000011 11000 ..... ..... ..... @fmt_fdrjrk
+fldgt_s 0011 10000111 01000 ..... ..... ..... @fmt_fdrjrk
+fldgt_d 0011 10000111 01001 ..... ..... ..... @fmt_fdrjrk
+fldle_s 0011 10000111 01010 ..... ..... ..... @fmt_fdrjrk
+fldle_d 0011 10000111 01011 ..... ..... ..... @fmt_fdrjrk
+fstgt_s 0011 10000111 01100 ..... ..... ..... @fmt_fdrjrk
+fstgt_d 0011 10000111 01101 ..... ..... ..... @fmt_fdrjrk
+fstle_s 0011 10000111 01110 ..... ..... ..... @fmt_fdrjrk
+fstle_d 0011 10000111 01111 ..... ..... ..... @fmt_fdrjrk
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index c57c8ee..5c2e9ee 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -190,6 +190,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_fcmp.c"
#include "insn_trans/trans_fcnv.c"
#include "insn_trans/trans_fmov.c"
+#include "insn_trans/trans_fmemory.c"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-09-14 13:13 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-14 13:00 [PATCH v5 00/21] Add LoongArch linux-user emulation support Song Gao
2021-09-14 13:00 ` [PATCH v5 01/21] target/loongarch: Add README Song Gao
2021-09-14 13:00 ` [PATCH v5 02/21] target/loongarch: Add core definition Song Gao
2021-09-14 13:00 ` [PATCH v5 03/21] target/loongarch: Add main translation routines Song Gao
2021-09-14 13:00 ` [PATCH v5 04/21] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-09-14 13:30 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 05/21] target/loongarch: Add fixed point shift " Song Gao
2021-09-14 13:33 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 06/21] target/loongarch: Add fixed point bit " Song Gao
2021-09-14 13:45 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 07/21] target/loongarch: Add fixed point load/store " Song Gao
2021-09-14 13:47 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 08/21] target/loongarch: Add fixed point atomic " Song Gao
2021-09-14 13:49 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 09/21] target/loongarch: Add fixed point extra " Song Gao
2021-09-14 13:00 ` [PATCH v5 10/21] target/loongarch: Add floating point arithmetic " Song Gao
2021-09-14 14:15 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 11/21] target/loongarch: Add floating point comparison " Song Gao
2021-09-14 14:21 ` Richard Henderson
2021-09-14 13:00 ` [PATCH v5 12/21] target/loongarch: Add floating point conversion " Song Gao
2021-09-14 13:00 ` [PATCH v5 13/21] target/loongarch: Add floating point move " Song Gao
2021-09-14 14:24 ` Richard Henderson
2021-09-14 13:00 ` Song Gao [this message]
2021-09-14 13:00 ` [PATCH v5 15/21] target/loongarch: Add branch " Song Gao
2021-09-14 13:00 ` [PATCH v5 16/21] target/loongarch: Add disassembler Song Gao
2021-09-14 13:00 ` [PATCH v5 17/21] LoongArch Linux User Emulation Song Gao
2021-09-14 13:00 ` [PATCH v5 18/21] default-configs: Add loongarch linux-user support Song Gao
2021-09-14 13:00 ` [PATCH v5 19/21] target/loongarch: Add target build suport Song Gao
2021-09-14 13:00 ` [PATCH v5 20/21] target/loongarch: 'make check-tcg' support Song Gao
2021-09-14 13:00 ` [PATCH v5 21/21] scripts: add loongarch64 binfmt config Song Gao
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