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From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Borislav Petkov <bp@suse.de>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/fpu] x86/mce: Deduplicate exception handling
Date: Tue, 14 Sep 2021 19:19:36 -0000	[thread overview]
Message-ID: <163164717636.25758.8676151426891714729.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20210908132525.096452100@linutronix.de>

The following commit has been merged into the x86/fpu branch of tip:

Commit-ID:     e42404afc4ca856c48f1e05752541faa3587c472
Gitweb:        https://git.kernel.org/tip/e42404afc4ca856c48f1e05752541faa3587c472
Author:        Thomas Gleixner <tglx@linutronix.de>
AuthorDate:    Wed, 08 Sep 2021 15:29:15 +02:00
Committer:     Borislav Petkov <bp@suse.de>
CommitterDate: Mon, 13 Sep 2021 17:00:23 +02:00

x86/mce: Deduplicate exception handling

Prepare code for further simplification. No functional change.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20210908132525.096452100@linutronix.de
---
 arch/x86/kernel/cpu/mce/core.c | 34 ++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 8cb7816..428eed9 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -373,13 +373,16 @@ static int msr_to_offset(u32 msr)
 	return -1;
 }
 
-__visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
-				      struct pt_regs *regs, int trapnr,
-				      unsigned long error_code,
-				      unsigned long fault_addr)
+static void ex_handler_msr_mce(struct pt_regs *regs, bool wrmsr)
 {
-	pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
-		 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
+	if (wrmsr) {
+		pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
+			 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
+			 regs->ip, (void *)regs->ip);
+	} else {
+		pr_emerg("MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)\n",
+			 (unsigned int)regs->cx, regs->ip, (void *)regs->ip);
+	}
 
 	show_stack_regs(regs);
 
@@ -387,7 +390,14 @@ __visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
 
 	while (true)
 		cpu_relax();
+}
 
+__visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup,
+				      struct pt_regs *regs, int trapnr,
+				      unsigned long error_code,
+				      unsigned long fault_addr)
+{
+	ex_handler_msr_mce(regs, false);
 	return true;
 }
 
@@ -432,17 +442,7 @@ __visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup,
 				      unsigned long error_code,
 				      unsigned long fault_addr)
 {
-	pr_emerg("MSR access error: WRMSR to 0x%x (tried to write 0x%08x%08x) at rIP: 0x%lx (%pS)\n",
-		 (unsigned int)regs->cx, (unsigned int)regs->dx, (unsigned int)regs->ax,
-		  regs->ip, (void *)regs->ip);
-
-	show_stack_regs(regs);
-
-	panic("MCA architectural violation!\n");
-
-	while (true)
-		cpu_relax();
-
+	ex_handler_msr_mce(regs, true);
 	return true;
 }
 

  reply	other threads:[~2021-09-14 19:20 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 13:29 [patch V3 00/20] x86/fpu: Clean up exception fixups and error handling in sigframe related code Thomas Gleixner
2021-09-08 13:29 ` [patch V3 01/20] x86/extable: Tidy up redundant handler functions Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 02/20] x86/extable: Get rid of redundant macros Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 03/20] x86/mce: Deduplicate exception handling Thomas Gleixner
2021-09-14 19:19   ` tip-bot2 for Thomas Gleixner [this message]
2021-09-08 13:29 ` [patch V3 04/20] x86/mce: Get rid of stray semicolons Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 05/20] x86/extable: Rework the exception table mechanics Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 06/20] x86/extable: Provide EX_TYPE_DEFAULT_MCE_SAFE and EX_TYPE_FAULT_MCE_SAFE Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 07/20] x86/copy_mc: Use EX_TYPE_DEFAULT_MCE_SAFE for exception fixups Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 08/20] x86/fpu: Use EX_TYPE_FAULT_MCE_SAFE " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 09/20] x86/extable: Remove EX_TYPE_FAULT from MCE safe fixups Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 10/20] x86/fpu/signal: Clarify exception handling in restore_fpregs_from_user() Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 11/20] x86/fpu: Dont use MCE safe fixups for writing FPU state to user space Thomas Gleixner
2021-09-08 13:29 ` [patch V3 12/20] x86/fpu/signal: Move header zeroing out of xsave_to_user_sigframe() Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 13/20] x86/fpu/signal: Move xstate clearing out of copy_fpregs_to_sigframe() Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 14/20] x86/fpu/signal: Change return type of copy_fpstate_to_sigframe() to boolean Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 15/20] x86/fpu/signal: Change return type of copy_fpregs_to_sigframe() helpers " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-21 10:58   ` [patch V3 15/20] " Anders Roxell
2021-09-21 17:35     ` Nick Desaulniers
2021-09-22 18:23       ` Nick Desaulniers
2021-09-21 20:13     ` Thomas Gleixner
2021-09-22 19:42       ` Anders Roxell
2021-09-08 13:29 ` [patch V3 16/20] x86/signal: Change return type of restore_sigcontext() " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 17/20] x86/fpu/signal: Change return type of fpu__restore_sig() " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 18/20] x86/fpu/signal: Change return type of __fpu_restore_sig() " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 19/20] x86/fpu/signal: Change return code of check_xstate_in_sigframe() " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 13:29 ` [patch V3 20/20] x86/fpu/signal: Change return code of restore_fpregs_from_user() " Thomas Gleixner
2021-09-14 19:19   ` [tip: x86/fpu] " tip-bot2 for Thomas Gleixner
2021-09-08 15:57 ` [patch V3 00/20] x86/fpu: Clean up exception fixups and error handling in sigframe related code Luck, Tony
2021-09-08 17:01   ` Luck, Tony

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