* [PATCH v5 0/4] arm: aspeed: Add UART routing support
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add UART routing driver and the device tree nodes.
v5:
- Fix typo in YAML file to solve the compatible string not found error
v4:
- Convert aspeed-lpc bindings to YAML schema to resolve dependecy issues
v3:
- Add individual bindings in YAML
- Add support for AST24xx (AST25xx shares the same design)
- Add more explanation for the sysfs ABI
v2:
- Add dt-bindings
- Add ABI documents for the exported sysfs interface
- Revise driver implementation suggested by Joel
Chia-Wei Wang (4):
dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
dt-bindings: aspeed: Add UART routing controller
soc: aspeed: Add UART routing support
ARM: dts: aspeed: Add uart routing to device tree
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 -----
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 191 ++++++
.../bindings/soc/aspeed/uart-routing.yaml | 70 ++
arch/arm/boot/dts/aspeed-g4.dtsi | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 6 +
arch/arm/boot/dts/aspeed-g6.dtsi | 6 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
10 files changed, 912 insertions(+), 161 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
--
2.17.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v5 0/4] arm: aspeed: Add UART routing support
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: yulei.sh, osk
Add UART routing driver and the device tree nodes.
v5:
- Fix typo in YAML file to solve the compatible string not found error
v4:
- Convert aspeed-lpc bindings to YAML schema to resolve dependecy issues
v3:
- Add individual bindings in YAML
- Add support for AST24xx (AST25xx shares the same design)
- Add more explanation for the sysfs ABI
v2:
- Add dt-bindings
- Add ABI documents for the exported sysfs interface
- Revise driver implementation suggested by Joel
Chia-Wei Wang (4):
dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
dt-bindings: aspeed: Add UART routing controller
soc: aspeed: Add UART routing support
ARM: dts: aspeed: Add uart routing to device tree
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 -----
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 191 ++++++
.../bindings/soc/aspeed/uart-routing.yaml | 70 ++
arch/arm/boot/dts/aspeed-g4.dtsi | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 6 +
arch/arm/boot/dts/aspeed-g6.dtsi | 6 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
10 files changed, 912 insertions(+), 161 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
--
2.17.1
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v5 0/4] arm: aspeed: Add UART routing support
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add UART routing driver and the device tree nodes.
v5:
- Fix typo in YAML file to solve the compatible string not found error
v4:
- Convert aspeed-lpc bindings to YAML schema to resolve dependecy issues
v3:
- Add individual bindings in YAML
- Add support for AST24xx (AST25xx shares the same design)
- Add more explanation for the sysfs ABI
v2:
- Add dt-bindings
- Add ABI documents for the exported sysfs interface
- Revise driver implementation suggested by Joel
Chia-Wei Wang (4):
dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
dt-bindings: aspeed: Add UART routing controller
soc: aspeed: Add UART routing support
ARM: dts: aspeed: Add uart routing to device tree
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 -----
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 191 ++++++
.../bindings/soc/aspeed/uart-routing.yaml | 70 ++
arch/arm/boot/dts/aspeed-g4.dtsi | 6 +
arch/arm/boot/dts/aspeed-g5.dtsi | 6 +
arch/arm/boot/dts/aspeed-g6.dtsi | 6 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
10 files changed, 912 insertions(+), 161 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 9:25 ` Chia-Wei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Convert the bindings of Aspeed LPC from text file into YAML schema.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
2 files changed, 187 insertions(+), 157 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
deleted file mode 100644
index 936aa108eab4..000000000000
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-======================================================================
-Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
-======================================================================
-
-The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
-peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
-primary use case of the Aspeed LPC controller is as a slave on the bus
-(typically in a Baseboard Management Controller SoC), but under certain
-conditions it can also take the role of bus master.
-
-The LPC controller is represented as a multi-function device to account for the
-mix of functionality, which includes, but is not limited to:
-
-* An IPMI Block Transfer[2] Controller
-
-* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
- physical properties of some LPC pins, configuration of serial IRQs, and
- APB-to-LPC bridging amonst other functions.
-
-* An LPC Host Interface Controller: Manages functions exposed to the host such
- as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
- management and bus snoop configuration.
-
-* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
- hardware management protocols for handover between the host and baseboard
- management controller.
-
-Additionally the state of the LPC controller influences the pinmux
-configuration, therefore the host portion of the controller is exposed as a
-syscon as a means to arbitrate access.
-
-[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
-[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
-[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
-[3] https://en.wikipedia.org/wiki/Super_I/O
-
-Required properties
-===================
-
-- compatible: One of:
- "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
-
-- reg: contains the physical address and length values of the Aspeed
- LPC memory region.
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Example:
-
-lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
- reg = <0x1e789000 0x1000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1e789000 0x1000>;
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- snoop-ports = <0x80>;
- };
-};
-
-
-LPC Host Interface Controller
--------------------
-
-The LPC Host Interface Controller manages functions exposed to the host such as
-LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
-management and bus snoop configuration.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lpc-ctrl";
- "aspeed,ast2500-lpc-ctrl";
- "aspeed,ast2600-lpc-ctrl";
-
-- reg: contains offset/length values of the host interface controller
- memory regions
-
-- clocks: contains a phandle to the syscon node describing the clocks.
- There should then be one cell representing the clock to use
-
-Optional properties:
-
-- memory-region: A phandle to a reserved_memory region to be used for the LPC
- to AHB mapping
-
-- flash: A phandle to the SPI flash controller containing the flash to
- be exposed over the LPC to AHB mapping
-
-Example:
-
-lpc_ctrl: lpc-ctrl@80 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x80 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
-};
-
-LPC Host Controller
--------------------
-
-The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
-between the host and the baseboard management controller. The registers exist
-in the "host" portion of the Aspeed LPC controller, which must be the parent of
-the LPC host controller node.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lhc";
- "aspeed,ast2500-lhc";
- "aspeed,ast2600-lhc";
-
-- reg: contains offset/length values of the LHC memory regions. In the
- AST2400 and AST2500 there are two regions.
-
-Example:
-
-lhc: lhc@a0 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0xa0 0x24 0xc8 0x8>;
-};
-
-LPC reset control
------------------
-
-The UARTs present in the ASPEED SoC can have their resets tied to the reset
-state of the LPC bus. Some systems may chose to modify this configuration.
-
-Required properties:
-
- - compatible: One of:
- "aspeed,ast2600-lpc-reset";
- "aspeed,ast2500-lpc-reset";
- "aspeed,ast2400-lpc-reset";
-
- - reg: offset and length of the IP in the LHC memory region
- - #reset-controller indicates the number of reset cells expected
-
-Example:
-
-lpc_reset: reset-controller@98 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x98 0x4>;
- #reset-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
new file mode 100644
index 000000000000..54f080df5e2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2021 Aspeed Tehchnology Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed Low Pin Count (LPC) Bus Controller
+
+maintainers:
+ - Andrew Jeffery <andrew@aj.id.au>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+ peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+ primary use case of the Aspeed LPC controller is as a slave on the bus
+ (typically in a Baseboard Management Controller SoC), but under certain
+ conditions it can also take the role of bus master.
+
+ The LPC controller is represented as a multi-function device to account for the
+ mix of functionality, which includes, but is not limited to
+
+ * An IPMI Block Transfer[2] Controller
+
+ * An LPC Host Interface Controller manages functions exposed to the host such
+ as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+ management and bus snoop configuration.
+
+ * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
+ hardware management protocols for handover between the host and baseboard
+ management controller.
+
+ Additionally the state of the LPC controller influences the pinmux
+ configuration, therefore the host portion of the controller is exposed as a
+ syscon as a means to arbitrate access.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-v2
+ - aspeed,ast2500-lpc-v2
+ - aspeed,ast2600-lpc-v2
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^lpc-ctrl@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC Host Interface Controller manages functions exposed to the host such as
+ LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
+ and bus snoop configuration.
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-ctrl
+ - aspeed,ast2500-lpc-ctrl
+ - aspeed,ast2600-lpc-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ memory-region:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reserved_memory region to be used for the LPC to AHB mapping
+
+ flash:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
+
+ required:
+ - compatible
+ - clocks
+
+ "^reset-controller@[0-9a-f]+$":
+ type: object
+
+ description:
+ The UARTs present in the ASPEED SoC can have their resets tied to the reset
+ state of the LPC bus. Some systems may chose to modify this configuration
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-reset
+ - aspeed,ast2500-lpc-reset
+ - aspeed,ast2600-lpc-reset
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+
+ "^lpc-snoop@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC snoop interface allows the BMC to listen on and record the data
+ bytes written by the Host to the targeted LPC I/O pots.
+
+ properties:
+ comptabile:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-snoop
+ - aspeed,ast2500-lpc-snoop
+ - aspeed,ast2600-lpc-snoop
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ snoop-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: The LPC I/O ports to snoop
+
+ required:
+ - compatible
+ - interrupts
+ - snoop-ports
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: yulei.sh, osk
Convert the bindings of Aspeed LPC from text file into YAML schema.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
2 files changed, 187 insertions(+), 157 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
deleted file mode 100644
index 936aa108eab4..000000000000
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-======================================================================
-Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
-======================================================================
-
-The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
-peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
-primary use case of the Aspeed LPC controller is as a slave on the bus
-(typically in a Baseboard Management Controller SoC), but under certain
-conditions it can also take the role of bus master.
-
-The LPC controller is represented as a multi-function device to account for the
-mix of functionality, which includes, but is not limited to:
-
-* An IPMI Block Transfer[2] Controller
-
-* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
- physical properties of some LPC pins, configuration of serial IRQs, and
- APB-to-LPC bridging amonst other functions.
-
-* An LPC Host Interface Controller: Manages functions exposed to the host such
- as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
- management and bus snoop configuration.
-
-* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
- hardware management protocols for handover between the host and baseboard
- management controller.
-
-Additionally the state of the LPC controller influences the pinmux
-configuration, therefore the host portion of the controller is exposed as a
-syscon as a means to arbitrate access.
-
-[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
-[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
-[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
-[3] https://en.wikipedia.org/wiki/Super_I/O
-
-Required properties
-===================
-
-- compatible: One of:
- "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
-
-- reg: contains the physical address and length values of the Aspeed
- LPC memory region.
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Example:
-
-lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
- reg = <0x1e789000 0x1000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1e789000 0x1000>;
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- snoop-ports = <0x80>;
- };
-};
-
-
-LPC Host Interface Controller
--------------------
-
-The LPC Host Interface Controller manages functions exposed to the host such as
-LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
-management and bus snoop configuration.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lpc-ctrl";
- "aspeed,ast2500-lpc-ctrl";
- "aspeed,ast2600-lpc-ctrl";
-
-- reg: contains offset/length values of the host interface controller
- memory regions
-
-- clocks: contains a phandle to the syscon node describing the clocks.
- There should then be one cell representing the clock to use
-
-Optional properties:
-
-- memory-region: A phandle to a reserved_memory region to be used for the LPC
- to AHB mapping
-
-- flash: A phandle to the SPI flash controller containing the flash to
- be exposed over the LPC to AHB mapping
-
-Example:
-
-lpc_ctrl: lpc-ctrl@80 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x80 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
-};
-
-LPC Host Controller
--------------------
-
-The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
-between the host and the baseboard management controller. The registers exist
-in the "host" portion of the Aspeed LPC controller, which must be the parent of
-the LPC host controller node.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lhc";
- "aspeed,ast2500-lhc";
- "aspeed,ast2600-lhc";
-
-- reg: contains offset/length values of the LHC memory regions. In the
- AST2400 and AST2500 there are two regions.
-
-Example:
-
-lhc: lhc@a0 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0xa0 0x24 0xc8 0x8>;
-};
-
-LPC reset control
------------------
-
-The UARTs present in the ASPEED SoC can have their resets tied to the reset
-state of the LPC bus. Some systems may chose to modify this configuration.
-
-Required properties:
-
- - compatible: One of:
- "aspeed,ast2600-lpc-reset";
- "aspeed,ast2500-lpc-reset";
- "aspeed,ast2400-lpc-reset";
-
- - reg: offset and length of the IP in the LHC memory region
- - #reset-controller indicates the number of reset cells expected
-
-Example:
-
-lpc_reset: reset-controller@98 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x98 0x4>;
- #reset-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
new file mode 100644
index 000000000000..54f080df5e2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2021 Aspeed Tehchnology Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed Low Pin Count (LPC) Bus Controller
+
+maintainers:
+ - Andrew Jeffery <andrew@aj.id.au>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+ peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+ primary use case of the Aspeed LPC controller is as a slave on the bus
+ (typically in a Baseboard Management Controller SoC), but under certain
+ conditions it can also take the role of bus master.
+
+ The LPC controller is represented as a multi-function device to account for the
+ mix of functionality, which includes, but is not limited to
+
+ * An IPMI Block Transfer[2] Controller
+
+ * An LPC Host Interface Controller manages functions exposed to the host such
+ as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+ management and bus snoop configuration.
+
+ * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
+ hardware management protocols for handover between the host and baseboard
+ management controller.
+
+ Additionally the state of the LPC controller influences the pinmux
+ configuration, therefore the host portion of the controller is exposed as a
+ syscon as a means to arbitrate access.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-v2
+ - aspeed,ast2500-lpc-v2
+ - aspeed,ast2600-lpc-v2
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^lpc-ctrl@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC Host Interface Controller manages functions exposed to the host such as
+ LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
+ and bus snoop configuration.
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-ctrl
+ - aspeed,ast2500-lpc-ctrl
+ - aspeed,ast2600-lpc-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ memory-region:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reserved_memory region to be used for the LPC to AHB mapping
+
+ flash:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
+
+ required:
+ - compatible
+ - clocks
+
+ "^reset-controller@[0-9a-f]+$":
+ type: object
+
+ description:
+ The UARTs present in the ASPEED SoC can have their resets tied to the reset
+ state of the LPC bus. Some systems may chose to modify this configuration
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-reset
+ - aspeed,ast2500-lpc-reset
+ - aspeed,ast2600-lpc-reset
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+
+ "^lpc-snoop@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC snoop interface allows the BMC to listen on and record the data
+ bytes written by the Host to the targeted LPC I/O pots.
+
+ properties:
+ comptabile:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-snoop
+ - aspeed,ast2500-lpc-snoop
+ - aspeed,ast2600-lpc-snoop
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ snoop-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: The LPC I/O ports to snoop
+
+ required:
+ - compatible
+ - interrupts
+ - snoop-ports
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Convert the bindings of Aspeed LPC from text file into YAML schema.
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
2 files changed, 187 insertions(+), 157 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
deleted file mode 100644
index 936aa108eab4..000000000000
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-======================================================================
-Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
-======================================================================
-
-The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
-peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
-primary use case of the Aspeed LPC controller is as a slave on the bus
-(typically in a Baseboard Management Controller SoC), but under certain
-conditions it can also take the role of bus master.
-
-The LPC controller is represented as a multi-function device to account for the
-mix of functionality, which includes, but is not limited to:
-
-* An IPMI Block Transfer[2] Controller
-
-* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
- physical properties of some LPC pins, configuration of serial IRQs, and
- APB-to-LPC bridging amonst other functions.
-
-* An LPC Host Interface Controller: Manages functions exposed to the host such
- as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
- management and bus snoop configuration.
-
-* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
- hardware management protocols for handover between the host and baseboard
- management controller.
-
-Additionally the state of the LPC controller influences the pinmux
-configuration, therefore the host portion of the controller is exposed as a
-syscon as a means to arbitrate access.
-
-[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
-[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
-[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
-[3] https://en.wikipedia.org/wiki/Super_I/O
-
-Required properties
-===================
-
-- compatible: One of:
- "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
- "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
-
-- reg: contains the physical address and length values of the Aspeed
- LPC memory region.
-
-- #address-cells: <1>
-- #size-cells: <1>
-- ranges: Maps 0 to the physical address and length of the LPC memory
- region
-
-Example:
-
-lpc: lpc@1e789000 {
- compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
- reg = <0x1e789000 0x1000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1e789000 0x1000>;
-
- lpc_snoop: lpc-snoop@0 {
- compatible = "aspeed,ast2600-lpc-snoop";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
- snoop-ports = <0x80>;
- };
-};
-
-
-LPC Host Interface Controller
--------------------
-
-The LPC Host Interface Controller manages functions exposed to the host such as
-LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
-management and bus snoop configuration.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lpc-ctrl";
- "aspeed,ast2500-lpc-ctrl";
- "aspeed,ast2600-lpc-ctrl";
-
-- reg: contains offset/length values of the host interface controller
- memory regions
-
-- clocks: contains a phandle to the syscon node describing the clocks.
- There should then be one cell representing the clock to use
-
-Optional properties:
-
-- memory-region: A phandle to a reserved_memory region to be used for the LPC
- to AHB mapping
-
-- flash: A phandle to the SPI flash controller containing the flash to
- be exposed over the LPC to AHB mapping
-
-Example:
-
-lpc_ctrl: lpc-ctrl@80 {
- compatible = "aspeed,ast2500-lpc-ctrl";
- reg = <0x80 0x80>;
- clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
- memory-region = <&flash_memory>;
- flash = <&spi>;
-};
-
-LPC Host Controller
--------------------
-
-The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
-between the host and the baseboard management controller. The registers exist
-in the "host" portion of the Aspeed LPC controller, which must be the parent of
-the LPC host controller node.
-
-Required properties:
-
-- compatible: One of:
- "aspeed,ast2400-lhc";
- "aspeed,ast2500-lhc";
- "aspeed,ast2600-lhc";
-
-- reg: contains offset/length values of the LHC memory regions. In the
- AST2400 and AST2500 there are two regions.
-
-Example:
-
-lhc: lhc@a0 {
- compatible = "aspeed,ast2500-lhc";
- reg = <0xa0 0x24 0xc8 0x8>;
-};
-
-LPC reset control
------------------
-
-The UARTs present in the ASPEED SoC can have their resets tied to the reset
-state of the LPC bus. Some systems may chose to modify this configuration.
-
-Required properties:
-
- - compatible: One of:
- "aspeed,ast2600-lpc-reset";
- "aspeed,ast2500-lpc-reset";
- "aspeed,ast2400-lpc-reset";
-
- - reg: offset and length of the IP in the LHC memory region
- - #reset-controller indicates the number of reset cells expected
-
-Example:
-
-lpc_reset: reset-controller@98 {
- compatible = "aspeed,ast2500-lpc-reset";
- reg = <0x98 0x4>;
- #reset-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
new file mode 100644
index 000000000000..54f080df5e2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -0,0 +1,187 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2021 Aspeed Tehchnology Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed Low Pin Count (LPC) Bus Controller
+
+maintainers:
+ - Andrew Jeffery <andrew@aj.id.au>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
+ peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
+ primary use case of the Aspeed LPC controller is as a slave on the bus
+ (typically in a Baseboard Management Controller SoC), but under certain
+ conditions it can also take the role of bus master.
+
+ The LPC controller is represented as a multi-function device to account for the
+ mix of functionality, which includes, but is not limited to
+
+ * An IPMI Block Transfer[2] Controller
+
+ * An LPC Host Interface Controller manages functions exposed to the host such
+ as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
+ management and bus snoop configuration.
+
+ * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
+ hardware management protocols for handover between the host and baseboard
+ management controller.
+
+ Additionally the state of the LPC controller influences the pinmux
+ configuration, therefore the host portion of the controller is exposed as a
+ syscon as a means to arbitrate access.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-v2
+ - aspeed,ast2500-lpc-v2
+ - aspeed,ast2600-lpc-v2
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^lpc-ctrl@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC Host Interface Controller manages functions exposed to the host such as
+ LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
+ and bus snoop configuration.
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-ctrl
+ - aspeed,ast2500-lpc-ctrl
+ - aspeed,ast2600-lpc-ctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ memory-region:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A reserved_memory region to be used for the LPC to AHB mapping
+
+ flash:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
+
+ required:
+ - compatible
+ - clocks
+
+ "^reset-controller@[0-9a-f]+$":
+ type: object
+
+ description:
+ The UARTs present in the ASPEED SoC can have their resets tied to the reset
+ state of the LPC bus. Some systems may chose to modify this configuration
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-reset
+ - aspeed,ast2500-lpc-reset
+ - aspeed,ast2600-lpc-reset
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+
+ "^lpc-snoop@[0-9a-f]+$":
+ type: object
+
+ description:
+ The LPC snoop interface allows the BMC to listen on and record the data
+ bytes written by the Host to the targeted LPC I/O pots.
+
+ properties:
+ comptabile:
+ items:
+ - enum:
+ - aspeed,ast2400-lpc-snoop
+ - aspeed,ast2500-lpc-snoop
+ - aspeed,ast2600-lpc-snoop
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ snoop-ports:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: The LPC I/O ports to snoop
+
+ required:
+ - compatible
+ - interrupts
+ - snoop-ports
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ lpc_ctrl: lpc-ctrl@80 {
+ compatible = "aspeed,ast2600-lpc-ctrl";
+ reg = <0x80 0x80>;
+ clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
+ memory-region = <&flash_memory>;
+ flash = <&spi>;
+ };
+
+ lpc_reset: reset-controller@98 {
+ compatible = "aspeed,ast2600-lpc-reset";
+ reg = <0x98 0x4>;
+ #reset-cells = <1>;
+ };
+
+ lpc_snoop: lpc-snoop@90 {
+ compatible = "aspeed,ast2600-lpc-snoop";
+ reg = <0x90 0x8>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ snoop-ports = <0x80>;
+ };
+ };
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 9:25 ` Chia-Wei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add dt-bindings for Aspeed UART routing controller.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
.../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 54f080df5e2f..697331d840a0 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -142,6 +142,10 @@ patternProperties:
- interrupts
- snoop-ports
+ "^uart-routing@[0-9a-f]+$":
+ $ref: /schemas/soc/aspeed/uart-routing.yaml#
+ description: The UART routing control under LPC register space
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
new file mode 100644
index 000000000000..534b2a9340ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2018 Google LLC
+# # Copyright (c) 2021 Aspeed Technology Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Aspeed UART Routing Controller
+
+maintainers:
+ - Oskar Senft <osk@google.com>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The Aspeed UART routing control allow to dynamically route the inputs for
+ the built-in UARTS and physical serial I/O ports.
+
+ This allows, for example, to connect the output of UART to another UART.
+ This can be used to enable Host <-> BMC communication via UARTs, e.g. to
+ allow access to the Host's serial console.
+
+ This driver is for the BMC side. The sysfs files allow the BMC userspace
+ which owns the system configuration policy, to configure how UARTs and
+ physical serial I/O ports are routed.
+
+ Two types of files, uart* and io*, are presented in sysfs. The uart*
+ configures the input signal of a UART controller whereas io* configures
+ that of a physical serial port.
+
+ When read, each file shows the list of available options with currently
+ selected option marked by brackets "[]". The list of available options
+ depends on the selected file.
+
+ e.g.
+ cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
+ [io1] io2 io3 io4 uart2 uart3 uart4 io6
+
+ In this case, UART1 gets its input from IO1 (physical serial port 1).
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-uart-routing
+ - aspeed,ast2500-uart-routing
+ - aspeed,ast2600-uart-routing
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: yulei.sh, osk
Add dt-bindings for Aspeed UART routing controller.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
.../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 54f080df5e2f..697331d840a0 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -142,6 +142,10 @@ patternProperties:
- interrupts
- snoop-ports
+ "^uart-routing@[0-9a-f]+$":
+ $ref: /schemas/soc/aspeed/uart-routing.yaml#
+ description: The UART routing control under LPC register space
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
new file mode 100644
index 000000000000..534b2a9340ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2018 Google LLC
+# # Copyright (c) 2021 Aspeed Technology Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Aspeed UART Routing Controller
+
+maintainers:
+ - Oskar Senft <osk@google.com>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The Aspeed UART routing control allow to dynamically route the inputs for
+ the built-in UARTS and physical serial I/O ports.
+
+ This allows, for example, to connect the output of UART to another UART.
+ This can be used to enable Host <-> BMC communication via UARTs, e.g. to
+ allow access to the Host's serial console.
+
+ This driver is for the BMC side. The sysfs files allow the BMC userspace
+ which owns the system configuration policy, to configure how UARTs and
+ physical serial I/O ports are routed.
+
+ Two types of files, uart* and io*, are presented in sysfs. The uart*
+ configures the input signal of a UART controller whereas io* configures
+ that of a physical serial port.
+
+ When read, each file shows the list of available options with currently
+ selected option marked by brackets "[]". The list of available options
+ depends on the selected file.
+
+ e.g.
+ cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
+ [io1] io2 io3 io4 uart2 uart3 uart4 io6
+
+ In this case, UART1 gets its input from IO1 (physical serial port 1).
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-uart-routing
+ - aspeed,ast2500-uart-routing
+ - aspeed,ast2600-uart-routing
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add dt-bindings for Aspeed UART routing controller.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
---
.../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
.../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
2 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
index 54f080df5e2f..697331d840a0 100644
--- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
@@ -142,6 +142,10 @@ patternProperties:
- interrupts
- snoop-ports
+ "^uart-routing@[0-9a-f]+$":
+ $ref: /schemas/soc/aspeed/uart-routing.yaml#
+ description: The UART routing control under LPC register space
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
new file mode 100644
index 000000000000..534b2a9340ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2018 Google LLC
+# # Copyright (c) 2021 Aspeed Technology Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Aspeed UART Routing Controller
+
+maintainers:
+ - Oskar Senft <osk@google.com>
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+
+description:
+ The Aspeed UART routing control allow to dynamically route the inputs for
+ the built-in UARTS and physical serial I/O ports.
+
+ This allows, for example, to connect the output of UART to another UART.
+ This can be used to enable Host <-> BMC communication via UARTs, e.g. to
+ allow access to the Host's serial console.
+
+ This driver is for the BMC side. The sysfs files allow the BMC userspace
+ which owns the system configuration policy, to configure how UARTs and
+ physical serial I/O ports are routed.
+
+ Two types of files, uart* and io*, are presented in sysfs. The uart*
+ configures the input signal of a UART controller whereas io* configures
+ that of a physical serial port.
+
+ When read, each file shows the list of available options with currently
+ selected option marked by brackets "[]". The list of available options
+ depends on the selected file.
+
+ e.g.
+ cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
+ [io1] io2 io3 io4 uart2 uart3 uart4 io6
+
+ In this case, UART1 gets its input from IO1 (physical serial port 1).
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2400-uart-routing
+ - aspeed,ast2500-uart-routing
+ - aspeed,ast2600-uart-routing
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ lpc: lpc@1e789000 {
+ compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
+ reg = <0x1e789000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e789000 0x1000>;
+
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ };
+ };
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 3/4] soc: aspeed: Add UART routing support
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 9:25 ` Chia-Wei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
4 files changed, 633 insertions(+), 4 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
diff --git a/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
new file mode 100644
index 000000000000..65f899f1f055
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
@@ -0,0 +1,15 @@
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of the UARTx device. The current
+ selection will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
+
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of IOx pins. The current selection
+ will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
index 243ca196e6ad..f579ee0b5afa 100644
--- a/drivers/soc/aspeed/Kconfig
+++ b/drivers/soc/aspeed/Kconfig
@@ -24,6 +24,16 @@ config ASPEED_LPC_SNOOP
allows the BMC to listen on and save the data written by
the host to an arbitrary LPC I/O port.
+config ASPEED_UART_ROUTING
+ tristate "ASPEED uart routing control"
+ select REGMAP
+ select MFD_SYSCON
+ default ARCH_ASPEED
+ help
+ Provides a driver to control the UART routing paths, allowing
+ users to perform runtime configuration of the RX muxes among
+ the UART controllers and I/O pins.
+
config ASPEED_P2A_CTRL
tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
select REGMAP
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
index fcab7192e1a4..b35d74592964 100644
--- a/drivers/soc/aspeed/Makefile
+++ b/drivers/soc/aspeed/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
-obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
-obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
+obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o
+obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
+obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
diff --git a/drivers/soc/aspeed/aspeed-uart-routing.c b/drivers/soc/aspeed/aspeed-uart-routing.c
new file mode 100644
index 000000000000..ef8b24fd1851
--- /dev/null
+++ b/drivers/soc/aspeed/aspeed-uart-routing.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Google LLC
+ * Copyright (c) 2021 Aspeed Technology Inc.
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/platform_device.h>
+
+/* register offsets */
+#define HICR9 0x98
+#define HICRA 0x9c
+
+/* attributes options */
+#define UART_ROUTING_IO1 "io1"
+#define UART_ROUTING_IO2 "io2"
+#define UART_ROUTING_IO3 "io3"
+#define UART_ROUTING_IO4 "io4"
+#define UART_ROUTING_IO5 "io5"
+#define UART_ROUTING_IO6 "io6"
+#define UART_ROUTING_IO10 "io10"
+#define UART_ROUTING_UART1 "uart1"
+#define UART_ROUTING_UART2 "uart2"
+#define UART_ROUTING_UART3 "uart3"
+#define UART_ROUTING_UART4 "uart4"
+#define UART_ROUTING_UART5 "uart5"
+#define UART_ROUTING_UART6 "uart6"
+#define UART_ROUTING_UART10 "uart10"
+#define UART_ROUTING_RES "reserved"
+
+struct aspeed_uart_routing {
+ struct regmap *map;
+ struct attribute_group const *attr_grp;
+};
+
+struct aspeed_uart_routing_selector {
+ struct device_attribute dev_attr;
+ uint8_t reg;
+ uint8_t mask;
+ uint8_t shift;
+ const char *const options[];
+};
+
+#define to_routing_selector(_dev_attr) \
+ container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr)
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf);
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count);
+
+#define ROUTING_ATTR(_name) { \
+ .attr = {.name = _name, \
+ .mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \
+ .show = aspeed_uart_routing_show, \
+ .store = aspeed_uart_routing_store, \
+}
+
+/* routing selector for AST25xx */
+static struct aspeed_uart_routing_selector ast2500_io6_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO6),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO5,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART5),
+ .reg = HICRA,
+ .shift = 28,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO5),
+ .reg = HICRA,
+ .shift = 12,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct attribute *ast2500_uart_routing_attrs[] = {
+ &ast2500_io6_sel.dev_attr.attr,
+ &ast2500_uart5_sel.dev_attr.attr,
+ &ast2500_uart4_sel.dev_attr.attr,
+ &ast2500_uart3_sel.dev_attr.attr,
+ &ast2500_uart2_sel.dev_attr.attr,
+ &ast2500_uart1_sel.dev_attr.attr,
+ &ast2500_io5_sel.dev_attr.attr,
+ &ast2500_io4_sel.dev_attr.attr,
+ &ast2500_io3_sel.dev_attr.attr,
+ &ast2500_io2_sel.dev_attr.attr,
+ &ast2500_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2500_uart_routing_attr_group = {
+ .attrs = ast2500_uart_routing_attrs,
+};
+
+/* routing selector for AST26xx */
+static struct aspeed_uart_routing_selector ast2600_uart10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART10),
+ .reg = HICR9,
+ .shift = 12,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO10,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO10),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_RES,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct attribute *ast2600_uart_routing_attrs[] = {
+ &ast2600_uart10_sel.dev_attr.attr,
+ &ast2600_io10_sel.dev_attr.attr,
+ &ast2600_uart4_sel.dev_attr.attr,
+ &ast2600_uart3_sel.dev_attr.attr,
+ &ast2600_uart2_sel.dev_attr.attr,
+ &ast2600_uart1_sel.dev_attr.attr,
+ &ast2600_io4_sel.dev_attr.attr,
+ &ast2600_io3_sel.dev_attr.attr,
+ &ast2600_io2_sel.dev_attr.attr,
+ &ast2600_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2600_uart_routing_attr_group = {
+ .attrs = ast2600_uart_routing_attrs,
+};
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val, pos, len;
+
+ regmap_read(uart_routing->map, sel->reg, &val);
+ val = (val >> sel->shift) & sel->mask;
+
+ len = 0;
+ for (pos = 0; sel->options[pos] != NULL; ++pos) {
+ if (pos == val)
+ len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]);
+ else
+ len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]);
+ }
+
+ if (val >= pos)
+ len += sysfs_emit_at(buf, len, "[unknown(%d)]", val);
+
+ len += sysfs_emit_at(buf, len, "\n");
+
+ return len;
+}
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val;
+
+ val = match_string(sel->options, -1, buf);
+ if (val < 0) {
+ dev_err(dev, "invalid value \"%s\"\n", buf);
+ return -EINVAL;
+ }
+
+ regmap_update_bits(uart_routing->map, sel->reg,
+ (sel->mask << sel->shift),
+ (val & sel->mask) << sel->shift);
+
+ return count;
+}
+
+static int aspeed_uart_routing_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing;
+
+ uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL);
+ if (!uart_routing)
+ return -ENOMEM;
+
+ uart_routing->map = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(uart_routing->map)) {
+ dev_err(dev, "cannot get regmap\n");
+ return PTR_ERR(uart_routing->map);
+ }
+
+ uart_routing->attr_grp = of_device_get_match_data(dev);
+
+ rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp);
+ if (rc < 0)
+ return rc;
+
+ dev_set_drvdata(dev, uart_routing);
+
+ dev_info(dev, "module loaded\n");
+
+ return 0;
+}
+
+static int aspeed_uart_routing_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev);
+
+ sysfs_remove_group(&dev->kobj, uart_routing->attr_grp);
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_uart_routing_table[] = {
+ { .compatible = "aspeed,ast2400-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2500-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2600-uart-routing",
+ .data = &ast2600_uart_routing_attr_group },
+ { },
+};
+
+static struct platform_driver aspeed_uart_routing_driver = {
+ .driver = {
+ .name = "aspeed-uart-routing",
+ .of_match_table = aspeed_uart_routing_table,
+ },
+ .probe = aspeed_uart_routing_probe,
+ .remove = aspeed_uart_routing_remove,
+};
+
+module_platform_driver(aspeed_uart_routing_driver);
+
+MODULE_AUTHOR("Oskar Senft <osk@google.com>");
+MODULE_AUTHOR("Chia-Wei Wang <chiawei_wang@aspeedtech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Driver to configure Aspeed UART routing");
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 3/4] soc: aspeed: Add UART routing support
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: yulei.sh, osk
Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
4 files changed, 633 insertions(+), 4 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
diff --git a/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
new file mode 100644
index 000000000000..65f899f1f055
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
@@ -0,0 +1,15 @@
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of the UARTx device. The current
+ selection will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
+
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of IOx pins. The current selection
+ will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
index 243ca196e6ad..f579ee0b5afa 100644
--- a/drivers/soc/aspeed/Kconfig
+++ b/drivers/soc/aspeed/Kconfig
@@ -24,6 +24,16 @@ config ASPEED_LPC_SNOOP
allows the BMC to listen on and save the data written by
the host to an arbitrary LPC I/O port.
+config ASPEED_UART_ROUTING
+ tristate "ASPEED uart routing control"
+ select REGMAP
+ select MFD_SYSCON
+ default ARCH_ASPEED
+ help
+ Provides a driver to control the UART routing paths, allowing
+ users to perform runtime configuration of the RX muxes among
+ the UART controllers and I/O pins.
+
config ASPEED_P2A_CTRL
tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
select REGMAP
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
index fcab7192e1a4..b35d74592964 100644
--- a/drivers/soc/aspeed/Makefile
+++ b/drivers/soc/aspeed/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
-obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
-obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
+obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o
+obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
+obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
diff --git a/drivers/soc/aspeed/aspeed-uart-routing.c b/drivers/soc/aspeed/aspeed-uart-routing.c
new file mode 100644
index 000000000000..ef8b24fd1851
--- /dev/null
+++ b/drivers/soc/aspeed/aspeed-uart-routing.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Google LLC
+ * Copyright (c) 2021 Aspeed Technology Inc.
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/platform_device.h>
+
+/* register offsets */
+#define HICR9 0x98
+#define HICRA 0x9c
+
+/* attributes options */
+#define UART_ROUTING_IO1 "io1"
+#define UART_ROUTING_IO2 "io2"
+#define UART_ROUTING_IO3 "io3"
+#define UART_ROUTING_IO4 "io4"
+#define UART_ROUTING_IO5 "io5"
+#define UART_ROUTING_IO6 "io6"
+#define UART_ROUTING_IO10 "io10"
+#define UART_ROUTING_UART1 "uart1"
+#define UART_ROUTING_UART2 "uart2"
+#define UART_ROUTING_UART3 "uart3"
+#define UART_ROUTING_UART4 "uart4"
+#define UART_ROUTING_UART5 "uart5"
+#define UART_ROUTING_UART6 "uart6"
+#define UART_ROUTING_UART10 "uart10"
+#define UART_ROUTING_RES "reserved"
+
+struct aspeed_uart_routing {
+ struct regmap *map;
+ struct attribute_group const *attr_grp;
+};
+
+struct aspeed_uart_routing_selector {
+ struct device_attribute dev_attr;
+ uint8_t reg;
+ uint8_t mask;
+ uint8_t shift;
+ const char *const options[];
+};
+
+#define to_routing_selector(_dev_attr) \
+ container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr)
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf);
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count);
+
+#define ROUTING_ATTR(_name) { \
+ .attr = {.name = _name, \
+ .mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \
+ .show = aspeed_uart_routing_show, \
+ .store = aspeed_uart_routing_store, \
+}
+
+/* routing selector for AST25xx */
+static struct aspeed_uart_routing_selector ast2500_io6_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO6),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO5,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART5),
+ .reg = HICRA,
+ .shift = 28,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO5),
+ .reg = HICRA,
+ .shift = 12,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct attribute *ast2500_uart_routing_attrs[] = {
+ &ast2500_io6_sel.dev_attr.attr,
+ &ast2500_uart5_sel.dev_attr.attr,
+ &ast2500_uart4_sel.dev_attr.attr,
+ &ast2500_uart3_sel.dev_attr.attr,
+ &ast2500_uart2_sel.dev_attr.attr,
+ &ast2500_uart1_sel.dev_attr.attr,
+ &ast2500_io5_sel.dev_attr.attr,
+ &ast2500_io4_sel.dev_attr.attr,
+ &ast2500_io3_sel.dev_attr.attr,
+ &ast2500_io2_sel.dev_attr.attr,
+ &ast2500_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2500_uart_routing_attr_group = {
+ .attrs = ast2500_uart_routing_attrs,
+};
+
+/* routing selector for AST26xx */
+static struct aspeed_uart_routing_selector ast2600_uart10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART10),
+ .reg = HICR9,
+ .shift = 12,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO10,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO10),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_RES,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct attribute *ast2600_uart_routing_attrs[] = {
+ &ast2600_uart10_sel.dev_attr.attr,
+ &ast2600_io10_sel.dev_attr.attr,
+ &ast2600_uart4_sel.dev_attr.attr,
+ &ast2600_uart3_sel.dev_attr.attr,
+ &ast2600_uart2_sel.dev_attr.attr,
+ &ast2600_uart1_sel.dev_attr.attr,
+ &ast2600_io4_sel.dev_attr.attr,
+ &ast2600_io3_sel.dev_attr.attr,
+ &ast2600_io2_sel.dev_attr.attr,
+ &ast2600_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2600_uart_routing_attr_group = {
+ .attrs = ast2600_uart_routing_attrs,
+};
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val, pos, len;
+
+ regmap_read(uart_routing->map, sel->reg, &val);
+ val = (val >> sel->shift) & sel->mask;
+
+ len = 0;
+ for (pos = 0; sel->options[pos] != NULL; ++pos) {
+ if (pos == val)
+ len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]);
+ else
+ len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]);
+ }
+
+ if (val >= pos)
+ len += sysfs_emit_at(buf, len, "[unknown(%d)]", val);
+
+ len += sysfs_emit_at(buf, len, "\n");
+
+ return len;
+}
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val;
+
+ val = match_string(sel->options, -1, buf);
+ if (val < 0) {
+ dev_err(dev, "invalid value \"%s\"\n", buf);
+ return -EINVAL;
+ }
+
+ regmap_update_bits(uart_routing->map, sel->reg,
+ (sel->mask << sel->shift),
+ (val & sel->mask) << sel->shift);
+
+ return count;
+}
+
+static int aspeed_uart_routing_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing;
+
+ uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL);
+ if (!uart_routing)
+ return -ENOMEM;
+
+ uart_routing->map = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(uart_routing->map)) {
+ dev_err(dev, "cannot get regmap\n");
+ return PTR_ERR(uart_routing->map);
+ }
+
+ uart_routing->attr_grp = of_device_get_match_data(dev);
+
+ rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp);
+ if (rc < 0)
+ return rc;
+
+ dev_set_drvdata(dev, uart_routing);
+
+ dev_info(dev, "module loaded\n");
+
+ return 0;
+}
+
+static int aspeed_uart_routing_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev);
+
+ sysfs_remove_group(&dev->kobj, uart_routing->attr_grp);
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_uart_routing_table[] = {
+ { .compatible = "aspeed,ast2400-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2500-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2600-uart-routing",
+ .data = &ast2600_uart_routing_attr_group },
+ { },
+};
+
+static struct platform_driver aspeed_uart_routing_driver = {
+ .driver = {
+ .name = "aspeed-uart-routing",
+ .of_match_table = aspeed_uart_routing_table,
+ },
+ .probe = aspeed_uart_routing_probe,
+ .remove = aspeed_uart_routing_remove,
+};
+
+module_platform_driver(aspeed_uart_routing_driver);
+
+MODULE_AUTHOR("Oskar Senft <osk@google.com>");
+MODULE_AUTHOR("Chia-Wei Wang <chiawei_wang@aspeedtech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Driver to configure Aspeed UART routing");
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 3/4] soc: aspeed: Add UART routing support
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
.../testing/sysfs-driver-aspeed-uart-routing | 15 +
drivers/soc/aspeed/Kconfig | 10 +
drivers/soc/aspeed/Makefile | 9 +-
drivers/soc/aspeed/aspeed-uart-routing.c | 603 ++++++++++++++++++
4 files changed, 633 insertions(+), 4 deletions(-)
create mode 100644 Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
create mode 100644 drivers/soc/aspeed/aspeed-uart-routing.c
diff --git a/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
new file mode 100644
index 000000000000..65f899f1f055
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing
@@ -0,0 +1,15 @@
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of the UARTx device. The current
+ selection will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
+
+What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
+Date: September 2021
+Contact: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+Description: Selects the RX source of IOx pins. The current selection
+ will be marked with the '[]' brackets.
+Users: OpenBMC. Proposed changes should be mailed to
+ openbmc@lists.ozlabs.org
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
index 243ca196e6ad..f579ee0b5afa 100644
--- a/drivers/soc/aspeed/Kconfig
+++ b/drivers/soc/aspeed/Kconfig
@@ -24,6 +24,16 @@ config ASPEED_LPC_SNOOP
allows the BMC to listen on and save the data written by
the host to an arbitrary LPC I/O port.
+config ASPEED_UART_ROUTING
+ tristate "ASPEED uart routing control"
+ select REGMAP
+ select MFD_SYSCON
+ default ARCH_ASPEED
+ help
+ Provides a driver to control the UART routing paths, allowing
+ users to perform runtime configuration of the RX muxes among
+ the UART controllers and I/O pins.
+
config ASPEED_P2A_CTRL
tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
select REGMAP
diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile
index fcab7192e1a4..b35d74592964 100644
--- a/drivers/soc/aspeed/Makefile
+++ b/drivers/soc/aspeed/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
-obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
-obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
-obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
+obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o
+obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o
+obj-$(CONFIG_ASPEED_UART_ROUTING) += aspeed-uart-routing.o
+obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o
+obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o
diff --git a/drivers/soc/aspeed/aspeed-uart-routing.c b/drivers/soc/aspeed/aspeed-uart-routing.c
new file mode 100644
index 000000000000..ef8b24fd1851
--- /dev/null
+++ b/drivers/soc/aspeed/aspeed-uart-routing.c
@@ -0,0 +1,603 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2018 Google LLC
+ * Copyright (c) 2021 Aspeed Technology Inc.
+ */
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/platform_device.h>
+
+/* register offsets */
+#define HICR9 0x98
+#define HICRA 0x9c
+
+/* attributes options */
+#define UART_ROUTING_IO1 "io1"
+#define UART_ROUTING_IO2 "io2"
+#define UART_ROUTING_IO3 "io3"
+#define UART_ROUTING_IO4 "io4"
+#define UART_ROUTING_IO5 "io5"
+#define UART_ROUTING_IO6 "io6"
+#define UART_ROUTING_IO10 "io10"
+#define UART_ROUTING_UART1 "uart1"
+#define UART_ROUTING_UART2 "uart2"
+#define UART_ROUTING_UART3 "uart3"
+#define UART_ROUTING_UART4 "uart4"
+#define UART_ROUTING_UART5 "uart5"
+#define UART_ROUTING_UART6 "uart6"
+#define UART_ROUTING_UART10 "uart10"
+#define UART_ROUTING_RES "reserved"
+
+struct aspeed_uart_routing {
+ struct regmap *map;
+ struct attribute_group const *attr_grp;
+};
+
+struct aspeed_uart_routing_selector {
+ struct device_attribute dev_attr;
+ uint8_t reg;
+ uint8_t mask;
+ uint8_t shift;
+ const char *const options[];
+};
+
+#define to_routing_selector(_dev_attr) \
+ container_of(_dev_attr, struct aspeed_uart_routing_selector, dev_attr)
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf);
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count);
+
+#define ROUTING_ATTR(_name) { \
+ .attr = {.name = _name, \
+ .mode = VERIFY_OCTAL_PERMISSIONS(0644) }, \
+ .show = aspeed_uart_routing_show, \
+ .store = aspeed_uart_routing_store, \
+}
+
+/* routing selector for AST25xx */
+static struct aspeed_uart_routing_selector ast2500_io6_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO6),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO5,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART5),
+ .reg = HICRA,
+ .shift = 28,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO5,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io5_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO5),
+ .reg = HICRA,
+ .shift = 12,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2500_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART5,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO6,
+ NULL,
+ },
+};
+
+static struct attribute *ast2500_uart_routing_attrs[] = {
+ &ast2500_io6_sel.dev_attr.attr,
+ &ast2500_uart5_sel.dev_attr.attr,
+ &ast2500_uart4_sel.dev_attr.attr,
+ &ast2500_uart3_sel.dev_attr.attr,
+ &ast2500_uart2_sel.dev_attr.attr,
+ &ast2500_uart1_sel.dev_attr.attr,
+ &ast2500_io5_sel.dev_attr.attr,
+ &ast2500_io4_sel.dev_attr.attr,
+ &ast2500_io3_sel.dev_attr.attr,
+ &ast2500_io2_sel.dev_attr.attr,
+ &ast2500_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2500_uart_routing_attr_group = {
+ .attrs = ast2500_uart_routing_attrs,
+};
+
+/* routing selector for AST26xx */
+static struct aspeed_uart_routing_selector ast2600_uart10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART10),
+ .reg = HICR9,
+ .shift = 12,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_IO10,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io10_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO10),
+ .reg = HICR9,
+ .shift = 8,
+ .mask = 0xf,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_RES,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_RES,
+ UART_ROUTING_UART10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART4),
+ .reg = HICRA,
+ .shift = 25,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART3),
+ .reg = HICRA,
+ .shift = 22,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART2),
+ .reg = HICRA,
+ .shift = 19,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO1,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_uart1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_UART1),
+ .reg = HICRA,
+ .shift = 16,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io4_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO4),
+ .reg = HICRA,
+ .shift = 9,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io3_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO3),
+ .reg = HICRA,
+ .shift = 6,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_IO1,
+ UART_ROUTING_IO2,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io2_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO2),
+ .reg = HICRA,
+ .shift = 3,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_UART1,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct aspeed_uart_routing_selector ast2600_io1_sel = {
+ .dev_attr = ROUTING_ATTR(UART_ROUTING_IO1),
+ .reg = HICRA,
+ .shift = 0,
+ .mask = 0x7,
+ .options = {
+ UART_ROUTING_UART1,
+ UART_ROUTING_UART2,
+ UART_ROUTING_UART3,
+ UART_ROUTING_UART4,
+ UART_ROUTING_UART10,
+ UART_ROUTING_IO3,
+ UART_ROUTING_IO4,
+ UART_ROUTING_IO10,
+ NULL,
+ },
+};
+
+static struct attribute *ast2600_uart_routing_attrs[] = {
+ &ast2600_uart10_sel.dev_attr.attr,
+ &ast2600_io10_sel.dev_attr.attr,
+ &ast2600_uart4_sel.dev_attr.attr,
+ &ast2600_uart3_sel.dev_attr.attr,
+ &ast2600_uart2_sel.dev_attr.attr,
+ &ast2600_uart1_sel.dev_attr.attr,
+ &ast2600_io4_sel.dev_attr.attr,
+ &ast2600_io3_sel.dev_attr.attr,
+ &ast2600_io2_sel.dev_attr.attr,
+ &ast2600_io1_sel.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ast2600_uart_routing_attr_group = {
+ .attrs = ast2600_uart_routing_attrs,
+};
+
+static ssize_t aspeed_uart_routing_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val, pos, len;
+
+ regmap_read(uart_routing->map, sel->reg, &val);
+ val = (val >> sel->shift) & sel->mask;
+
+ len = 0;
+ for (pos = 0; sel->options[pos] != NULL; ++pos) {
+ if (pos == val)
+ len += sysfs_emit_at(buf, len, "[%s] ", sel->options[pos]);
+ else
+ len += sysfs_emit_at(buf, len, "%s ", sel->options[pos]);
+ }
+
+ if (val >= pos)
+ len += sysfs_emit_at(buf, len, "[unknown(%d)]", val);
+
+ len += sysfs_emit_at(buf, len, "\n");
+
+ return len;
+}
+
+static ssize_t aspeed_uart_routing_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct aspeed_uart_routing *uart_routing = dev_get_drvdata(dev);
+ struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
+ int val;
+
+ val = match_string(sel->options, -1, buf);
+ if (val < 0) {
+ dev_err(dev, "invalid value \"%s\"\n", buf);
+ return -EINVAL;
+ }
+
+ regmap_update_bits(uart_routing->map, sel->reg,
+ (sel->mask << sel->shift),
+ (val & sel->mask) << sel->shift);
+
+ return count;
+}
+
+static int aspeed_uart_routing_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing;
+
+ uart_routing = devm_kzalloc(&pdev->dev, sizeof(*uart_routing), GFP_KERNEL);
+ if (!uart_routing)
+ return -ENOMEM;
+
+ uart_routing->map = syscon_node_to_regmap(dev->parent->of_node);
+ if (IS_ERR(uart_routing->map)) {
+ dev_err(dev, "cannot get regmap\n");
+ return PTR_ERR(uart_routing->map);
+ }
+
+ uart_routing->attr_grp = of_device_get_match_data(dev);
+
+ rc = sysfs_create_group(&dev->kobj, uart_routing->attr_grp);
+ if (rc < 0)
+ return rc;
+
+ dev_set_drvdata(dev, uart_routing);
+
+ dev_info(dev, "module loaded\n");
+
+ return 0;
+}
+
+static int aspeed_uart_routing_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct aspeed_uart_routing *uart_routing = platform_get_drvdata(pdev);
+
+ sysfs_remove_group(&dev->kobj, uart_routing->attr_grp);
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_uart_routing_table[] = {
+ { .compatible = "aspeed,ast2400-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2500-uart-routing",
+ .data = &ast2500_uart_routing_attr_group },
+ { .compatible = "aspeed,ast2600-uart-routing",
+ .data = &ast2600_uart_routing_attr_group },
+ { },
+};
+
+static struct platform_driver aspeed_uart_routing_driver = {
+ .driver = {
+ .name = "aspeed-uart-routing",
+ .of_match_table = aspeed_uart_routing_table,
+ },
+ .probe = aspeed_uart_routing_probe,
+ .remove = aspeed_uart_routing_remove,
+};
+
+module_platform_driver(aspeed_uart_routing_driver);
+
+MODULE_AUTHOR("Oskar Senft <osk@google.com>");
+MODULE_AUTHOR("Chia-Wei Wang <chiawei_wang@aspeedtech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Driver to configure Aspeed UART routing");
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 4/4] ARM: dts: aspeed: Add uart routing to device tree
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 9:25 ` Chia-Wei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add LPC uart routing to the device tree for Aspeed SoCs.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c5aeb3cf3a09..b313a1cf5f73 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -383,6 +383,12 @@
interrupts = <8>;
status = "disabled";
};
+
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2400-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
};
uart2: serial@1e78d000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 73ca1ec6fc24..c7049454c7cb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -491,6 +491,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2500-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
+
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..cdc59c5d86fe 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -551,6 +551,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ status = "disabled";
+ };
+
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 4/4] ARM: dts: aspeed: Add uart routing to device tree
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: yulei.sh, osk
Add LPC uart routing to the device tree for Aspeed SoCs.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c5aeb3cf3a09..b313a1cf5f73 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -383,6 +383,12 @@
interrupts = <8>;
status = "disabled";
};
+
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2400-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
};
uart2: serial@1e78d000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 73ca1ec6fc24..c7049454c7cb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -491,6 +491,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2500-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
+
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..cdc59c5d86fe 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -551,6 +551,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ status = "disabled";
+ };
+
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
--
2.17.1
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 4/4] ARM: dts: aspeed: Add uart routing to device tree
@ 2021-09-16 9:25 ` Chia-Wei Wang
0 siblings, 0 replies; 30+ messages in thread
From: Chia-Wei Wang @ 2021-09-16 9:25 UTC (permalink / raw)
To: robh+dt, joel, andrew, linux-arm-kernel, linux-aspeed,
linux-kernel, devicetree, openbmc
Cc: osk, yulei.sh
Add LPC uart routing to the device tree for Aspeed SoCs.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index c5aeb3cf3a09..b313a1cf5f73 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -383,6 +383,12 @@
interrupts = <8>;
status = "disabled";
};
+
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2400-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
};
uart2: serial@1e78d000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 73ca1ec6fc24..c7049454c7cb 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -491,6 +491,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@9c {
+ compatible = "aspeed,ast2500-uart-routing";
+ reg = <0x9c 0x4>;
+ status = "disabled";
+ };
+
lhc: lhc@a0 {
compatible = "aspeed,ast2500-lhc";
reg = <0xa0 0x24 0xc8 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..cdc59c5d86fe 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -551,6 +551,12 @@
#reset-cells = <1>;
};
+ uart_routing: uart-routing@98 {
+ compatible = "aspeed,ast2600-uart-routing";
+ reg = <0x98 0x8>;
+ status = "disabled";
+ };
+
ibt: ibt@140 {
compatible = "aspeed,ast2600-ibt-bmc";
reg = <0x140 0x18>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 12:21 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 12:21 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: linux-arm-kernel, andrew, openbmc, linux-kernel, robh+dt,
linux-aspeed, yulei.sh, joel, osk, devicetree
On Thu, 16 Sep 2021 17:25:12 +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: /example-0/lpc@1e789000/lpc-snoop@90: failed to match any schema with compatible: ['aspeed,ast2600-lpc-snoop']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1528736
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 12:21 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 12:21 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: devicetree, linux-aspeed, andrew, openbmc, yulei.sh,
linux-kernel, robh+dt, linux-arm-kernel, osk
On Thu, 16 Sep 2021 17:25:12 +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: /example-0/lpc@1e789000/lpc-snoop@90: failed to match any schema with compatible: ['aspeed,ast2600-lpc-snoop']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1528736
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 12:21 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 12:21 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: linux-arm-kernel, andrew, openbmc, linux-kernel, robh+dt,
linux-aspeed, yulei.sh, joel, osk, devicetree
On Thu, 16 Sep 2021 17:25:12 +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mfd/aspeed-lpc.example.dt.yaml:0:0: /example-0/lpc@1e789000/lpc-snoop@90: failed to match any schema with compatible: ['aspeed,ast2600-lpc-snoop']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1528736
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 14:31 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 14:31 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> deleted file mode 100644
> index 936aa108eab4..000000000000
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -======================================================================
> -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
> -======================================================================
> -
> -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> -primary use case of the Aspeed LPC controller is as a slave on the bus
> -(typically in a Baseboard Management Controller SoC), but under certain
> -conditions it can also take the role of bus master.
> -
> -The LPC controller is represented as a multi-function device to account for the
> -mix of functionality, which includes, but is not limited to:
> -
> -* An IPMI Block Transfer[2] Controller
> -
> -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
> - physical properties of some LPC pins, configuration of serial IRQs, and
> - APB-to-LPC bridging amonst other functions.
> -
> -* An LPC Host Interface Controller: Manages functions exposed to the host such
> - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> - management and bus snoop configuration.
> -
> -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
> - hardware management protocols for handover between the host and baseboard
> - management controller.
> -
> -Additionally the state of the LPC controller influences the pinmux
> -configuration, therefore the host portion of the controller is exposed as a
> -syscon as a means to arbitrate access.
> -
> -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
> -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> -[3] https://en.wikipedia.org/wiki/Super_I/O
> -
> -Required properties
> -===================
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> -
> -- reg: contains the physical address and length values of the Aspeed
> - LPC memory region.
> -
> -- #address-cells: <1>
> -- #size-cells: <1>
> -- ranges: Maps 0 to the physical address and length of the LPC memory
> - region
> -
> -Example:
> -
> -lpc: lpc@1e789000 {
> - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> - reg = <0x1e789000 0x1000>;
> -
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x1e789000 0x1000>;
> -
> - lpc_snoop: lpc-snoop@0 {
> - compatible = "aspeed,ast2600-lpc-snoop";
> - reg = <0x0 0x80>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - snoop-ports = <0x80>;
> - };
> -};
> -
> -
> -LPC Host Interface Controller
> --------------------
> -
> -The LPC Host Interface Controller manages functions exposed to the host such as
> -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> -management and bus snoop configuration.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-ctrl";
> - "aspeed,ast2500-lpc-ctrl";
> - "aspeed,ast2600-lpc-ctrl";
> -
> -- reg: contains offset/length values of the host interface controller
> - memory regions
> -
> -- clocks: contains a phandle to the syscon node describing the clocks.
> - There should then be one cell representing the clock to use
> -
> -Optional properties:
> -
> -- memory-region: A phandle to a reserved_memory region to be used for the LPC
> - to AHB mapping
> -
> -- flash: A phandle to the SPI flash controller containing the flash to
> - be exposed over the LPC to AHB mapping
> -
> -Example:
> -
> -lpc_ctrl: lpc-ctrl@80 {
> - compatible = "aspeed,ast2500-lpc-ctrl";
> - reg = <0x80 0x80>;
> - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> - memory-region = <&flash_memory>;
> - flash = <&spi>;
> -};
> -
> -LPC Host Controller
> --------------------
> -
> -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> -between the host and the baseboard management controller. The registers exist
> -in the "host" portion of the Aspeed LPC controller, which must be the parent of
> -the LPC host controller node.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lhc";
> - "aspeed,ast2500-lhc";
> - "aspeed,ast2600-lhc";
> -
> -- reg: contains offset/length values of the LHC memory regions. In the
> - AST2400 and AST2500 there are two regions.
> -
> -Example:
> -
> -lhc: lhc@a0 {
> - compatible = "aspeed,ast2500-lhc";
> - reg = <0xa0 0x24 0xc8 0x8>;
> -};
> -
> -LPC reset control
> ------------------
> -
> -The UARTs present in the ASPEED SoC can have their resets tied to the reset
> -state of the LPC bus. Some systems may chose to modify this configuration.
> -
> -Required properties:
> -
> - - compatible: One of:
> - "aspeed,ast2600-lpc-reset";
> - "aspeed,ast2500-lpc-reset";
> - "aspeed,ast2400-lpc-reset";
> -
> - - reg: offset and length of the IP in the LHC memory region
> - - #reset-controller indicates the number of reset cells expected
> -
> -Example:
> -
> -lpc_reset: reset-controller@98 {
> - compatible = "aspeed,ast2500-lpc-reset";
> - reg = <0x98 0x4>;
> - #reset-cells = <1>;
> -};
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> new file mode 100644
> index 000000000000..54f080df5e2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -0,0 +1,187 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2021 Aspeed Tehchnology Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed Low Pin Count (LPC) Bus Controller
> +
> +maintainers:
> + - Andrew Jeffery <andrew@aj.id.au>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> + primary use case of the Aspeed LPC controller is as a slave on the bus
> + (typically in a Baseboard Management Controller SoC), but under certain
> + conditions it can also take the role of bus master.
> +
> + The LPC controller is represented as a multi-function device to account for the
> + mix of functionality, which includes, but is not limited to
> +
> + * An IPMI Block Transfer[2] Controller
> +
> + * An LPC Host Interface Controller manages functions exposed to the host such
> + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> + management and bus snoop configuration.
> +
> + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
> + hardware management protocols for handover between the host and baseboard
> + management controller.
> +
> + Additionally the state of the LPC controller influences the pinmux
> + configuration, therefore the host portion of the controller is exposed as a
> + syscon as a means to arbitrate access.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-v2
> + - aspeed,ast2500-lpc-v2
> + - aspeed,ast2600-lpc-v2
> + - const: simple-mfd
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^lpc-ctrl@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC Host Interface Controller manages functions exposed to the host such as
> + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
> + and bus snoop configuration.
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-ctrl
> + - aspeed,ast2500-lpc-ctrl
> + - aspeed,ast2600-lpc-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + memory-region:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A reserved_memory region to be used for the LPC to AHB mapping
> +
> + flash:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
> +
> + required:
> + - compatible
> + - clocks
> +
> + "^reset-controller@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The UARTs present in the ASPEED SoC can have their resets tied to the reset
> + state of the LPC bus. Some systems may chose to modify this configuration
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-reset
> + - aspeed,ast2500-lpc-reset
> + - aspeed,ast2600-lpc-reset
> +
> + reg:
> + maxItems: 1
> +
> + required:
> + - compatible
> +
> + "^lpc-snoop@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC snoop interface allows the BMC to listen on and record the data
> + bytes written by the Host to the targeted LPC I/O pots.
> +
> + properties:
> + comptabile:
I guess I have to point out *every* instance of your typo?
Run 'make dt_binding_check' and find these problems before you send this
out.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 14:31 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 14:31 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: devicetree, linux-aspeed, andrew, openbmc, yulei.sh,
linux-kernel, linux-arm-kernel, osk
On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> deleted file mode 100644
> index 936aa108eab4..000000000000
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -======================================================================
> -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
> -======================================================================
> -
> -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> -primary use case of the Aspeed LPC controller is as a slave on the bus
> -(typically in a Baseboard Management Controller SoC), but under certain
> -conditions it can also take the role of bus master.
> -
> -The LPC controller is represented as a multi-function device to account for the
> -mix of functionality, which includes, but is not limited to:
> -
> -* An IPMI Block Transfer[2] Controller
> -
> -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
> - physical properties of some LPC pins, configuration of serial IRQs, and
> - APB-to-LPC bridging amonst other functions.
> -
> -* An LPC Host Interface Controller: Manages functions exposed to the host such
> - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> - management and bus snoop configuration.
> -
> -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
> - hardware management protocols for handover between the host and baseboard
> - management controller.
> -
> -Additionally the state of the LPC controller influences the pinmux
> -configuration, therefore the host portion of the controller is exposed as a
> -syscon as a means to arbitrate access.
> -
> -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
> -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> -[3] https://en.wikipedia.org/wiki/Super_I/O
> -
> -Required properties
> -===================
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> -
> -- reg: contains the physical address and length values of the Aspeed
> - LPC memory region.
> -
> -- #address-cells: <1>
> -- #size-cells: <1>
> -- ranges: Maps 0 to the physical address and length of the LPC memory
> - region
> -
> -Example:
> -
> -lpc: lpc@1e789000 {
> - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> - reg = <0x1e789000 0x1000>;
> -
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x1e789000 0x1000>;
> -
> - lpc_snoop: lpc-snoop@0 {
> - compatible = "aspeed,ast2600-lpc-snoop";
> - reg = <0x0 0x80>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - snoop-ports = <0x80>;
> - };
> -};
> -
> -
> -LPC Host Interface Controller
> --------------------
> -
> -The LPC Host Interface Controller manages functions exposed to the host such as
> -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> -management and bus snoop configuration.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-ctrl";
> - "aspeed,ast2500-lpc-ctrl";
> - "aspeed,ast2600-lpc-ctrl";
> -
> -- reg: contains offset/length values of the host interface controller
> - memory regions
> -
> -- clocks: contains a phandle to the syscon node describing the clocks.
> - There should then be one cell representing the clock to use
> -
> -Optional properties:
> -
> -- memory-region: A phandle to a reserved_memory region to be used for the LPC
> - to AHB mapping
> -
> -- flash: A phandle to the SPI flash controller containing the flash to
> - be exposed over the LPC to AHB mapping
> -
> -Example:
> -
> -lpc_ctrl: lpc-ctrl@80 {
> - compatible = "aspeed,ast2500-lpc-ctrl";
> - reg = <0x80 0x80>;
> - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> - memory-region = <&flash_memory>;
> - flash = <&spi>;
> -};
> -
> -LPC Host Controller
> --------------------
> -
> -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> -between the host and the baseboard management controller. The registers exist
> -in the "host" portion of the Aspeed LPC controller, which must be the parent of
> -the LPC host controller node.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lhc";
> - "aspeed,ast2500-lhc";
> - "aspeed,ast2600-lhc";
> -
> -- reg: contains offset/length values of the LHC memory regions. In the
> - AST2400 and AST2500 there are two regions.
> -
> -Example:
> -
> -lhc: lhc@a0 {
> - compatible = "aspeed,ast2500-lhc";
> - reg = <0xa0 0x24 0xc8 0x8>;
> -};
> -
> -LPC reset control
> ------------------
> -
> -The UARTs present in the ASPEED SoC can have their resets tied to the reset
> -state of the LPC bus. Some systems may chose to modify this configuration.
> -
> -Required properties:
> -
> - - compatible: One of:
> - "aspeed,ast2600-lpc-reset";
> - "aspeed,ast2500-lpc-reset";
> - "aspeed,ast2400-lpc-reset";
> -
> - - reg: offset and length of the IP in the LHC memory region
> - - #reset-controller indicates the number of reset cells expected
> -
> -Example:
> -
> -lpc_reset: reset-controller@98 {
> - compatible = "aspeed,ast2500-lpc-reset";
> - reg = <0x98 0x4>;
> - #reset-cells = <1>;
> -};
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> new file mode 100644
> index 000000000000..54f080df5e2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -0,0 +1,187 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2021 Aspeed Tehchnology Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed Low Pin Count (LPC) Bus Controller
> +
> +maintainers:
> + - Andrew Jeffery <andrew@aj.id.au>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> + primary use case of the Aspeed LPC controller is as a slave on the bus
> + (typically in a Baseboard Management Controller SoC), but under certain
> + conditions it can also take the role of bus master.
> +
> + The LPC controller is represented as a multi-function device to account for the
> + mix of functionality, which includes, but is not limited to
> +
> + * An IPMI Block Transfer[2] Controller
> +
> + * An LPC Host Interface Controller manages functions exposed to the host such
> + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> + management and bus snoop configuration.
> +
> + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
> + hardware management protocols for handover between the host and baseboard
> + management controller.
> +
> + Additionally the state of the LPC controller influences the pinmux
> + configuration, therefore the host portion of the controller is exposed as a
> + syscon as a means to arbitrate access.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-v2
> + - aspeed,ast2500-lpc-v2
> + - aspeed,ast2600-lpc-v2
> + - const: simple-mfd
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^lpc-ctrl@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC Host Interface Controller manages functions exposed to the host such as
> + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
> + and bus snoop configuration.
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-ctrl
> + - aspeed,ast2500-lpc-ctrl
> + - aspeed,ast2600-lpc-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + memory-region:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A reserved_memory region to be used for the LPC to AHB mapping
> +
> + flash:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
> +
> + required:
> + - compatible
> + - clocks
> +
> + "^reset-controller@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The UARTs present in the ASPEED SoC can have their resets tied to the reset
> + state of the LPC bus. Some systems may chose to modify this configuration
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-reset
> + - aspeed,ast2500-lpc-reset
> + - aspeed,ast2600-lpc-reset
> +
> + reg:
> + maxItems: 1
> +
> + required:
> + - compatible
> +
> + "^lpc-snoop@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC snoop interface allows the BMC to listen on and record the data
> + bytes written by the Host to the targeted LPC I/O pots.
> +
> + properties:
> + comptabile:
I guess I have to point out *every* instance of your typo?
Run 'make dt_binding_check' and find these problems before you send this
out.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-16 14:31 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 14:31 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> Convert the bindings of Aspeed LPC from text file into YAML schema.
>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187 ++++++++++++++++++
> 2 files changed, 187 insertions(+), 157 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> deleted file mode 100644
> index 936aa108eab4..000000000000
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ /dev/null
> @@ -1,157 +0,0 @@
> -======================================================================
> -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
> -======================================================================
> -
> -The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> -peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> -primary use case of the Aspeed LPC controller is as a slave on the bus
> -(typically in a Baseboard Management Controller SoC), but under certain
> -conditions it can also take the role of bus master.
> -
> -The LPC controller is represented as a multi-function device to account for the
> -mix of functionality, which includes, but is not limited to:
> -
> -* An IPMI Block Transfer[2] Controller
> -
> -* An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
> - physical properties of some LPC pins, configuration of serial IRQs, and
> - APB-to-LPC bridging amonst other functions.
> -
> -* An LPC Host Interface Controller: Manages functions exposed to the host such
> - as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> - management and bus snoop configuration.
> -
> -* A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
> - hardware management protocols for handover between the host and baseboard
> - management controller.
> -
> -Additionally the state of the LPC controller influences the pinmux
> -configuration, therefore the host portion of the controller is exposed as a
> -syscon as a means to arbitrate access.
> -
> -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> -[1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
> -[2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> -[3] https://en.wikipedia.org/wiki/Super_I/O
> -
> -Required properties
> -===================
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> -
> -- reg: contains the physical address and length values of the Aspeed
> - LPC memory region.
> -
> -- #address-cells: <1>
> -- #size-cells: <1>
> -- ranges: Maps 0 to the physical address and length of the LPC memory
> - region
> -
> -Example:
> -
> -lpc: lpc@1e789000 {
> - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> - reg = <0x1e789000 0x1000>;
> -
> - #address-cells = <1>;
> - #size-cells = <1>;
> - ranges = <0x0 0x1e789000 0x1000>;
> -
> - lpc_snoop: lpc-snoop@0 {
> - compatible = "aspeed,ast2600-lpc-snoop";
> - reg = <0x0 0x80>;
> - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> - snoop-ports = <0x80>;
> - };
> -};
> -
> -
> -LPC Host Interface Controller
> --------------------
> -
> -The LPC Host Interface Controller manages functions exposed to the host such as
> -LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> -management and bus snoop configuration.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lpc-ctrl";
> - "aspeed,ast2500-lpc-ctrl";
> - "aspeed,ast2600-lpc-ctrl";
> -
> -- reg: contains offset/length values of the host interface controller
> - memory regions
> -
> -- clocks: contains a phandle to the syscon node describing the clocks.
> - There should then be one cell representing the clock to use
> -
> -Optional properties:
> -
> -- memory-region: A phandle to a reserved_memory region to be used for the LPC
> - to AHB mapping
> -
> -- flash: A phandle to the SPI flash controller containing the flash to
> - be exposed over the LPC to AHB mapping
> -
> -Example:
> -
> -lpc_ctrl: lpc-ctrl@80 {
> - compatible = "aspeed,ast2500-lpc-ctrl";
> - reg = <0x80 0x80>;
> - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> - memory-region = <&flash_memory>;
> - flash = <&spi>;
> -};
> -
> -LPC Host Controller
> --------------------
> -
> -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> -between the host and the baseboard management controller. The registers exist
> -in the "host" portion of the Aspeed LPC controller, which must be the parent of
> -the LPC host controller node.
> -
> -Required properties:
> -
> -- compatible: One of:
> - "aspeed,ast2400-lhc";
> - "aspeed,ast2500-lhc";
> - "aspeed,ast2600-lhc";
> -
> -- reg: contains offset/length values of the LHC memory regions. In the
> - AST2400 and AST2500 there are two regions.
> -
> -Example:
> -
> -lhc: lhc@a0 {
> - compatible = "aspeed,ast2500-lhc";
> - reg = <0xa0 0x24 0xc8 0x8>;
> -};
> -
> -LPC reset control
> ------------------
> -
> -The UARTs present in the ASPEED SoC can have their resets tied to the reset
> -state of the LPC bus. Some systems may chose to modify this configuration.
> -
> -Required properties:
> -
> - - compatible: One of:
> - "aspeed,ast2600-lpc-reset";
> - "aspeed,ast2500-lpc-reset";
> - "aspeed,ast2400-lpc-reset";
> -
> - - reg: offset and length of the IP in the LHC memory region
> - - #reset-controller indicates the number of reset cells expected
> -
> -Example:
> -
> -lpc_reset: reset-controller@98 {
> - compatible = "aspeed,ast2500-lpc-reset";
> - reg = <0x98 0x4>;
> - #reset-cells = <1>;
> -};
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> new file mode 100644
> index 000000000000..54f080df5e2f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -0,0 +1,187 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2021 Aspeed Tehchnology Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Aspeed Low Pin Count (LPC) Bus Controller
> +
> +maintainers:
> + - Andrew Jeffery <andrew@aj.id.au>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
> + peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
> + primary use case of the Aspeed LPC controller is as a slave on the bus
> + (typically in a Baseboard Management Controller SoC), but under certain
> + conditions it can also take the role of bus master.
> +
> + The LPC controller is represented as a multi-function device to account for the
> + mix of functionality, which includes, but is not limited to
> +
> + * An IPMI Block Transfer[2] Controller
> +
> + * An LPC Host Interface Controller manages functions exposed to the host such
> + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
> + management and bus snoop configuration.
> +
> + * A set of SuperIO[3] scratch registers enableing implementation of e.g. custom
> + hardware management protocols for handover between the host and baseboard
> + management controller.
> +
> + Additionally the state of the LPC controller influences the pinmux
> + configuration, therefore the host portion of the controller is exposed as a
> + syscon as a means to arbitrate access.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-v2
> + - aspeed,ast2500-lpc-v2
> + - aspeed,ast2600-lpc-v2
> + - const: simple-mfd
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + "#address-cells":
> + const: 1
> +
> + "#size-cells":
> + const: 1
> +
> + ranges: true
> +
> +patternProperties:
> + "^lpc-ctrl@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC Host Interface Controller manages functions exposed to the host such as
> + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART management
> + and bus snoop configuration.
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-ctrl
> + - aspeed,ast2500-lpc-ctrl
> + - aspeed,ast2600-lpc-ctrl
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + memory-region:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A reserved_memory region to be used for the LPC to AHB mapping
> +
> + flash:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The SPI flash controller containing the flash to be exposed over the LPC to AHB mapping
> +
> + required:
> + - compatible
> + - clocks
> +
> + "^reset-controller@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The UARTs present in the ASPEED SoC can have their resets tied to the reset
> + state of the LPC bus. Some systems may chose to modify this configuration
> +
> + properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-lpc-reset
> + - aspeed,ast2500-lpc-reset
> + - aspeed,ast2600-lpc-reset
> +
> + reg:
> + maxItems: 1
> +
> + required:
> + - compatible
> +
> + "^lpc-snoop@[0-9a-f]+$":
> + type: object
> +
> + description:
> + The LPC snoop interface allows the BMC to listen on and record the data
> + bytes written by the Host to the targeted LPC I/O pots.
> +
> + properties:
> + comptabile:
I guess I have to point out *every* instance of your typo?
Run 'make dt_binding_check' and find these problems before you send this
out.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
2021-09-16 9:25 ` Chia-Wei Wang
(?)
@ 2021-09-16 20:18 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 20:18 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> Add dt-bindings for Aspeed UART routing controller.
>
> Signed-off-by: Oskar Senft <osk@google.com>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> .../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
> 2 files changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> index 54f080df5e2f..697331d840a0 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -142,6 +142,10 @@ patternProperties:
> - interrupts
> - snoop-ports
>
> + "^uart-routing@[0-9a-f]+$":
> + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> + description: The UART routing control under LPC register space
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> new file mode 100644
> index 000000000000..534b2a9340ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2018 Google LLC
> +# # Copyright (c) 2021 Aspeed Technology Inc.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Aspeed UART Routing Controller
> +
> +maintainers:
> + - Oskar Senft <osk@google.com>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The Aspeed UART routing control allow to dynamically route the inputs for
> + the built-in UARTS and physical serial I/O ports.
> +
> + This allows, for example, to connect the output of UART to another UART.
> + This can be used to enable Host <-> BMC communication via UARTs, e.g. to
> + allow access to the Host's serial console.
> +
> + This driver is for the BMC side. The sysfs files allow the BMC userspace
> + which owns the system configuration policy, to configure how UARTs and
> + physical serial I/O ports are routed.
> +
> + Two types of files, uart* and io*, are presented in sysfs. The uart*
> + configures the input signal of a UART controller whereas io* configures
> + that of a physical serial port.
> +
> + When read, each file shows the list of available options with currently
> + selected option marked by brackets "[]". The list of available options
> + depends on the selected file.
> +
> + e.g.
> + cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> +
> + In this case, UART1 gets its input from IO1 (physical serial port 1).
This is about documenting the hardware, not an OS driver.
sysfs files have their own documentation.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-uart-routing
> + - aspeed,ast2500-uart-routing
> + - aspeed,ast2600-uart-routing
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + lpc: lpc@1e789000 {
> + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
> + reg = <0x1e789000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x1e789000 0x1000>;
> +
> + uart_routing: uart-routing@98 {
> + compatible = "aspeed,ast2600-uart-routing";
> + reg = <0x98 0x8>;
> + };
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-16 20:18 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 20:18 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: devicetree, linux-aspeed, andrew, openbmc, yulei.sh,
linux-kernel, linux-arm-kernel, osk
On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> Add dt-bindings for Aspeed UART routing controller.
>
> Signed-off-by: Oskar Senft <osk@google.com>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> .../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
> 2 files changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> index 54f080df5e2f..697331d840a0 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -142,6 +142,10 @@ patternProperties:
> - interrupts
> - snoop-ports
>
> + "^uart-routing@[0-9a-f]+$":
> + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> + description: The UART routing control under LPC register space
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> new file mode 100644
> index 000000000000..534b2a9340ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2018 Google LLC
> +# # Copyright (c) 2021 Aspeed Technology Inc.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Aspeed UART Routing Controller
> +
> +maintainers:
> + - Oskar Senft <osk@google.com>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The Aspeed UART routing control allow to dynamically route the inputs for
> + the built-in UARTS and physical serial I/O ports.
> +
> + This allows, for example, to connect the output of UART to another UART.
> + This can be used to enable Host <-> BMC communication via UARTs, e.g. to
> + allow access to the Host's serial console.
> +
> + This driver is for the BMC side. The sysfs files allow the BMC userspace
> + which owns the system configuration policy, to configure how UARTs and
> + physical serial I/O ports are routed.
> +
> + Two types of files, uart* and io*, are presented in sysfs. The uart*
> + configures the input signal of a UART controller whereas io* configures
> + that of a physical serial port.
> +
> + When read, each file shows the list of available options with currently
> + selected option marked by brackets "[]". The list of available options
> + depends on the selected file.
> +
> + e.g.
> + cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> +
> + In this case, UART1 gets its input from IO1 (physical serial port 1).
This is about documenting the hardware, not an OS driver.
sysfs files have their own documentation.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-uart-routing
> + - aspeed,ast2500-uart-routing
> + - aspeed,ast2600-uart-routing
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + lpc: lpc@1e789000 {
> + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
> + reg = <0x1e789000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x1e789000 0x1000>;
> +
> + uart_routing: uart-routing@98 {
> + compatible = "aspeed,ast2600-uart-routing";
> + reg = <0x98 0x8>;
> + };
> + };
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-16 20:18 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2021-09-16 20:18 UTC (permalink / raw)
To: Chia-Wei Wang
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> Add dt-bindings for Aspeed UART routing controller.
>
> Signed-off-by: Oskar Senft <osk@google.com>
> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> .../bindings/soc/aspeed/uart-routing.yaml | 70 +++++++++++++++++++
> 2 files changed, 74 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> index 54f080df5e2f..697331d840a0 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> @@ -142,6 +142,10 @@ patternProperties:
> - interrupts
> - snoop-ports
>
> + "^uart-routing@[0-9a-f]+$":
> + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> + description: The UART routing control under LPC register space
> +
> required:
> - compatible
> - reg
> diff --git a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> new file mode 100644
> index 000000000000..534b2a9340ce
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# # Copyright (c) 2018 Google LLC
> +# # Copyright (c) 2021 Aspeed Technology Inc.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Aspeed UART Routing Controller
> +
> +maintainers:
> + - Oskar Senft <osk@google.com>
> + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> +
> +description:
> + The Aspeed UART routing control allow to dynamically route the inputs for
> + the built-in UARTS and physical serial I/O ports.
> +
> + This allows, for example, to connect the output of UART to another UART.
> + This can be used to enable Host <-> BMC communication via UARTs, e.g. to
> + allow access to the Host's serial console.
> +
> + This driver is for the BMC side. The sysfs files allow the BMC userspace
> + which owns the system configuration policy, to configure how UARTs and
> + physical serial I/O ports are routed.
> +
> + Two types of files, uart* and io*, are presented in sysfs. The uart*
> + configures the input signal of a UART controller whereas io* configures
> + that of a physical serial port.
> +
> + When read, each file shows the list of available options with currently
> + selected option marked by brackets "[]". The list of available options
> + depends on the selected file.
> +
> + e.g.
> + cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> +
> + In this case, UART1 gets its input from IO1 (physical serial port 1).
This is about documenting the hardware, not an OS driver.
sysfs files have their own documentation.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,ast2400-uart-routing
> + - aspeed,ast2500-uart-routing
> + - aspeed,ast2600-uart-routing
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + lpc: lpc@1e789000 {
> + compatible = "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon";
> + reg = <0x1e789000 0x1000>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x1e789000 0x1000>;
> +
> + uart_routing: uart-routing@98 {
> + compatible = "aspeed,ast2600-uart-routing";
> + reg = <0x98 0x8>;
> + };
> + };
> --
> 2.17.1
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
2021-09-16 20:18 ` Rob Herring
(?)
@ 2021-09-17 0:46 ` ChiaWei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-17 0:46 UTC (permalink / raw)
To: Rob Herring
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 17, 2021 4:19 AM
>
> On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> > Add dt-bindings for Aspeed UART routing controller.
> >
> > Signed-off-by: Oskar Senft <osk@google.com>
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> > .../bindings/soc/aspeed/uart-routing.yaml | 70
> +++++++++++++++++++
> > 2 files changed, 74 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > index 54f080df5e2f..697331d840a0 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -142,6 +142,10 @@ patternProperties:
> > - interrupts
> > - snoop-ports
> >
> > + "^uart-routing@[0-9a-f]+$":
> > + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> > + description: The UART routing control under LPC register space
> > +
> > required:
> > - compatible
> > - reg
> > diff --git
> > a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > new file mode 100644
> > index 000000000000..534b2a9340ce
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2018 Google LLC # # Copyright (c) 2021 Aspeed
> > +Technology Inc.
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Aspeed UART Routing Controller
> > +
> > +maintainers:
> > + - Oskar Senft <osk@google.com>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The Aspeed UART routing control allow to dynamically route the
> > +inputs for
> > + the built-in UARTS and physical serial I/O ports.
> > +
> > + This allows, for example, to connect the output of UART to another UART.
> > + This can be used to enable Host <-> BMC communication via UARTs,
> > + e.g. to allow access to the Host's serial console.
> > +
> > + This driver is for the BMC side. The sysfs files allow the BMC
> > + userspace which owns the system configuration policy, to configure
> > + how UARTs and physical serial I/O ports are routed.
> > +
> > + Two types of files, uart* and io*, are presented in sysfs. The
> > + uart* configures the input signal of a UART controller whereas io*
> > + configures that of a physical serial port.
> > +
> > + When read, each file shows the list of available options with
> > + currently selected option marked by brackets "[]". The list of
> > + available options depends on the selected file.
> > +
> > + e.g.
> > + cat
> > + /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> > + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> > +
> > + In this case, UART1 gets its input from IO1 (physical serial port 1).
>
> This is about documenting the hardware, not an OS driver.
>
> sysfs files have their own documentation.
>
Understood. I will remove this sysfs description from bindings in the next revision.
Thanks.
Chiawei
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-17 0:46 ` ChiaWei Wang
0 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-17 0:46 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-aspeed, andrew, openbmc, yulei.sh,
linux-kernel, linux-arm-kernel, osk
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 17, 2021 4:19 AM
>
> On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> > Add dt-bindings for Aspeed UART routing controller.
> >
> > Signed-off-by: Oskar Senft <osk@google.com>
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> > .../bindings/soc/aspeed/uart-routing.yaml | 70
> +++++++++++++++++++
> > 2 files changed, 74 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > index 54f080df5e2f..697331d840a0 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -142,6 +142,10 @@ patternProperties:
> > - interrupts
> > - snoop-ports
> >
> > + "^uart-routing@[0-9a-f]+$":
> > + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> > + description: The UART routing control under LPC register space
> > +
> > required:
> > - compatible
> > - reg
> > diff --git
> > a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > new file mode 100644
> > index 000000000000..534b2a9340ce
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2018 Google LLC # # Copyright (c) 2021 Aspeed
> > +Technology Inc.
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Aspeed UART Routing Controller
> > +
> > +maintainers:
> > + - Oskar Senft <osk@google.com>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The Aspeed UART routing control allow to dynamically route the
> > +inputs for
> > + the built-in UARTS and physical serial I/O ports.
> > +
> > + This allows, for example, to connect the output of UART to another UART.
> > + This can be used to enable Host <-> BMC communication via UARTs,
> > + e.g. to allow access to the Host's serial console.
> > +
> > + This driver is for the BMC side. The sysfs files allow the BMC
> > + userspace which owns the system configuration policy, to configure
> > + how UARTs and physical serial I/O ports are routed.
> > +
> > + Two types of files, uart* and io*, are presented in sysfs. The
> > + uart* configures the input signal of a UART controller whereas io*
> > + configures that of a physical serial port.
> > +
> > + When read, each file shows the list of available options with
> > + currently selected option marked by brackets "[]". The list of
> > + available options depends on the selected file.
> > +
> > + e.g.
> > + cat
> > + /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> > + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> > +
> > + In this case, UART1 gets its input from IO1 (physical serial port 1).
>
> This is about documenting the hardware, not an OS driver.
>
> sysfs files have their own documentation.
>
Understood. I will remove this sysfs description from bindings in the next revision.
Thanks.
Chiawei
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller
@ 2021-09-17 0:46 ` ChiaWei Wang
0 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-17 0:46 UTC (permalink / raw)
To: Rob Herring
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Friday, September 17, 2021 4:19 AM
>
> On Thu, Sep 16, 2021 at 05:25:13PM +0800, Chia-Wei Wang wrote:
> > Add dt-bindings for Aspeed UART routing controller.
> >
> > Signed-off-by: Oskar Senft <osk@google.com>
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 4 ++
> > .../bindings/soc/aspeed/uart-routing.yaml | 70
> +++++++++++++++++++
> > 2 files changed, 74 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > index 54f080df5e2f..697331d840a0 100644
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -142,6 +142,10 @@ patternProperties:
> > - interrupts
> > - snoop-ports
> >
> > + "^uart-routing@[0-9a-f]+$":
> > + $ref: /schemas/soc/aspeed/uart-routing.yaml#
> > + description: The UART routing control under LPC register space
> > +
> > required:
> > - compatible
> > - reg
> > diff --git
> > a/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > new file mode 100644
> > index 000000000000..534b2a9340ce
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/aspeed/uart-routing.yaml
> > @@ -0,0 +1,70 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2018 Google LLC # # Copyright (c) 2021 Aspeed
> > +Technology Inc.
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: Aspeed UART Routing Controller
> > +
> > +maintainers:
> > + - Oskar Senft <osk@google.com>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The Aspeed UART routing control allow to dynamically route the
> > +inputs for
> > + the built-in UARTS and physical serial I/O ports.
> > +
> > + This allows, for example, to connect the output of UART to another UART.
> > + This can be used to enable Host <-> BMC communication via UARTs,
> > + e.g. to allow access to the Host's serial console.
> > +
> > + This driver is for the BMC side. The sysfs files allow the BMC
> > + userspace which owns the system configuration policy, to configure
> > + how UARTs and physical serial I/O ports are routed.
> > +
> > + Two types of files, uart* and io*, are presented in sysfs. The
> > + uart* configures the input signal of a UART controller whereas io*
> > + configures that of a physical serial port.
> > +
> > + When read, each file shows the list of available options with
> > + currently selected option marked by brackets "[]". The list of
> > + available options depends on the selected file.
> > +
> > + e.g.
> > + cat
> > + /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
> > + [io1] io2 io3 io4 uart2 uart3 uart4 io6
> > +
> > + In this case, UART1 gets its input from IO1 (physical serial port 1).
>
> This is about documenting the hardware, not an OS driver.
>
> sysfs files have their own documentation.
>
Understood. I will remove this sysfs description from bindings in the next revision.
Thanks.
Chiawei
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
2021-09-16 14:31 ` Rob Herring
(?)
@ 2021-09-22 5:54 ` ChiaWei Wang
-1 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-22 5:54 UTC (permalink / raw)
To: Rob Herring
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, September 16, 2021 10:32 PM
>
> On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> > Convert the bindings of Aspeed LPC from text file into YAML schema.
> >
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187
> ++++++++++++++++++
> > 2 files changed, 187 insertions(+), 157 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > create mode 100644
> > Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > deleted file mode 100644
> > index 936aa108eab4..000000000000
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > +++ /dev/null
> > @@ -1,157 +0,0 @@
> >
> -===============================================================
> ======
> > = -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus
> > Controller
> >
> -===============================================================
> ======
> > =
> > -
> > -The LPC bus is a means to bridge a host CPU to a number of
> > low-bandwidth -peripheral devices, replacing the use of the ISA bus in
> > the age of PCI[0]. The -primary use case of the Aspeed LPC controller
> > is as a slave on the bus -(typically in a Baseboard Management
> > Controller SoC), but under certain -conditions it can also take the role of bus
> master.
> > -
> > -The LPC controller is represented as a multi-function device to
> > account for the -mix of functionality, which includes, but is not limited to:
> > -
> > -* An IPMI Block Transfer[2] Controller
> > -
> > -* An LPC Host Controller: Manages LPC functions such as host vs slave
> > mode, the
> > - physical properties of some LPC pins, configuration of serial IRQs,
> > and
> > - APB-to-LPC bridging amonst other functions.
> > -
> > -* An LPC Host Interface Controller: Manages functions exposed to the
> > host such
> > - as LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART
> > - management and bus snoop configuration.
> > -
> > -* A set of SuperIO[3] scratch registers: Enables implementation of
> > e.g. custom
> > - hardware management protocols for handover between the host and
> > baseboard
> > - management controller.
> > -
> > -Additionally the state of the LPC controller influences the pinmux
> > -configuration, therefore the host portion of the controller is
> > exposed as a -syscon as a means to arbitrate access.
> > -
> > -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> > -[1]
> >
> https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2
> 1
> > 68.pdf?key=7c88837454702128622bee53acbda8f4
> > -[2]
> >
> https://www.intel.com/content/dam/www/public/us/en/documents/product-b
> > riefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> > -[3] https://en.wikipedia.org/wiki/Super_I/O
> > -
> > -Required properties
> > -===================
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> > -
> > -- reg: contains the physical address and length values of the Aspeed
> > - LPC memory region.
> > -
> > -- #address-cells: <1>
> > -- #size-cells: <1>
> > -- ranges: Maps 0 to the physical address and length of the LPC memory
> > - region
> > -
> > -Example:
> > -
> > -lpc: lpc@1e789000 {
> > - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> > - reg = <0x1e789000 0x1000>;
> > -
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > - ranges = <0x0 0x1e789000 0x1000>;
> > -
> > - lpc_snoop: lpc-snoop@0 {
> > - compatible = "aspeed,ast2600-lpc-snoop";
> > - reg = <0x0 0x80>;
> > - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > - snoop-ports = <0x80>;
> > - };
> > -};
> > -
> > -
> > -LPC Host Interface Controller
> > --------------------
> > -
> > -The LPC Host Interface Controller manages functions exposed to the
> > host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART -management and bus snoop configuration.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-ctrl";
> > - "aspeed,ast2500-lpc-ctrl";
> > - "aspeed,ast2600-lpc-ctrl";
> > -
> > -- reg: contains offset/length values of the host interface controller
> > - memory regions
> > -
> > -- clocks: contains a phandle to the syscon node describing the clocks.
> > - There should then be one cell representing the clock to use
> > -
> > -Optional properties:
> > -
> > -- memory-region: A phandle to a reserved_memory region to be used for
> the LPC
> > - to AHB mapping
> > -
> > -- flash: A phandle to the SPI flash controller containing the flash to
> > - be exposed over the LPC to AHB mapping
> > -
> > -Example:
> > -
> > -lpc_ctrl: lpc-ctrl@80 {
> > - compatible = "aspeed,ast2500-lpc-ctrl";
> > - reg = <0x80 0x80>;
> > - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> > - memory-region = <&flash_memory>;
> > - flash = <&spi>;
> > -};
> > -
> > -LPC Host Controller
> > --------------------
> > -
> > -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus
> > behaviour -between the host and the baseboard management controller.
> > The registers exist -in the "host" portion of the Aspeed LPC
> > controller, which must be the parent of -the LPC host controller node.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lhc";
> > - "aspeed,ast2500-lhc";
> > - "aspeed,ast2600-lhc";
> > -
> > -- reg: contains offset/length values of the LHC memory regions. In the
> > - AST2400 and AST2500 there are two regions.
> > -
> > -Example:
> > -
> > -lhc: lhc@a0 {
> > - compatible = "aspeed,ast2500-lhc";
> > - reg = <0xa0 0x24 0xc8 0x8>;
> > -};
> > -
> > -LPC reset control
> > ------------------
> > -
> > -The UARTs present in the ASPEED SoC can have their resets tied to the
> > reset -state of the LPC bus. Some systems may chose to modify this
> configuration.
> > -
> > -Required properties:
> > -
> > - - compatible: One of:
> > - "aspeed,ast2600-lpc-reset";
> > - "aspeed,ast2500-lpc-reset";
> > - "aspeed,ast2400-lpc-reset";
> > -
> > - - reg: offset and length of the IP in the LHC memory region
> > - - #reset-controller indicates the number of reset cells expected
> > -
> > -Example:
> > -
> > -lpc_reset: reset-controller@98 {
> > - compatible = "aspeed,ast2500-lpc-reset";
> > - reg = <0x98 0x4>;
> > - #reset-cells = <1>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > new file mode 100644
> > index 000000000000..54f080df5e2f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -0,0 +1,187 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2021 Aspeed Tehchnology Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Aspeed Low Pin Count (LPC) Bus Controller
> > +
> > +maintainers:
> > + - Andrew Jeffery <andrew@aj.id.au>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The LPC bus is a means to bridge a host CPU to a number of
> > +low-bandwidth
> > + peripheral devices, replacing the use of the ISA bus in the age of
> > +PCI[0]. The
> > + primary use case of the Aspeed LPC controller is as a slave on the
> > +bus
> > + (typically in a Baseboard Management Controller SoC), but under
> > +certain
> > + conditions it can also take the role of bus master.
> > +
> > + The LPC controller is represented as a multi-function device to
> > + account for the mix of functionality, which includes, but is not
> > + limited to
> > +
> > + * An IPMI Block Transfer[2] Controller
> > +
> > + * An LPC Host Interface Controller manages functions exposed to the host
> such
> > + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART
> > + management and bus snoop configuration.
> > +
> > + * A set of SuperIO[3] scratch registers enableing implementation of e.g.
> custom
> > + hardware management protocols for handover between the host and
> baseboard
> > + management controller.
> > +
> > + Additionally the state of the LPC controller influences the pinmux
> > + configuration, therefore the host portion of the controller is
> > + exposed as a syscon as a means to arbitrate access.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-v2
> > + - aspeed,ast2500-lpc-v2
> > + - aspeed,ast2600-lpc-v2
> > + - const: simple-mfd
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges: true
> > +
> > +patternProperties:
> > + "^lpc-ctrl@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC Host Interface Controller manages functions exposed to the
> host such as
> > + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART management
> > + and bus snoop configuration.
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-ctrl
> > + - aspeed,ast2500-lpc-ctrl
> > + - aspeed,ast2600-lpc-ctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + memory-region:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A reserved_memory region to be used for the LPC
> > + to AHB mapping
> > +
> > + flash:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: The SPI flash controller containing the flash to
> > + be exposed over the LPC to AHB mapping
> > +
> > + required:
> > + - compatible
> > + - clocks
> > +
> > + "^reset-controller@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The UARTs present in the ASPEED SoC can have their resets tied to
> the reset
> > + state of the LPC bus. Some systems may chose to modify this
> > + configuration
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-reset
> > + - aspeed,ast2500-lpc-reset
> > + - aspeed,ast2600-lpc-reset
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > +
> > + "^lpc-snoop@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC snoop interface allows the BMC to listen on and record the
> data
> > + bytes written by the Host to the targeted LPC I/O pots.
> > +
> > + properties:
> > + comptabile:
>
> I guess I have to point out *every* instance of your typo?
>
> Run 'make dt_binding_check' and find these problems before you send this
> out.
Sorry for making this error again.
I missed the "DT_CHECKER_FLAGS=-m" command line argument and thus the warning did not show up.
Will keep in mind next time. Thanks for your help.
Chiawei
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-22 5:54 ` ChiaWei Wang
0 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-22 5:54 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, linux-aspeed, andrew, openbmc, yulei.sh,
linux-kernel, linux-arm-kernel, osk
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, September 16, 2021 10:32 PM
>
> On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> > Convert the bindings of Aspeed LPC from text file into YAML schema.
> >
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187
> ++++++++++++++++++
> > 2 files changed, 187 insertions(+), 157 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > create mode 100644
> > Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > deleted file mode 100644
> > index 936aa108eab4..000000000000
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > +++ /dev/null
> > @@ -1,157 +0,0 @@
> >
> -===============================================================
> ======
> > = -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus
> > Controller
> >
> -===============================================================
> ======
> > =
> > -
> > -The LPC bus is a means to bridge a host CPU to a number of
> > low-bandwidth -peripheral devices, replacing the use of the ISA bus in
> > the age of PCI[0]. The -primary use case of the Aspeed LPC controller
> > is as a slave on the bus -(typically in a Baseboard Management
> > Controller SoC), but under certain -conditions it can also take the role of bus
> master.
> > -
> > -The LPC controller is represented as a multi-function device to
> > account for the -mix of functionality, which includes, but is not limited to:
> > -
> > -* An IPMI Block Transfer[2] Controller
> > -
> > -* An LPC Host Controller: Manages LPC functions such as host vs slave
> > mode, the
> > - physical properties of some LPC pins, configuration of serial IRQs,
> > and
> > - APB-to-LPC bridging amonst other functions.
> > -
> > -* An LPC Host Interface Controller: Manages functions exposed to the
> > host such
> > - as LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART
> > - management and bus snoop configuration.
> > -
> > -* A set of SuperIO[3] scratch registers: Enables implementation of
> > e.g. custom
> > - hardware management protocols for handover between the host and
> > baseboard
> > - management controller.
> > -
> > -Additionally the state of the LPC controller influences the pinmux
> > -configuration, therefore the host portion of the controller is
> > exposed as a -syscon as a means to arbitrate access.
> > -
> > -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> > -[1]
> >
> https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2
> 1
> > 68.pdf?key=7c88837454702128622bee53acbda8f4
> > -[2]
> >
> https://www.intel.com/content/dam/www/public/us/en/documents/product-b
> > riefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> > -[3] https://en.wikipedia.org/wiki/Super_I/O
> > -
> > -Required properties
> > -===================
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> > -
> > -- reg: contains the physical address and length values of the Aspeed
> > - LPC memory region.
> > -
> > -- #address-cells: <1>
> > -- #size-cells: <1>
> > -- ranges: Maps 0 to the physical address and length of the LPC memory
> > - region
> > -
> > -Example:
> > -
> > -lpc: lpc@1e789000 {
> > - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> > - reg = <0x1e789000 0x1000>;
> > -
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > - ranges = <0x0 0x1e789000 0x1000>;
> > -
> > - lpc_snoop: lpc-snoop@0 {
> > - compatible = "aspeed,ast2600-lpc-snoop";
> > - reg = <0x0 0x80>;
> > - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > - snoop-ports = <0x80>;
> > - };
> > -};
> > -
> > -
> > -LPC Host Interface Controller
> > --------------------
> > -
> > -The LPC Host Interface Controller manages functions exposed to the
> > host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART -management and bus snoop configuration.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-ctrl";
> > - "aspeed,ast2500-lpc-ctrl";
> > - "aspeed,ast2600-lpc-ctrl";
> > -
> > -- reg: contains offset/length values of the host interface controller
> > - memory regions
> > -
> > -- clocks: contains a phandle to the syscon node describing the clocks.
> > - There should then be one cell representing the clock to use
> > -
> > -Optional properties:
> > -
> > -- memory-region: A phandle to a reserved_memory region to be used for
> the LPC
> > - to AHB mapping
> > -
> > -- flash: A phandle to the SPI flash controller containing the flash to
> > - be exposed over the LPC to AHB mapping
> > -
> > -Example:
> > -
> > -lpc_ctrl: lpc-ctrl@80 {
> > - compatible = "aspeed,ast2500-lpc-ctrl";
> > - reg = <0x80 0x80>;
> > - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> > - memory-region = <&flash_memory>;
> > - flash = <&spi>;
> > -};
> > -
> > -LPC Host Controller
> > --------------------
> > -
> > -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus
> > behaviour -between the host and the baseboard management controller.
> > The registers exist -in the "host" portion of the Aspeed LPC
> > controller, which must be the parent of -the LPC host controller node.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lhc";
> > - "aspeed,ast2500-lhc";
> > - "aspeed,ast2600-lhc";
> > -
> > -- reg: contains offset/length values of the LHC memory regions. In the
> > - AST2400 and AST2500 there are two regions.
> > -
> > -Example:
> > -
> > -lhc: lhc@a0 {
> > - compatible = "aspeed,ast2500-lhc";
> > - reg = <0xa0 0x24 0xc8 0x8>;
> > -};
> > -
> > -LPC reset control
> > ------------------
> > -
> > -The UARTs present in the ASPEED SoC can have their resets tied to the
> > reset -state of the LPC bus. Some systems may chose to modify this
> configuration.
> > -
> > -Required properties:
> > -
> > - - compatible: One of:
> > - "aspeed,ast2600-lpc-reset";
> > - "aspeed,ast2500-lpc-reset";
> > - "aspeed,ast2400-lpc-reset";
> > -
> > - - reg: offset and length of the IP in the LHC memory region
> > - - #reset-controller indicates the number of reset cells expected
> > -
> > -Example:
> > -
> > -lpc_reset: reset-controller@98 {
> > - compatible = "aspeed,ast2500-lpc-reset";
> > - reg = <0x98 0x4>;
> > - #reset-cells = <1>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > new file mode 100644
> > index 000000000000..54f080df5e2f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -0,0 +1,187 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2021 Aspeed Tehchnology Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Aspeed Low Pin Count (LPC) Bus Controller
> > +
> > +maintainers:
> > + - Andrew Jeffery <andrew@aj.id.au>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The LPC bus is a means to bridge a host CPU to a number of
> > +low-bandwidth
> > + peripheral devices, replacing the use of the ISA bus in the age of
> > +PCI[0]. The
> > + primary use case of the Aspeed LPC controller is as a slave on the
> > +bus
> > + (typically in a Baseboard Management Controller SoC), but under
> > +certain
> > + conditions it can also take the role of bus master.
> > +
> > + The LPC controller is represented as a multi-function device to
> > + account for the mix of functionality, which includes, but is not
> > + limited to
> > +
> > + * An IPMI Block Transfer[2] Controller
> > +
> > + * An LPC Host Interface Controller manages functions exposed to the host
> such
> > + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART
> > + management and bus snoop configuration.
> > +
> > + * A set of SuperIO[3] scratch registers enableing implementation of e.g.
> custom
> > + hardware management protocols for handover between the host and
> baseboard
> > + management controller.
> > +
> > + Additionally the state of the LPC controller influences the pinmux
> > + configuration, therefore the host portion of the controller is
> > + exposed as a syscon as a means to arbitrate access.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-v2
> > + - aspeed,ast2500-lpc-v2
> > + - aspeed,ast2600-lpc-v2
> > + - const: simple-mfd
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges: true
> > +
> > +patternProperties:
> > + "^lpc-ctrl@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC Host Interface Controller manages functions exposed to the
> host such as
> > + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART management
> > + and bus snoop configuration.
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-ctrl
> > + - aspeed,ast2500-lpc-ctrl
> > + - aspeed,ast2600-lpc-ctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + memory-region:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A reserved_memory region to be used for the LPC
> > + to AHB mapping
> > +
> > + flash:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: The SPI flash controller containing the flash to
> > + be exposed over the LPC to AHB mapping
> > +
> > + required:
> > + - compatible
> > + - clocks
> > +
> > + "^reset-controller@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The UARTs present in the ASPEED SoC can have their resets tied to
> the reset
> > + state of the LPC bus. Some systems may chose to modify this
> > + configuration
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-reset
> > + - aspeed,ast2500-lpc-reset
> > + - aspeed,ast2600-lpc-reset
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > +
> > + "^lpc-snoop@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC snoop interface allows the BMC to listen on and record the
> data
> > + bytes written by the Host to the targeted LPC I/O pots.
> > +
> > + properties:
> > + comptabile:
>
> I guess I have to point out *every* instance of your typo?
>
> Run 'make dt_binding_check' and find these problems before you send this
> out.
Sorry for making this error again.
I missed the "DT_CHECKER_FLAGS=-m" command line argument and thus the warning did not show up.
Will keep in mind next time. Thanks for your help.
Chiawei
^ permalink raw reply [flat|nested] 30+ messages in thread
* RE: [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema
@ 2021-09-22 5:54 ` ChiaWei Wang
0 siblings, 0 replies; 30+ messages in thread
From: ChiaWei Wang @ 2021-09-22 5:54 UTC (permalink / raw)
To: Rob Herring
Cc: joel, andrew, linux-arm-kernel, linux-aspeed, linux-kernel,
devicetree, openbmc, osk, yulei.sh
Hi Rob,
> From: Rob Herring <robh@kernel.org>
> Sent: Thursday, September 16, 2021 10:32 PM
>
> On Thu, Sep 16, 2021 at 05:25:12PM +0800, Chia-Wei Wang wrote:
> > Convert the bindings of Aspeed LPC from text file into YAML schema.
> >
> > Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > ---
> > .../devicetree/bindings/mfd/aspeed-lpc.txt | 157 ---------------
> > .../devicetree/bindings/mfd/aspeed-lpc.yaml | 187
> ++++++++++++++++++
> > 2 files changed, 187 insertions(+), 157 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > create mode 100644
> > Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > deleted file mode 100644
> > index 936aa108eab4..000000000000
> > --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> > +++ /dev/null
> > @@ -1,157 +0,0 @@
> >
> -===============================================================
> ======
> > = -Device tree bindings for the Aspeed Low Pin Count (LPC) Bus
> > Controller
> >
> -===============================================================
> ======
> > =
> > -
> > -The LPC bus is a means to bridge a host CPU to a number of
> > low-bandwidth -peripheral devices, replacing the use of the ISA bus in
> > the age of PCI[0]. The -primary use case of the Aspeed LPC controller
> > is as a slave on the bus -(typically in a Baseboard Management
> > Controller SoC), but under certain -conditions it can also take the role of bus
> master.
> > -
> > -The LPC controller is represented as a multi-function device to
> > account for the -mix of functionality, which includes, but is not limited to:
> > -
> > -* An IPMI Block Transfer[2] Controller
> > -
> > -* An LPC Host Controller: Manages LPC functions such as host vs slave
> > mode, the
> > - physical properties of some LPC pins, configuration of serial IRQs,
> > and
> > - APB-to-LPC bridging amonst other functions.
> > -
> > -* An LPC Host Interface Controller: Manages functions exposed to the
> > host such
> > - as LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART
> > - management and bus snoop configuration.
> > -
> > -* A set of SuperIO[3] scratch registers: Enables implementation of
> > e.g. custom
> > - hardware management protocols for handover between the host and
> > baseboard
> > - management controller.
> > -
> > -Additionally the state of the LPC controller influences the pinmux
> > -configuration, therefore the host portion of the controller is
> > exposed as a -syscon as a means to arbitrate access.
> > -
> > -[0] http://www.intel.com/design/chipsets/industry/25128901.pdf
> > -[1]
> >
> https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2
> 1
> > 68.pdf?key=7c88837454702128622bee53acbda8f4
> > -[2]
> >
> https://www.intel.com/content/dam/www/public/us/en/documents/product-b
> > riefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
> > -[3] https://en.wikipedia.org/wiki/Super_I/O
> > -
> > -Required properties
> > -===================
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
> > - "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
> > -
> > -- reg: contains the physical address and length values of the Aspeed
> > - LPC memory region.
> > -
> > -- #address-cells: <1>
> > -- #size-cells: <1>
> > -- ranges: Maps 0 to the physical address and length of the LPC memory
> > - region
> > -
> > -Example:
> > -
> > -lpc: lpc@1e789000 {
> > - compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
> > - reg = <0x1e789000 0x1000>;
> > -
> > - #address-cells = <1>;
> > - #size-cells = <1>;
> > - ranges = <0x0 0x1e789000 0x1000>;
> > -
> > - lpc_snoop: lpc-snoop@0 {
> > - compatible = "aspeed,ast2600-lpc-snoop";
> > - reg = <0x0 0x80>;
> > - interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > - snoop-ports = <0x80>;
> > - };
> > -};
> > -
> > -
> > -LPC Host Interface Controller
> > --------------------
> > -
> > -The LPC Host Interface Controller manages functions exposed to the
> > host such as -LPC firmware hub cycles, configuration of the LPC-to-AHB
> > mapping, UART -management and bus snoop configuration.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lpc-ctrl";
> > - "aspeed,ast2500-lpc-ctrl";
> > - "aspeed,ast2600-lpc-ctrl";
> > -
> > -- reg: contains offset/length values of the host interface controller
> > - memory regions
> > -
> > -- clocks: contains a phandle to the syscon node describing the clocks.
> > - There should then be one cell representing the clock to use
> > -
> > -Optional properties:
> > -
> > -- memory-region: A phandle to a reserved_memory region to be used for
> the LPC
> > - to AHB mapping
> > -
> > -- flash: A phandle to the SPI flash controller containing the flash to
> > - be exposed over the LPC to AHB mapping
> > -
> > -Example:
> > -
> > -lpc_ctrl: lpc-ctrl@80 {
> > - compatible = "aspeed,ast2500-lpc-ctrl";
> > - reg = <0x80 0x80>;
> > - clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
> > - memory-region = <&flash_memory>;
> > - flash = <&spi>;
> > -};
> > -
> > -LPC Host Controller
> > --------------------
> > -
> > -The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus
> > behaviour -between the host and the baseboard management controller.
> > The registers exist -in the "host" portion of the Aspeed LPC
> > controller, which must be the parent of -the LPC host controller node.
> > -
> > -Required properties:
> > -
> > -- compatible: One of:
> > - "aspeed,ast2400-lhc";
> > - "aspeed,ast2500-lhc";
> > - "aspeed,ast2600-lhc";
> > -
> > -- reg: contains offset/length values of the LHC memory regions. In the
> > - AST2400 and AST2500 there are two regions.
> > -
> > -Example:
> > -
> > -lhc: lhc@a0 {
> > - compatible = "aspeed,ast2500-lhc";
> > - reg = <0xa0 0x24 0xc8 0x8>;
> > -};
> > -
> > -LPC reset control
> > ------------------
> > -
> > -The UARTs present in the ASPEED SoC can have their resets tied to the
> > reset -state of the LPC bus. Some systems may chose to modify this
> configuration.
> > -
> > -Required properties:
> > -
> > - - compatible: One of:
> > - "aspeed,ast2600-lpc-reset";
> > - "aspeed,ast2500-lpc-reset";
> > - "aspeed,ast2400-lpc-reset";
> > -
> > - - reg: offset and length of the IP in the LHC memory region
> > - - #reset-controller indicates the number of reset cells expected
> > -
> > -Example:
> > -
> > -lpc_reset: reset-controller@98 {
> > - compatible = "aspeed,ast2500-lpc-reset";
> > - reg = <0x98 0x4>;
> > - #reset-cells = <1>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > new file mode 100644
> > index 000000000000..54f080df5e2f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml
> > @@ -0,0 +1,187 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # #
> > +Copyright (c) 2021 Aspeed Tehchnology Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Aspeed Low Pin Count (LPC) Bus Controller
> > +
> > +maintainers:
> > + - Andrew Jeffery <andrew@aj.id.au>
> > + - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
> > +
> > +description:
> > + The LPC bus is a means to bridge a host CPU to a number of
> > +low-bandwidth
> > + peripheral devices, replacing the use of the ISA bus in the age of
> > +PCI[0]. The
> > + primary use case of the Aspeed LPC controller is as a slave on the
> > +bus
> > + (typically in a Baseboard Management Controller SoC), but under
> > +certain
> > + conditions it can also take the role of bus master.
> > +
> > + The LPC controller is represented as a multi-function device to
> > + account for the mix of functionality, which includes, but is not
> > + limited to
> > +
> > + * An IPMI Block Transfer[2] Controller
> > +
> > + * An LPC Host Interface Controller manages functions exposed to the host
> such
> > + as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART
> > + management and bus snoop configuration.
> > +
> > + * A set of SuperIO[3] scratch registers enableing implementation of e.g.
> custom
> > + hardware management protocols for handover between the host and
> baseboard
> > + management controller.
> > +
> > + Additionally the state of the LPC controller influences the pinmux
> > + configuration, therefore the host portion of the controller is
> > + exposed as a syscon as a means to arbitrate access.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-v2
> > + - aspeed,ast2500-lpc-v2
> > + - aspeed,ast2600-lpc-v2
> > + - const: simple-mfd
> > + - const: syscon
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 1
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges: true
> > +
> > +patternProperties:
> > + "^lpc-ctrl@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC Host Interface Controller manages functions exposed to the
> host such as
> > + LPC firmware hub cycles, configuration of the LPC-to-AHB mapping,
> UART management
> > + and bus snoop configuration.
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-ctrl
> > + - aspeed,ast2500-lpc-ctrl
> > + - aspeed,ast2600-lpc-ctrl
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + memory-region:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A reserved_memory region to be used for the LPC
> > + to AHB mapping
> > +
> > + flash:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: The SPI flash controller containing the flash to
> > + be exposed over the LPC to AHB mapping
> > +
> > + required:
> > + - compatible
> > + - clocks
> > +
> > + "^reset-controller@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The UARTs present in the ASPEED SoC can have their resets tied to
> the reset
> > + state of the LPC bus. Some systems may chose to modify this
> > + configuration
> > +
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - aspeed,ast2400-lpc-reset
> > + - aspeed,ast2500-lpc-reset
> > + - aspeed,ast2600-lpc-reset
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + required:
> > + - compatible
> > +
> > + "^lpc-snoop@[0-9a-f]+$":
> > + type: object
> > +
> > + description:
> > + The LPC snoop interface allows the BMC to listen on and record the
> data
> > + bytes written by the Host to the targeted LPC I/O pots.
> > +
> > + properties:
> > + comptabile:
>
> I guess I have to point out *every* instance of your typo?
>
> Run 'make dt_binding_check' and find these problems before you send this
> out.
Sorry for making this error again.
I missed the "DT_CHECKER_FLAGS=-m" command line argument and thus the warning did not show up.
Will keep in mind next time. Thanks for your help.
Chiawei
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2021-09-22 10:29 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-16 9:25 [PATCH v5 0/4] arm: aspeed: Add UART routing support Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` [PATCH v5 1/4] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 12:21 ` Rob Herring
2021-09-16 12:21 ` Rob Herring
2021-09-16 12:21 ` Rob Herring
2021-09-16 14:31 ` Rob Herring
2021-09-16 14:31 ` Rob Herring
2021-09-16 14:31 ` Rob Herring
2021-09-22 5:54 ` ChiaWei Wang
2021-09-22 5:54 ` ChiaWei Wang
2021-09-22 5:54 ` ChiaWei Wang
2021-09-16 9:25 ` [PATCH v5 2/4] dt-bindings: aspeed: Add UART routing controller Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 20:18 ` Rob Herring
2021-09-16 20:18 ` Rob Herring
2021-09-16 20:18 ` Rob Herring
2021-09-17 0:46 ` ChiaWei Wang
2021-09-17 0:46 ` ChiaWei Wang
2021-09-17 0:46 ` ChiaWei Wang
2021-09-16 9:25 ` [PATCH v5 3/4] soc: aspeed: Add UART routing support Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` [PATCH v5 4/4] ARM: dts: aspeed: Add uart routing to device tree Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
2021-09-16 9:25 ` Chia-Wei Wang
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