From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com,
chenhuacai@loongson.cn, philmd@redhat.com,
richard.henderson@linaro.org, laurent@vivier.eu,
peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn,
alistair.francis@wdc.com, maobibo@loongson.cn,
pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org,
gaosong@loongson.cn
Subject: [PATCH v6 11/21] target/loongarch: Add floating point comparison instruction translation
Date: Fri, 17 Sep 2021 16:12:50 +0800 [thread overview]
Message-ID: <1631866380-31017-12-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1631866380-31017-1-git-send-email-gaosong@loongson.cn>
This patch implement floating point comparison instruction translation.
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: XiaoJuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/fpu_helper.c | 60 ++++++++++++++++++++++++++++++++
target/loongarch/helper.h | 9 +++++
target/loongarch/insn_trans/trans_fcmp.c | 59 +++++++++++++++++++++++++++++++
target/loongarch/insns.decode | 10 ++++++
target/loongarch/internals.h | 5 +++
target/loongarch/translate.c | 1 +
6 files changed, 144 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_fcmp.c
diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index 0106881..49d3af8 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -404,3 +404,63 @@ uint64_t helper_fmuladd_d(CPULoongArchState *env, uint64_t fj,
update_fcsr0(env, GETPC());
return fd;
}
+
+static uint64_t fcmp_common(CPULoongArchState *env, FloatRelation cmp,
+ uint32_t flags)
+{
+ bool ret;
+
+ switch (cmp) {
+ case float_relation_less:
+ ret = (flags & FCMP_LT);
+ break;
+ case float_relation_equal:
+ ret = (flags & FCMP_EQ);
+ break;
+ case float_relation_greater:
+ ret = (flags & FCMP_GT);
+ break;
+ case float_relation_unordered:
+ ret = (flags & FCMP_UN);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ update_fcsr0(env, GETPC());
+
+ return ret;
+}
+
+/* fcmp_cXXX_s */
+uint64_t helper_fcmp_c_s(CPULoongArchState *env, uint64_t fj,
+ uint64_t fk, uint32_t flags)
+{
+ FloatRelation cmp = float32_compare_quiet((uint32_t)fj,
+ (uint32_t)fk, &env->fp_status);
+ return fcmp_common(env, cmp, flags);
+}
+
+/* fcmp_sXXX_s */
+uint64_t helper_fcmp_s_s(CPULoongArchState *env, uint64_t fj,
+ uint64_t fk, uint32_t flags)
+{
+ FloatRelation cmp = float32_compare((uint32_t)fj,
+ (uint32_t)fk, &env->fp_status);
+ return fcmp_common(env, cmp, flags);
+}
+
+/* fcmp_cXXX_d */
+uint64_t helper_fcmp_c_d(CPULoongArchState *env, uint64_t fj,
+ uint64_t fk, uint32_t flags)
+{
+ FloatRelation cmp = float64_compare_quiet(fj, fk, &env->fp_status);
+ return fcmp_common(env, cmp, flags);
+}
+
+/* fcmp_sXXX_d */
+uint64_t helper_fcmp_s_d(CPULoongArchState *env, uint64_t fj,
+ uint64_t fk, uint32_t flags)
+{
+ FloatRelation cmp = float64_compare(fj, fk, &env->fp_status);
+ return fcmp_common(env, cmp, flags);
+}
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 901ab27..e0ab735 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -55,3 +55,12 @@ DEF_HELPER_2(frecip_d, i64, env, i64)
DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(fclass_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
+
+/* fcmp.cXXX.s */
+DEF_HELPER_4(fcmp_c_s, i64, env, i64, i64, i32)
+/* fcmp.sXXX.s */
+DEF_HELPER_4(fcmp_s_s, i64, env, i64, i64, i32)
+/* fcmp.cXXX.d */
+DEF_HELPER_4(fcmp_c_d, i64, env, i64, i64, i32)
+/* fcmp.sXXX.d */
+DEF_HELPER_4(fcmp_s_d, i64, env, i64, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_fcmp.c b/target/loongarch/insn_trans/trans_fcmp.c
new file mode 100644
index 0000000..1c5945b
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_fcmp.c
@@ -0,0 +1,59 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+/* bit0(signaling/quiet) bit1(lt) bit2(eq) bit3(un) bit4(neq) */
+static uint32_t get_fcmp_flags(int cond)
+{
+ uint32_t flags = 0;
+
+ if (cond & 0x1) {
+ flags |= FCMP_LT;
+ }
+ if (cond & 0x2) {
+ flags |= FCMP_EQ;
+ }
+ if (cond & 0x4) {
+ flags |= FCMP_UN;
+ }
+ if (cond & 0x8) {
+ flags |= FCMP_GT | FCMP_LT;
+ }
+ return flags;
+}
+
+static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
+{
+ TCGv var = tcg_temp_new();
+ uint32_t flags;
+ void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+
+ fn = (a->fcond & 1 ? gen_helper_fcmp_s_s : gen_helper_fcmp_c_s);
+ flags = get_fcmp_flags(a->fcond >> 1);
+
+ fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
+
+ tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+ tcg_temp_free(var);
+ return true;
+}
+
+static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
+{
+ TCGv var = tcg_temp_new();
+ uint32_t flags;
+ void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);
+ fn = (a->fcond & 1 ? gen_helper_fcmp_s_d : gen_helper_fcmp_c_d);
+ flags = get_fcmp_flags(a->fcond >> 1);
+
+ fn(var, cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk], tcg_constant_i32(flags));
+
+ tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+
+ tcg_temp_free(var);
+ return true;
+}
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 9e6a727..8aadcfd 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -32,6 +32,8 @@
%fj 5:5
%fk 10:5
%fa 15:5
+%cd 0:3
+%fcond 15:5
#
# Argument sets
@@ -56,6 +58,7 @@
&fmt_fdfjfk fd fj fk
&fmt_fdfjfkfa fd fj fk fa
&fmt_fdfj fd fj
+&fmt_cdfjfkfcond cd fj fk fcond
#
# Formats
@@ -80,6 +83,7 @@
@fmt_fdfjfk .... ........ ..... ..... ..... ..... &fmt_fdfjfk %fd %fj %fk
@fmt_fdfjfkfa .... ........ ..... ..... ..... ..... &fmt_fdfjfkfa %fd %fj %fk %fa
@fmt_fdfj .... ........ ..... ..... ..... ..... &fmt_fdfj %fd %fj
+@fmt_cdfjfkfcond .... ........ ..... ..... ..... .. ... &fmt_cdfjfkfcond %cd %fj %fk %fcond
#
# Fixed point arithmetic operation instruction
@@ -341,3 +345,9 @@ fcopysign_s 0000 00010001 00101 ..... ..... ..... @fmt_fdfjfk
fcopysign_d 0000 00010001 00110 ..... ..... ..... @fmt_fdfjfk
fclass_s 0000 00010001 01000 01101 ..... ..... @fmt_fdfj
fclass_d 0000 00010001 01000 01110 ..... ..... @fmt_fdfj
+
+#
+# Floating point compare instruction
+#
+fcmp_cond_s 0000 11000001 ..... ..... ..... 00 ... @fmt_cdfjfkfcond
+fcmp_cond_d 0000 11000010 ..... ..... ..... 00 ... @fmt_cdfjfkfcond
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 096a4a7..b408aed 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -9,6 +9,11 @@
#ifndef LOONGARCH_INTERNALS_H
#define LOONGARCH_INTERNALS_H
+#define FCMP_LT 0x0001 /* fp0 < fp1 */
+#define FCMP_EQ 0x0010 /* fp0 = fp1 */
+#define FCMP_UN 0x0100 /* unordered */
+#define FCMP_GT 0x1000 /* fp0 > fp1 */
+
void loongarch_translate_init(void);
void loongarch_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9eeaf76..7301ac5 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -187,6 +187,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_atomic.c"
#include "insn_trans/trans_extra.c"
#include "insn_trans/trans_farith.c"
+#include "insn_trans/trans_fcmp.c"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-09-17 8:32 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-17 8:12 [PATCH v6 00/21] Add LoongArch linux-user emulation support Song Gao
2021-09-17 8:12 ` [PATCH v6 01/21] target/loongarch: Add README Song Gao
2021-09-20 18:51 ` Richard Henderson
2021-09-17 8:12 ` [PATCH v6 02/21] target/loongarch: Add core definition Song Gao
2021-09-20 18:55 ` Richard Henderson
2021-09-17 8:12 ` [PATCH v6 03/21] target/loongarch: Add main translation routines Song Gao
2021-09-17 8:12 ` [PATCH v6 04/21] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-09-17 8:12 ` [PATCH v6 05/21] target/loongarch: Add fixed point shift " Song Gao
2021-09-17 8:12 ` [PATCH v6 06/21] target/loongarch: Add fixed point bit " Song Gao
2021-09-17 8:12 ` [PATCH v6 07/21] target/loongarch: Add fixed point load/store " Song Gao
2021-09-17 8:12 ` [PATCH v6 08/21] target/loongarch: Add fixed point atomic " Song Gao
2021-09-17 8:12 ` [PATCH v6 09/21] target/loongarch: Add fixed point extra " Song Gao
2021-09-17 8:12 ` [PATCH v6 10/21] target/loongarch: Add floating point arithmetic " Song Gao
2021-09-20 18:56 ` Richard Henderson
2021-09-17 8:12 ` Song Gao [this message]
2021-09-17 8:12 ` [PATCH v6 12/21] target/loongarch: Add floating point conversion " Song Gao
2021-09-17 8:12 ` [PATCH v6 13/21] target/loongarch: Add floating point move " Song Gao
2021-09-17 8:12 ` [PATCH v6 14/21] target/loongarch: Add floating point load/store " Song Gao
2021-09-17 8:12 ` [PATCH v6 15/21] target/loongarch: Add branch " Song Gao
2021-09-17 8:12 ` [PATCH v6 16/21] target/loongarch: Add disassembler Song Gao
2021-09-17 8:12 ` [PATCH v6 17/21] LoongArch Linux User Emulation Song Gao
2021-09-23 6:53 ` Laurent Vivier
2021-09-23 8:42 ` Song Gao
2021-09-17 8:12 ` [PATCH v6 18/21] default-configs: Add loongarch linux-user support Song Gao
2021-09-17 8:12 ` [PATCH v6 19/21] target/loongarch: Add target build suport Song Gao
2021-09-17 8:12 ` [PATCH v6 20/21] target/loongarch: 'make check-tcg' support Song Gao
2021-09-17 8:13 ` [PATCH v6 21/21] scripts: add loongarch64 binfmt config Song Gao
2021-09-20 21:17 ` [PATCH v6 00/21] Add LoongArch linux-user emulation support Richard Henderson
2021-09-22 6:22 ` Song Gao
2021-09-22 9:49 ` WANG Xuerui
2021-09-23 3:09 ` gaosong
2021-09-23 4:26 ` WANG Xuerui
2021-09-23 8:54 ` Song Gao
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