From: David Laight <David.Laight@ACULAB.COM>
To: 'Bin Meng' <bmeng.cn@gmail.com>
Cc: Matteo Croce <mcroce@linux.microsoft.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"Emil Renner Berthing" <kernel@esmil.dk>,
Akira Tsukamoto <akira.tsukamoto@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>
Subject: RE: [PATCH 1/3] riscv: optimized memcpy
Date: Tue, 15 Jun 2021 13:18:33 +0000 [thread overview]
Message-ID: <1632006872b04c64be828fa0c4e4eae0@AcuMS.aculab.com> (raw)
In-Reply-To: <CAEUhbmV+Vi0Ssyzq1B2RTkbjMpE21xjdj2MSKdLydgW6WuCKtA@mail.gmail.com>
From: Bin Meng
> Sent: 15 June 2021 14:09
>
> On Tue, Jun 15, 2021 at 4:57 PM David Laight <David.Laight@aculab.com> wrote:
> >
...
> > I'm surprised that the C loop:
> >
> > > + for (; count >= bytes_long; count -= bytes_long)
> > > + *d.ulong++ = *s.ulong++;
> >
> > ends up being faster than the ASM 'read lots' - 'write lots' loop.
>
> I believe that's because the assembly version has some unaligned
> access cases, which end up being trap-n-emulated in the OpenSBI
> firmware, and that is a big overhead.
Ah, that would make sense since the asm user copy code
was broken for misaligned copies.
I suspect memcpy() was broken the same way.
I'm surprised IP_NET_ALIGN isn't set to 2 to try to
avoid all these misaligned copies in the network stack.
Although avoiding 8n+4 aligned data is rather harder.
Misaligned copies are just best avoided - really even on x86.
The 'real fun' is when the access crosses TLB boundaries.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
WARNING: multiple messages have this Message-ID (diff)
From: David Laight <David.Laight@ACULAB.COM>
To: 'Bin Meng' <bmeng.cn@gmail.com>
Cc: Matteo Croce <mcroce@linux.microsoft.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"Emil Renner Berthing" <kernel@esmil.dk>,
Akira Tsukamoto <akira.tsukamoto@gmail.com>,
"Drew Fustini" <drew@beagleboard.org>
Subject: RE: [PATCH 1/3] riscv: optimized memcpy
Date: Tue, 15 Jun 2021 13:18:33 +0000 [thread overview]
Message-ID: <1632006872b04c64be828fa0c4e4eae0@AcuMS.aculab.com> (raw)
In-Reply-To: <CAEUhbmV+Vi0Ssyzq1B2RTkbjMpE21xjdj2MSKdLydgW6WuCKtA@mail.gmail.com>
From: Bin Meng
> Sent: 15 June 2021 14:09
>
> On Tue, Jun 15, 2021 at 4:57 PM David Laight <David.Laight@aculab.com> wrote:
> >
...
> > I'm surprised that the C loop:
> >
> > > + for (; count >= bytes_long; count -= bytes_long)
> > > + *d.ulong++ = *s.ulong++;
> >
> > ends up being faster than the ASM 'read lots' - 'write lots' loop.
>
> I believe that's because the assembly version has some unaligned
> access cases, which end up being trap-n-emulated in the OpenSBI
> firmware, and that is a big overhead.
Ah, that would make sense since the asm user copy code
was broken for misaligned copies.
I suspect memcpy() was broken the same way.
I'm surprised IP_NET_ALIGN isn't set to 2 to try to
avoid all these misaligned copies in the network stack.
Although avoiding 8n+4 aligned data is rather harder.
Misaligned copies are just best avoided - really even on x86.
The 'real fun' is when the access crosses TLB boundaries.
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
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next prev parent reply other threads:[~2021-06-15 13:18 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 2:38 [PATCH 0/3] riscv: optimized mem* functions Matteo Croce
2021-06-15 2:38 ` Matteo Croce
2021-06-15 2:38 ` [PATCH 1/3] riscv: optimized memcpy Matteo Croce
2021-06-15 2:38 ` Matteo Croce
2021-06-15 8:57 ` David Laight
2021-06-15 8:57 ` David Laight
2021-06-15 13:08 ` Bin Meng
2021-06-15 13:08 ` Bin Meng
2021-06-15 13:18 ` David Laight [this message]
2021-06-15 13:18 ` David Laight
2021-06-15 13:28 ` Bin Meng
2021-06-15 13:28 ` Bin Meng
2021-06-15 16:12 ` Emil Renner Berthing
2021-06-15 16:12 ` Emil Renner Berthing
2021-06-16 0:33 ` Bin Meng
2021-06-16 0:33 ` Bin Meng
2021-06-16 2:01 ` Matteo Croce
2021-06-16 2:01 ` Matteo Croce
2021-06-16 8:24 ` David Laight
2021-06-16 8:24 ` David Laight
2021-06-16 10:48 ` Akira Tsukamoto
2021-06-16 10:48 ` Akira Tsukamoto
2021-06-16 19:06 ` Matteo Croce
2021-06-16 19:06 ` Matteo Croce
2021-06-15 13:44 ` Matteo Croce
2021-06-15 13:44 ` Matteo Croce
2021-06-16 11:46 ` Guo Ren
2021-06-16 11:46 ` Guo Ren
2021-06-16 18:52 ` Matteo Croce
2021-06-16 18:52 ` Matteo Croce
2021-06-17 21:30 ` David Laight
2021-06-17 21:30 ` David Laight
2021-06-17 21:48 ` Matteo Croce
2021-06-17 21:48 ` Matteo Croce
2021-06-18 0:32 ` Matteo Croce
2021-06-18 0:32 ` Matteo Croce
2021-06-18 1:05 ` Matteo Croce
2021-06-18 1:05 ` Matteo Croce
2021-06-18 8:32 ` David Laight
2021-06-18 8:32 ` David Laight
2021-06-15 2:38 ` [PATCH 2/3] riscv: optimized memmove Matteo Croce
2021-06-15 2:38 ` Matteo Croce
2021-06-15 2:38 ` [PATCH 3/3] riscv: optimized memset Matteo Croce
2021-06-15 2:38 ` Matteo Croce
2021-06-15 2:43 ` [PATCH 0/3] riscv: optimized mem* functions Bin Meng
2021-06-15 2:43 ` Bin Meng
2024-01-28 11:10 [PATCH 0/3] riscv: optimize memcpy/memmove/memset Jisheng Zhang
2024-01-28 11:10 ` [PATCH 1/3] riscv: optimized memcpy Jisheng Zhang
2024-01-28 11:10 ` Jisheng Zhang
2024-01-28 12:35 ` David Laight
2024-01-28 12:35 ` David Laight
2024-01-30 12:11 ` Nick Kossifidis
2024-01-30 12:11 ` Nick Kossifidis
2024-01-30 22:44 ` kernel test robot
2024-01-31 0:19 ` kernel test robot
2024-01-31 0:19 ` kernel test robot
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