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Fri, 24 Sep 2021 03:09:18 -0700 Envelope-to: git@xilinx.com, arnd@arndb.de, saikrishna12468@gmail.com, broonie@kernel.org, robh+dt@kernel.org, gregkh@linuxfoundation.org, linux-arm-kernel@lists.infradead.org, iwamatsu@nigauri.org, p.yadav@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org Received: from [172.23.63.68] (port=39484 helo=xhdvnc208.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mTi8r-0003Y4-36; Fri, 24 Sep 2021 03:09:17 -0700 Received: by xhdvnc208.xilinx.com (Postfix, from userid 14964) id 4263720633; Fri, 24 Sep 2021 15:39:16 +0530 (IST) From: Sai Krishna Potthuri To: Mark Brown , Rob Herring , Pratyush Yadav , Michal Simek , "Greg Kroah-Hartman" CC: , , , , , , Arnd Bergmann , Nobuhiro Iwamatsu , Sai Krishna Potthuri Subject: [PATCH 0/4] spi: cadence-quadspi: Add Xilinx Versal OSPI support Date: Fri, 24 Sep 2021 15:37:07 +0530 Message-ID: <1632478031-12242-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 52bf69c4-5eaf-4048-a18c-08d97f436044 X-MS-TrafficTypeDiagnostic: BN7PR02MB4243: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2021 10:09:20.2963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52bf69c4-5eaf-4048-a18c-08d97f436044 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT014.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB4243 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Octal SPI(OSPI) controller support for Xilinx Versal SoC. Update the binding to add Xilinx Versal compatible string, also add 'power-domains' property and made as required for Xilinx Versal SoCs. Add API in xilinx firmware for configuring OSPI Mux, which is required to change the interface to OSPI. Xilinx Versal SoC has external DMA support, so by using the OSPI MUX selection, interface to the OSPI will be selected (either DMA interface or AXI slave interface). Xilinx Versal OSPI external DMA: Xilinx Versal OSPI DMA module is integrated to the Cadence OSPI Controller with the DMA write channel. Cadence OSPI Controller which reads the data from the Flash and stores in its internal SRAM and Xilinx Versal OSPI DMA which reads the data from the SRAM in the Cadence OSPI Controller using the DMA SRC channel and then the DMA DST channel initiates a write DMA transfer into the destined address location. Sai Krishna Potthuri (4): firmware: xilinx: Add OSPI Mux selection support dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC spi: cadence-quadspi: Add Xilinx Versal external DMA support .../bindings/spi/cdns,qspi-nor.yaml | 12 + drivers/firmware/xilinx/zynqmp.c | 17 ++ drivers/spi/spi-cadence-quadspi.c | 214 ++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 12 + 4 files changed, 255 insertions(+) -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A018C433F5 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add Octal SPI(OSPI) controller support for Xilinx Versal SoC. Update the binding to add Xilinx Versal compatible string, also add 'power-domains' property and made as required for Xilinx Versal SoCs. Add API in xilinx firmware for configuring OSPI Mux, which is required to change the interface to OSPI. Xilinx Versal SoC has external DMA support, so by using the OSPI MUX selection, interface to the OSPI will be selected (either DMA interface or AXI slave interface). Xilinx Versal OSPI external DMA: Xilinx Versal OSPI DMA module is integrated to the Cadence OSPI Controller with the DMA write channel. Cadence OSPI Controller which reads the data from the Flash and stores in its internal SRAM and Xilinx Versal OSPI DMA which reads the data from the SRAM in the Cadence OSPI Controller using the DMA SRC channel and then the DMA DST channel initiates a write DMA transfer into the destined address location. Sai Krishna Potthuri (4): firmware: xilinx: Add OSPI Mux selection support dt-bindings: spi: cadence-quadspi: Add support for Xilinx Versal OSPI spi: cadence-quadspi: Add OSPI support for Xilinx Versal SoC spi: cadence-quadspi: Add Xilinx Versal external DMA support .../bindings/spi/cdns,qspi-nor.yaml | 12 + drivers/firmware/xilinx/zynqmp.c | 17 ++ drivers/spi/spi-cadence-quadspi.c | 214 ++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 12 + 4 files changed, 255 insertions(+) -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel