From: patchwork-bot+netdevbpf@kernel.org
To: Geetha sowjanya <gakula@marvell.com>
Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
kuba@kernel.org, davem@davemloft.net, sgoutham@marvell.com,
sbhatta@marvell.com, hkelam@marvell.com
Subject: Re: [net-next v3 PATCH] octeontx2-pf: Use hardware register for CQE count
Date: Tue, 28 Sep 2021 13:20:06 +0000 [thread overview]
Message-ID: <163283520646.29265.11641226830844674997.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20210928055526.19286-1-gakula@marvell.com>
Hello:
This patch was applied to netdev/net-next.git (refs/heads/master):
On Tue, 28 Sep 2021 11:25:26 +0530 you wrote:
> Current driver uses software CQ head pointer to poll on CQE
> header in memory to determine if CQE is valid. Software needs
> to make sure, that the reads of the CQE do not get re-ordered
> so much that it ends up with an inconsistent view of the CQE.
> To ensure that DMB barrier after read to first CQE cacheline
> and before reading of the rest of the CQE is needed.
> But having barrier for every CQE read will impact the performance,
> instead use hardware CQ head and tail pointers to find the
> valid number of CQEs.
>
> [...]
Here is the summary with links:
- [net-next,v3] octeontx2-pf: Use hardware register for CQE count
https://git.kernel.org/netdev/net-next/c/af3826db74d1
You are awesome, thank you!
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prev parent reply other threads:[~2021-09-28 13:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-28 5:55 [net-next v3 PATCH] octeontx2-pf: Use hardware register for CQE count Geetha sowjanya
2021-09-28 13:20 ` patchwork-bot+netdevbpf [this message]
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