* [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
@ 2021-10-06 11:10 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This series includes the patches to add audio pinmux settings for LD11/LD20/PXs3
SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
the same kinds of pinmux settings as the other UniPhier SoCs.
---
Change since v1:
- Remove non-existent groups "usb2" and "usb3" in NX1 patch
Kunihiko Hayashi (3):
pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and
PXs3 SoCs
dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
pinctrl: uniphier: Add UniPhier NX1 pinctrl driver
.../pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 18 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 35 ++
drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c | 489 +++++++++++++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 40 ++
7 files changed, 588 insertions(+)
create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
--
2.7.4
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
@ 2021-10-06 11:10 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This series includes the patches to add audio pinmux settings for LD11/LD20/PXs3
SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
the same kinds of pinmux settings as the other UniPhier SoCs.
---
Change since v1:
- Remove non-existent groups "usb2" and "usb3" in NX1 patch
Kunihiko Hayashi (3):
pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and
PXs3 SoCs
dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
pinctrl: uniphier: Add UniPhier NX1 pinctrl driver
.../pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 18 +
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 35 ++
drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c | 489 +++++++++++++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 40 ++
7 files changed, 588 insertions(+)
create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 1/3] pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCs
2021-10-06 11:10 ` Kunihiko Hayashi
@ 2021-10-06 11:10 ` Kunihiko Hayashi
-1 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 18 +++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 35 +++++++++++++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 40 ++++++++++++++++++++++++
3 files changed, 93 insertions(+)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index c390a551d6dd..a4fa8e3af607 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -461,10 +461,18 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
166, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {151, 152, 153, 154, 155, 156, 157};
+static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
+static const unsigned ainiec1_pins[] = {150};
+static const int ainiec1_muxvals[] = {4};
+static const unsigned ainiec1b_pins[] = {141};
+static const int ainiec1b_muxvals[] = {4};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
+static const unsigned aoutiec2_pins[] = {135, 136};
+static const int aoutiec2_muxvals[] = {1, 1};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -573,8 +581,12 @@ static const unsigned int gpio_range5_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(ainiec1),
+ UNIPHIER_PINCTRL_GROUP(ainiec1b),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
@@ -614,8 +626,11 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5),
};
+static const char * const ain1_groups[] = {"ain1"};
static const char * const aout1_groups[] = {"aout1"};
+static const char * const ainiec1_groups[] = {"ainiec1", "ainiec1b"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const hscin0_groups[] = {"hscin0_ci",
@@ -646,8 +661,11 @@ static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(ainiec1),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(hscin0),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 0a8b1867057b..850736998206 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -542,12 +542,26 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
175, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {150, 151, 152, 153, 154, 155, 156};
+static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4};
+static const unsigned ain2_pins[] = {116, 117, 118, 119, 120, 121, 122};
+static const int ain2_muxvals[] = {26, 26, 26, 26, 26, 26, 26};
+static const unsigned ain3_pins[] = {116, 117, 118, 119};
+static const int ain3_muxvals[] = {27, 27, 27, 27};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156};
static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout2_pins[] = {165, 157, 162, 158, 159, 160, 161};
+static const int aout2_muxvals[] = {2, 2, 2, 1, 1, 1, 1};
+static const unsigned aout3_pins[] = {166, 167, 168, 163};
+static const int aout3_muxvals[] = {2, 2, 2, 1};
+static const unsigned aout4_pins[] = {169, 170, 171, 164};
+static const int aout4_muxvals[] = {2, 2, 2, 1};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
+static const unsigned aoutiec2_pins[] = {135, 136};
+static const int aoutiec2_muxvals[] = {1, 1};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -667,9 +681,16 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
+ UNIPHIER_PINCTRL_GROUP(ain2),
+ UNIPHIER_PINCTRL_GROUP(ain3),
UNIPHIER_PINCTRL_GROUP(aout1),
UNIPHIER_PINCTRL_GROUP(aout1b),
+ UNIPHIER_PINCTRL_GROUP(aout2),
+ UNIPHIER_PINCTRL_GROUP(aout3),
+ UNIPHIER_PINCTRL_GROUP(aout4),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@@ -713,8 +734,15 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
+static const char * const ain1_groups[] = {"ain1"};
+static const char * const ain2_groups[] = {"ain2"};
+static const char * const ain3_groups[] = {"ain3"};
static const char * const aout1_groups[] = {"aout1", "aout1b"};
+static const char * const aout2_groups[] = {"aout2"};
+static const char * const aout3_groups[] = {"aout3"};
+static const char * const aout4_groups[] = {"aout4"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@@ -752,8 +780,15 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
+ UNIPHIER_PINMUX_FUNCTION(ain2),
+ UNIPHIER_PINMUX_FUNCTION(ain3),
UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aout2),
+ UNIPHIER_PINMUX_FUNCTION(aout3),
+ UNIPHIER_PINMUX_FUNCTION(aout4),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index 2b388fdcca3a..4810db6c0ee8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -767,6 +767,22 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = {
250, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {186, 187, 188, 189, 237, 238, 239};
+static const int ain1_muxvals[] = {0, 0, 0, 0, 1, 1, 1};
+static const unsigned ain2_pins[] = {243, 244, 245, 246, 247, 248, 249};
+static const int ain2_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout1_pins[] = {226, 227, 228, 229, 230, 231, 232};
+static const int aout1_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout2_pins[] = {192, 193, 194, 195, 196, 197, 198};
+static const int aout2_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned aout3_pins[] = {199, 200, 201, 202};
+static const int aout3_muxvals[] = {0, 0, 0, 0};
+static const unsigned ainiec1_pins[] = {240};
+static const int ainiec1_muxvals[] = {1};
+static const unsigned aoutiec1_pins[] = {190};
+static const int aoutiec1_muxvals[] = {0};
+static const unsigned aoutiec2_pins[] = {191};
+static const int aoutiec2_muxvals[] = {0};
static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42};
@@ -871,6 +887,14 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
+ UNIPHIER_PINCTRL_GROUP(ain2),
+ UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(aout2),
+ UNIPHIER_PINCTRL_GROUP(aout3),
+ UNIPHIER_PINCTRL_GROUP(ainiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@@ -902,6 +926,14 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
+static const char * const ain1_groups[] = {"ain1"};
+static const char * const ain2_groups[] = {"ain2"};
+static const char * const aout1_groups[] = {"aout1"};
+static const char * const aout2_groups[] = {"aout2"};
+static const char * const aout3_groups[] = {"aout3"};
+static const char * const ainiec1_groups[] = {"ainiec1"};
+static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@@ -928,6 +960,14 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_pxs3_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
+ UNIPHIER_PINMUX_FUNCTION(ain2),
+ UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aout2),
+ UNIPHIER_PINMUX_FUNCTION(aout3),
+ UNIPHIER_PINMUX_FUNCTION(ainiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 1/3] pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCs
@ 2021-10-06 11:10 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c | 18 +++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c | 35 +++++++++++++++++++++
drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 40 ++++++++++++++++++++++++
3 files changed, 93 insertions(+)
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index c390a551d6dd..a4fa8e3af607 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -461,10 +461,18 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
166, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {151, 152, 153, 154, 155, 156, 157};
+static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
+static const unsigned ainiec1_pins[] = {150};
+static const int ainiec1_muxvals[] = {4};
+static const unsigned ainiec1b_pins[] = {141};
+static const int ainiec1b_muxvals[] = {4};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
+static const unsigned aoutiec2_pins[] = {135, 136};
+static const int aoutiec2_muxvals[] = {1, 1};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -573,8 +581,12 @@ static const unsigned int gpio_range5_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(ainiec1),
+ UNIPHIER_PINCTRL_GROUP(ainiec1b),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rmii),
@@ -614,8 +626,11 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range5),
};
+static const char * const ain1_groups[] = {"ain1"};
static const char * const aout1_groups[] = {"aout1"};
+static const char * const ainiec1_groups[] = {"ainiec1", "ainiec1b"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
static const char * const hscin0_groups[] = {"hscin0_ci",
@@ -646,8 +661,11 @@ static const char * const usb1_groups[] = {"usb1"};
static const char * const usb2_groups[] = {"usb2"};
static const struct uniphier_pinmux_function uniphier_ld11_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(ainiec1),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
UNIPHIER_PINMUX_FUNCTION(hscin0),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 0a8b1867057b..850736998206 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -542,12 +542,26 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
175, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {150, 151, 152, 153, 154, 155, 156};
+static const int ain1_muxvals[] = {4, 4, 4, 4, 4, 4, 4};
+static const unsigned ain2_pins[] = {116, 117, 118, 119, 120, 121, 122};
+static const int ain2_muxvals[] = {26, 26, 26, 26, 26, 26, 26};
+static const unsigned ain3_pins[] = {116, 117, 118, 119};
+static const int ain3_muxvals[] = {27, 27, 27, 27};
static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142};
static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0};
static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156};
static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout2_pins[] = {165, 157, 162, 158, 159, 160, 161};
+static const int aout2_muxvals[] = {2, 2, 2, 1, 1, 1, 1};
+static const unsigned aout3_pins[] = {166, 167, 168, 163};
+static const int aout3_muxvals[] = {2, 2, 2, 1};
+static const unsigned aout4_pins[] = {169, 170, 171, 164};
+static const int aout4_muxvals[] = {2, 2, 2, 1};
static const unsigned aoutiec1_pins[] = {135, 136};
static const int aoutiec1_muxvals[] = {0, 0};
+static const unsigned aoutiec2_pins[] = {135, 136};
+static const int aoutiec2_muxvals[] = {1, 1};
static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
@@ -667,9 +681,16 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
+ UNIPHIER_PINCTRL_GROUP(ain2),
+ UNIPHIER_PINCTRL_GROUP(ain3),
UNIPHIER_PINCTRL_GROUP(aout1),
UNIPHIER_PINCTRL_GROUP(aout1b),
+ UNIPHIER_PINCTRL_GROUP(aout2),
+ UNIPHIER_PINCTRL_GROUP(aout3),
+ UNIPHIER_PINCTRL_GROUP(aout4),
UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@@ -713,8 +734,15 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
+static const char * const ain1_groups[] = {"ain1"};
+static const char * const ain2_groups[] = {"ain2"};
+static const char * const ain3_groups[] = {"ain3"};
static const char * const aout1_groups[] = {"aout1", "aout1b"};
+static const char * const aout2_groups[] = {"aout2"};
+static const char * const aout3_groups[] = {"aout3"};
+static const char * const aout4_groups[] = {"aout4"};
static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@@ -752,8 +780,15 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_ld20_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
+ UNIPHIER_PINMUX_FUNCTION(ain2),
+ UNIPHIER_PINMUX_FUNCTION(ain3),
UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aout2),
+ UNIPHIER_PINMUX_FUNCTION(aout3),
+ UNIPHIER_PINMUX_FUNCTION(aout4),
UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index 2b388fdcca3a..4810db6c0ee8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -767,6 +767,22 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = {
250, UNIPHIER_PIN_PULL_DOWN),
};
+static const unsigned ain1_pins[] = {186, 187, 188, 189, 237, 238, 239};
+static const int ain1_muxvals[] = {0, 0, 0, 0, 1, 1, 1};
+static const unsigned ain2_pins[] = {243, 244, 245, 246, 247, 248, 249};
+static const int ain2_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout1_pins[] = {226, 227, 228, 229, 230, 231, 232};
+static const int aout1_muxvals[] = {1, 1, 1, 1, 1, 1, 1};
+static const unsigned aout2_pins[] = {192, 193, 194, 195, 196, 197, 198};
+static const int aout2_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
+static const unsigned aout3_pins[] = {199, 200, 201, 202};
+static const int aout3_muxvals[] = {0, 0, 0, 0};
+static const unsigned ainiec1_pins[] = {240};
+static const int ainiec1_muxvals[] = {1};
+static const unsigned aoutiec1_pins[] = {190};
+static const int aoutiec1_muxvals[] = {0};
+static const unsigned aoutiec2_pins[] = {191};
+static const int aoutiec2_muxvals[] = {0};
static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38};
static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42};
@@ -871,6 +887,14 @@ static const unsigned int gpio_range2_pins[] = {
};
static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(ain1),
+ UNIPHIER_PINCTRL_GROUP(ain2),
+ UNIPHIER_PINCTRL_GROUP(aout1),
+ UNIPHIER_PINCTRL_GROUP(aout2),
+ UNIPHIER_PINCTRL_GROUP(aout3),
+ UNIPHIER_PINCTRL_GROUP(ainiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec1),
+ UNIPHIER_PINCTRL_GROUP(aoutiec2),
UNIPHIER_PINCTRL_GROUP(emmc),
UNIPHIER_PINCTRL_GROUP(emmc_dat8),
UNIPHIER_PINCTRL_GROUP(ether_rgmii),
@@ -902,6 +926,14 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = {
UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
};
+static const char * const ain1_groups[] = {"ain1"};
+static const char * const ain2_groups[] = {"ain2"};
+static const char * const aout1_groups[] = {"aout1"};
+static const char * const aout2_groups[] = {"aout2"};
+static const char * const aout3_groups[] = {"aout3"};
+static const char * const ainiec1_groups[] = {"ainiec1"};
+static const char * const aoutiec1_groups[] = {"aoutiec1"};
+static const char * const aoutiec2_groups[] = {"aoutiec2"};
static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
static const char * const ether_rmii_groups[] = {"ether_rmii"};
@@ -928,6 +960,14 @@ static const char * const usb2_groups[] = {"usb2"};
static const char * const usb3_groups[] = {"usb3"};
static const struct uniphier_pinmux_function uniphier_pxs3_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(ain1),
+ UNIPHIER_PINMUX_FUNCTION(ain2),
+ UNIPHIER_PINMUX_FUNCTION(aout1),
+ UNIPHIER_PINMUX_FUNCTION(aout2),
+ UNIPHIER_PINMUX_FUNCTION(aout3),
+ UNIPHIER_PINMUX_FUNCTION(ainiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec1),
+ UNIPHIER_PINMUX_FUNCTION(aoutiec2),
UNIPHIER_PINMUX_FUNCTION(emmc),
UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
UNIPHIER_PINMUX_FUNCTION(ether_rmii),
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/3] dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
2021-10-06 11:10 ` Kunihiko Hayashi
@ 2021-10-06 11:10 ` Kunihiko Hayashi
-1 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Update pinctrl binding document for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
index 502480a19f49..a804d9bc1602 100644
--- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
@@ -24,6 +24,7 @@ properties:
- socionext,uniphier-ld11-pinctrl
- socionext,uniphier-ld20-pinctrl
- socionext,uniphier-pxs3-pinctrl
+ - socionext,uniphier-nx1-pinctrl
required:
- compatible
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 2/3] dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
@ 2021-10-06 11:10 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Update pinctrl binding document for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
index 502480a19f49..a804d9bc1602 100644
--- a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml
@@ -24,6 +24,7 @@ properties:
- socionext,uniphier-ld11-pinctrl
- socionext,uniphier-ld20-pinctrl
- socionext,uniphier-pxs3-pinctrl
+ - socionext,uniphier-nx1-pinctrl
required:
- compatible
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/3] pinctrl: uniphier: Add UniPhier NX1 pinctrl driver
2021-10-06 11:10 ` Kunihiko Hayashi
@ 2021-10-06 11:10 ` Kunihiko Hayashi
-1 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add pin configuration and pinmux support for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c | 489 ++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index c51a4db16040..b71c07d84662 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -45,4 +45,8 @@ config PINCTRL_UNIPHIER_PXS3
bool "UniPhier PXs3 SoC pinctrl driver"
default ARM64
+config PINCTRL_UNIPHIER_NX1
+ bool "UniPhier NX1 SoC pinctrl driver"
+ default ARM64
+
endif
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index ec66c86e276e..59932cb3e8ff 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3) += pinctrl-uniphier-pxs3.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_NX1) += pinctrl-uniphier-nx1.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
new file mode 100644
index 000000000000..4fd3ec511d37
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2019 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct pinctrl_pin_desc uniphier_nx1_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "LPST", UNIPHIER_PIN_IECTRL_EXIST,
+ 0, UNIPHIER_PIN_DRV_3BIT,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 12, UNIPHIER_PIN_DRV_2BIT,
+ 1, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(2, "SDCMD", UNIPHIER_PIN_IECTRL_EXIST,
+ 13, UNIPHIER_PIN_DRV_2BIT,
+ 2, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(3, "SDDAT0", UNIPHIER_PIN_IECTRL_EXIST,
+ 14, UNIPHIER_PIN_DRV_2BIT,
+ 3, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(4, "SDDAT1", UNIPHIER_PIN_IECTRL_EXIST,
+ 15, UNIPHIER_PIN_DRV_2BIT,
+ 4, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(5, "SDDAT2", UNIPHIER_PIN_IECTRL_EXIST,
+ 16, UNIPHIER_PIN_DRV_2BIT,
+ 5, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(6, "SDDAT3", UNIPHIER_PIN_IECTRL_EXIST,
+ 17, UNIPHIER_PIN_DRV_2BIT,
+ 6, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(7, "SDCD", UNIPHIER_PIN_IECTRL_EXIST,
+ 1, UNIPHIER_PIN_DRV_3BIT,
+ 7, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(8, "SDWP", UNIPHIER_PIN_IECTRL_EXIST,
+ 2, UNIPHIER_PIN_DRV_3BIT,
+ 8, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(9, "SDVOLC", UNIPHIER_PIN_IECTRL_EXIST,
+ 3, UNIPHIER_PIN_DRV_3BIT,
+ 9, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(10, "XERST", UNIPHIER_PIN_IECTRL_EXIST,
+ 0, UNIPHIER_PIN_DRV_2BIT,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "MDC", UNIPHIER_PIN_IECTRL_EXIST,
+ 18, UNIPHIER_PIN_DRV_2BIT,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(12, "MDIO", UNIPHIER_PIN_IECTRL_EXIST,
+ 19, UNIPHIER_PIN_DRV_2BIT,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "MDIO_INTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 20, UNIPHIER_PIN_DRV_2BIT,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(14, "PHYRSTL", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(15, "RGMII_RXCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 22, UNIPHIER_PIN_DRV_2BIT,
+ 15, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "RGMII_RXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 23, UNIPHIER_PIN_DRV_2BIT,
+ 16, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "RGMII_RXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 24, UNIPHIER_PIN_DRV_2BIT,
+ 17, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "RGMII_RXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 25, UNIPHIER_PIN_DRV_2BIT,
+ 18, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "RGMII_RXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 26, UNIPHIER_PIN_DRV_2BIT,
+ 19, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "RGMII_RXCTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 27, UNIPHIER_PIN_DRV_2BIT,
+ 20, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "RGMII_TXCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 28, UNIPHIER_PIN_DRV_2BIT,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "RGMII_TXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 29, UNIPHIER_PIN_DRV_2BIT,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "RGMII_TXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 30, UNIPHIER_PIN_DRV_2BIT,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "RGMII_TXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 31, UNIPHIER_PIN_DRV_2BIT,
+ 24, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(25, "RGMII_TXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 32, UNIPHIER_PIN_DRV_2BIT,
+ 25, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(26, "RGMII_TXCTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 33, UNIPHIER_PIN_DRV_2BIT,
+ 26, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(27, "TXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 4, UNIPHIER_PIN_DRV_3BIT,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "RXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 5, UNIPHIER_PIN_DRV_3BIT,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "TXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 6, UNIPHIER_PIN_DRV_3BIT,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "RXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 7, UNIPHIER_PIN_DRV_3BIT,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "XRTS1", UNIPHIER_PIN_IECTRL_EXIST,
+ 8, UNIPHIER_PIN_DRV_3BIT,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "XDTR1", UNIPHIER_PIN_IECTRL_EXIST,
+ 9, UNIPHIER_PIN_DRV_3BIT,
+ 32, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(33, "XCTS1", UNIPHIER_PIN_IECTRL_EXIST,
+ 10, UNIPHIER_PIN_DRV_3BIT,
+ 33, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(34, "XDSR1", UNIPHIER_PIN_IECTRL_EXIST,
+ 11, UNIPHIER_PIN_DRV_3BIT,
+ 34, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(35, "XDCD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 12, UNIPHIER_PIN_DRV_3BIT,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(36, "TXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 13, UNIPHIER_PIN_DRV_3BIT,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(37, "RXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 14, UNIPHIER_PIN_DRV_3BIT,
+ 37, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(38, "XRTS2", UNIPHIER_PIN_IECTRL_EXIST,
+ 15, UNIPHIER_PIN_DRV_3BIT,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(39, "XCTS2", UNIPHIER_PIN_IECTRL_EXIST,
+ 16, UNIPHIER_PIN_DRV_3BIT,
+ 39, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(40, "TXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 17, UNIPHIER_PIN_DRV_3BIT,
+ 40, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(41, "RXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 18, UNIPHIER_PIN_DRV_3BIT,
+ 41, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(42, "SPISYNC0", UNIPHIER_PIN_IECTRL_EXIST,
+ 19, UNIPHIER_PIN_DRV_3BIT,
+ 42, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(43, "SPISCLK0", UNIPHIER_PIN_IECTRL_EXIST,
+ 20, UNIPHIER_PIN_DRV_3BIT,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "SPITXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 21, UNIPHIER_PIN_DRV_3BIT,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "SPIRXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 22, UNIPHIER_PIN_DRV_3BIT,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "SPISYNC1", UNIPHIER_PIN_IECTRL_EXIST,
+ 23, UNIPHIER_PIN_DRV_3BIT,
+ 46, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(47, "SPISCLK1", UNIPHIER_PIN_IECTRL_EXIST,
+ 24, UNIPHIER_PIN_DRV_3BIT,
+ 47, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(48, "SPITXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 25, UNIPHIER_PIN_DRV_3BIT,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "SPIRXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 26, UNIPHIER_PIN_DRV_3BIT,
+ 49, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(50, "SDA0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(51, "SCL0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(52, "SDA1", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(53, "SCL1", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(54, "SDA2", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(55, "SCL2", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(56, "SDA3", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(57, "SCL3", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(58, "XIRQ0", UNIPHIER_PIN_IECTRL_EXIST,
+ 27, UNIPHIER_PIN_DRV_3BIT,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "XIRQ1", UNIPHIER_PIN_IECTRL_EXIST,
+ 28, UNIPHIER_PIN_DRV_3BIT,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "XIRQ2", UNIPHIER_PIN_IECTRL_EXIST,
+ 29, UNIPHIER_PIN_DRV_3BIT,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "XIRQ3", UNIPHIER_PIN_IECTRL_EXIST,
+ 30, UNIPHIER_PIN_DRV_3BIT,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "XIRQ4", UNIPHIER_PIN_IECTRL_EXIST,
+ 31, UNIPHIER_PIN_DRV_3BIT,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "XIRQ5", UNIPHIER_PIN_IECTRL_EXIST,
+ 32, UNIPHIER_PIN_DRV_3BIT,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "PORT00", UNIPHIER_PIN_IECTRL_EXIST,
+ 33, UNIPHIER_PIN_DRV_3BIT,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "PORT01", UNIPHIER_PIN_IECTRL_EXIST,
+ 34, UNIPHIER_PIN_DRV_3BIT,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "PORT02", UNIPHIER_PIN_IECTRL_EXIST,
+ 35, UNIPHIER_PIN_DRV_3BIT,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "PORT03", UNIPHIER_PIN_IECTRL_EXIST,
+ 36, UNIPHIER_PIN_DRV_3BIT,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "PORT04", UNIPHIER_PIN_IECTRL_EXIST,
+ 37, UNIPHIER_PIN_DRV_3BIT,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "PORT05", UNIPHIER_PIN_IECTRL_EXIST,
+ 38, UNIPHIER_PIN_DRV_3BIT,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "PORT06", UNIPHIER_PIN_IECTRL_EXIST,
+ 39, UNIPHIER_PIN_DRV_3BIT,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "PORT07", UNIPHIER_PIN_IECTRL_EXIST,
+ 40, UNIPHIER_PIN_DRV_3BIT,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "PORT10", UNIPHIER_PIN_IECTRL_EXIST,
+ 41, UNIPHIER_PIN_DRV_3BIT,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "PORT11", UNIPHIER_PIN_IECTRL_EXIST,
+ 42, UNIPHIER_PIN_DRV_3BIT,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "PORT12", UNIPHIER_PIN_IECTRL_EXIST,
+ 43, UNIPHIER_PIN_DRV_3BIT,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "PORT13", UNIPHIER_PIN_IECTRL_EXIST,
+ 44, UNIPHIER_PIN_DRV_3BIT,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "PORT14", UNIPHIER_PIN_IECTRL_EXIST,
+ 45, UNIPHIER_PIN_DRV_3BIT,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "PORT15", UNIPHIER_PIN_IECTRL_EXIST,
+ 46, UNIPHIER_PIN_DRV_3BIT,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "USBAVBUS", UNIPHIER_PIN_IECTRL_EXIST,
+ 47, UNIPHIER_PIN_DRV_3BIT,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "USBAOD", UNIPHIER_PIN_IECTRL_EXIST,
+ 48, UNIPHIER_PIN_DRV_3BIT,
+ 79, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(80, "USBBVBUS", UNIPHIER_PIN_IECTRL_EXIST,
+ 49, UNIPHIER_PIN_DRV_3BIT,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "USBBOD", UNIPHIER_PIN_IECTRL_EXIST,
+ 50, UNIPHIER_PIN_DRV_3BIT,
+ 81, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(82, "HTDDCSDA0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(83, "HTDDCSCL0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(84, "HTHPDI0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(85, "MMCCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 1, UNIPHIER_PIN_DRV_2BIT,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "MMCCMD", UNIPHIER_PIN_IECTRL_EXIST,
+ 2, UNIPHIER_PIN_DRV_2BIT,
+ 86, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(87, "MMCDS", UNIPHIER_PIN_IECTRL_EXIST,
+ 3, UNIPHIER_PIN_DRV_2BIT,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "MMCDAT0", UNIPHIER_PIN_IECTRL_EXIST,
+ 4, UNIPHIER_PIN_DRV_2BIT,
+ 88, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(89, "MMCDAT1", UNIPHIER_PIN_IECTRL_EXIST,
+ 5, UNIPHIER_PIN_DRV_2BIT,
+ 89, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(90, "MMCDAT2", UNIPHIER_PIN_IECTRL_EXIST,
+ 6, UNIPHIER_PIN_DRV_2BIT,
+ 90, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(91, "MMCDAT3", UNIPHIER_PIN_IECTRL_EXIST,
+ 7, UNIPHIER_PIN_DRV_2BIT,
+ 91, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(92, "MMCDAT4", UNIPHIER_PIN_IECTRL_EXIST,
+ 8, UNIPHIER_PIN_DRV_2BIT,
+ 92, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(93, "MMCDAT5", UNIPHIER_PIN_IECTRL_EXIST,
+ 9, UNIPHIER_PIN_DRV_2BIT,
+ 93, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(94, "MMCDAT6", UNIPHIER_PIN_IECTRL_EXIST,
+ 10, UNIPHIER_PIN_DRV_2BIT,
+ 94, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(95, "MMCDAT7", UNIPHIER_PIN_IECTRL_EXIST,
+ 11, UNIPHIER_PIN_DRV_2BIT,
+ 95, UNIPHIER_PIN_PULL_UP),
+};
+
+static const unsigned int emmc_pins[] = {85, 86, 87, 88, 89, 90, 91};
+static const int emmc_muxvals[] = {-1, -1, -1, -1, -1, -1, -1};
+static const unsigned int emmc_dat8_pins[] = {92, 93, 94, 95};
+static const int emmc_dat8_muxvals[] = {-1, -1, -1, -1};
+static const unsigned int ether_rgmii_pins[] = {11, 12, 13, 14, 15, 16, 17, 18,
+ 19, 20, 21, 22, 23, 24, 25, 26};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0};
+static const unsigned int ether_rmii_pins[] = {11, 12, 13, 14, 15, 16, 17, 18,
+ 20, 22, 23, 26};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned int i2c0_pins[] = {50, 51};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned int i2c1_pins[] = {52, 53};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned int i2c2_pins[] = {54, 55};
+static const int i2c2_muxvals[] = {0, 0};
+static const unsigned int i2c3_pins[] = {56, 57};
+static const int i2c3_muxvals[] = {0, 0};
+static const unsigned int i2c4_pins[] = {72, 73};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned int i2c5_pins[] = {74, 75};
+static const int i2c5_muxvals[] = {1, 1};
+static const unsigned int i2c6_pins[] = {82, 83};
+static const int i2c6_muxvals[] = {1, 1};
+static const unsigned int sd_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {42, 43, 44, 45};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {46, 47, 48, 49};
+static const int spi1_muxvals[] = {0, 0, 0, 0};
+static const unsigned int uart0_pins[] = {27, 28};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned int uart1_pins[] = {29, 30};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned int uart1_ctsrts_pins[] = {31, 33};
+static const int uart1_ctsrts_muxvals[] = {0, 0};
+static const unsigned int uart1_modem_pins[] = {32, 34, 35};
+static const int uart1_modem_muxvals[] = {0, 0, 0};
+static const unsigned int uart2_pins[] = {36, 37};
+static const int uart2_muxvals[] = {0, 0};
+static const unsigned int uart2_ctsrts_pins[] = {38, 39};
+static const int uart2_ctsrts_muxvals[] = {0, 0};
+static const unsigned int uart3_pins[] = {40, 41};
+static const int uart3_muxvals[] = {0, 0};
+static const unsigned int usb0_pins[] = {78, 79};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned int usb1_pins[] = {80, 81};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned int gpio_range0_pins[] = {
+ 64, 65, 66, 67, 68, 69, 70, 71, /* PORT0x */
+ 72, 73, 74, 75, 76, 77, 0, 1, /* PORT1x */
+ 2, 3, 4, 5, 6, 7, 8, 9, /* PORT2x */
+ 10, 78, 79, 80, 81, /* PORT30-34 */
+};
+static const unsigned int gpio_range1_pins[] = {
+ 11, 12, 13, /* PORT61-63 */
+};
+static const unsigned int gpio_range2_pins[] = {
+ 15, 16, 17, /* PORT65-67 */
+ 18, 19, 20, 21, 22, 23, 24, 25, /* PORT7x */
+ 26, 27, 28, 29, 30, 31, 32, 33, /* PORT8x */
+ 34, 35, 36, 37, 38, 39, 40, 41, /* PORT9x */
+ 42, 43, 44, 45, 46, 47, 48, 49, /* PORT10x */
+};
+static const unsigned int gpio_range3_pins[] = {
+ 58, 59, 60, 61, 62, 63, /* PORT12x */
+};
+static const unsigned int gpio_range4_pins[] = {
+ 58, 59, 60, 61, 62, 63, /* XIRQ0-5 */
+};
+
+static const struct uniphier_pinctrl_group uniphier_nx1_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(spi0),
+ UNIPHIER_PINCTRL_GROUP(spi1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1_ctsrts),
+ UNIPHIER_PINCTRL_GROUP(uart1_modem),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart2_ctsrts),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range3),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range4),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c4_groups[] = {"i2c4"};
+static const char * const i2c5_groups[] = {"i2c5"};
+static const char * const i2c6_groups[] = {"i2c6"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const spi0_groups[] = {"spi0"};
+static const char * const spi1_groups[] = {"spi1"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1", "uart1_ctsrts",
+ "uart1_modem"};
+static const char * const uart2_groups[] = {"uart2", "uart2_ctsrts"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+
+static const struct uniphier_pinmux_function uniphier_nx1_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c4),
+ UNIPHIER_PINMUX_FUNCTION(i2c5),
+ UNIPHIER_PINMUX_FUNCTION(i2c6),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(spi0),
+ UNIPHIER_PINMUX_FUNCTION(spi1),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+};
+
+static int uniphier_nx1_get_gpio_muxval(unsigned int pin,
+ unsigned int gpio_offset)
+{
+ if (gpio_offset >= 120) /* XIRQx */
+ return 14;
+
+ return 15;
+}
+
+static const struct uniphier_pinctrl_socdata uniphier_nx1_pindata = {
+ .pins = uniphier_nx1_pins,
+ .npins = ARRAY_SIZE(uniphier_nx1_pins),
+ .groups = uniphier_nx1_groups,
+ .groups_count = ARRAY_SIZE(uniphier_nx1_groups),
+ .functions = uniphier_nx1_functions,
+ .functions_count = ARRAY_SIZE(uniphier_nx1_functions),
+ .get_gpio_muxval = uniphier_nx1_get_gpio_muxval,
+ .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_nx1_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &uniphier_nx1_pindata);
+}
+
+static const struct of_device_id uniphier_nx1_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-nx1-pinctrl" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver uniphier_nx1_pinctrl_driver = {
+ .probe = uniphier_nx1_pinctrl_probe,
+ .driver = {
+ .name = "uniphier-nx1-pinctrl",
+ .of_match_table = uniphier_nx1_pinctrl_match,
+ .pm = &uniphier_pinctrl_pm_ops,
+ },
+};
+builtin_platform_driver(uniphier_nx1_pinctrl_driver);
--
2.7.4
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v2 3/3] pinctrl: uniphier: Add UniPhier NX1 pinctrl driver
@ 2021-10-06 11:10 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-06 11:10 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Masami Hiramatsu
Cc: linux-gpio, devicetree, linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add pin configuration and pinmux support for UniPhier NX1 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pinctrl/uniphier/Kconfig | 4 +
drivers/pinctrl/uniphier/Makefile | 1 +
drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c | 489 ++++++++++++++++++++++++
3 files changed, 494 insertions(+)
create mode 100644 drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index c51a4db16040..b71c07d84662 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -45,4 +45,8 @@ config PINCTRL_UNIPHIER_PXS3
bool "UniPhier PXs3 SoC pinctrl driver"
default ARM64
+config PINCTRL_UNIPHIER_NX1
+ bool "UniPhier NX1 SoC pinctrl driver"
+ default ARM64
+
endif
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index ec66c86e276e..59932cb3e8ff 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_UNIPHIER_LD6B) += pinctrl-uniphier-ld6b.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD11) += pinctrl-uniphier-ld11.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD20) += pinctrl-uniphier-ld20.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PXS3) += pinctrl-uniphier-pxs3.o
+obj-$(CONFIG_PINCTRL_UNIPHIER_NX1) += pinctrl-uniphier-nx1.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
new file mode 100644
index 000000000000..4fd3ec511d37
--- /dev/null
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-nx1.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2019 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-uniphier.h"
+
+static const struct pinctrl_pin_desc uniphier_nx1_pins[] = {
+ UNIPHIER_PINCTRL_PIN(0, "LPST", UNIPHIER_PIN_IECTRL_EXIST,
+ 0, UNIPHIER_PIN_DRV_3BIT,
+ 0, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(1, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 12, UNIPHIER_PIN_DRV_2BIT,
+ 1, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(2, "SDCMD", UNIPHIER_PIN_IECTRL_EXIST,
+ 13, UNIPHIER_PIN_DRV_2BIT,
+ 2, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(3, "SDDAT0", UNIPHIER_PIN_IECTRL_EXIST,
+ 14, UNIPHIER_PIN_DRV_2BIT,
+ 3, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(4, "SDDAT1", UNIPHIER_PIN_IECTRL_EXIST,
+ 15, UNIPHIER_PIN_DRV_2BIT,
+ 4, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(5, "SDDAT2", UNIPHIER_PIN_IECTRL_EXIST,
+ 16, UNIPHIER_PIN_DRV_2BIT,
+ 5, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(6, "SDDAT3", UNIPHIER_PIN_IECTRL_EXIST,
+ 17, UNIPHIER_PIN_DRV_2BIT,
+ 6, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(7, "SDCD", UNIPHIER_PIN_IECTRL_EXIST,
+ 1, UNIPHIER_PIN_DRV_3BIT,
+ 7, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(8, "SDWP", UNIPHIER_PIN_IECTRL_EXIST,
+ 2, UNIPHIER_PIN_DRV_3BIT,
+ 8, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(9, "SDVOLC", UNIPHIER_PIN_IECTRL_EXIST,
+ 3, UNIPHIER_PIN_DRV_3BIT,
+ 9, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(10, "XERST", UNIPHIER_PIN_IECTRL_EXIST,
+ 0, UNIPHIER_PIN_DRV_2BIT,
+ 10, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(11, "MDC", UNIPHIER_PIN_IECTRL_EXIST,
+ 18, UNIPHIER_PIN_DRV_2BIT,
+ 11, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(12, "MDIO", UNIPHIER_PIN_IECTRL_EXIST,
+ 19, UNIPHIER_PIN_DRV_2BIT,
+ 12, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(13, "MDIO_INTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 20, UNIPHIER_PIN_DRV_2BIT,
+ 13, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(14, "PHYRSTL", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(15, "RGMII_RXCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 22, UNIPHIER_PIN_DRV_2BIT,
+ 15, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(16, "RGMII_RXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 23, UNIPHIER_PIN_DRV_2BIT,
+ 16, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(17, "RGMII_RXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 24, UNIPHIER_PIN_DRV_2BIT,
+ 17, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(18, "RGMII_RXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 25, UNIPHIER_PIN_DRV_2BIT,
+ 18, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(19, "RGMII_RXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 26, UNIPHIER_PIN_DRV_2BIT,
+ 19, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(20, "RGMII_RXCTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 27, UNIPHIER_PIN_DRV_2BIT,
+ 20, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(21, "RGMII_TXCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 28, UNIPHIER_PIN_DRV_2BIT,
+ 21, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(22, "RGMII_TXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 29, UNIPHIER_PIN_DRV_2BIT,
+ 22, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(23, "RGMII_TXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 30, UNIPHIER_PIN_DRV_2BIT,
+ 23, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(24, "RGMII_TXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 31, UNIPHIER_PIN_DRV_2BIT,
+ 24, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(25, "RGMII_TXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 32, UNIPHIER_PIN_DRV_2BIT,
+ 25, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(26, "RGMII_TXCTL", UNIPHIER_PIN_IECTRL_EXIST,
+ 33, UNIPHIER_PIN_DRV_2BIT,
+ 26, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(27, "TXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 4, UNIPHIER_PIN_DRV_3BIT,
+ 27, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(28, "RXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 5, UNIPHIER_PIN_DRV_3BIT,
+ 28, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(29, "TXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 6, UNIPHIER_PIN_DRV_3BIT,
+ 29, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(30, "RXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 7, UNIPHIER_PIN_DRV_3BIT,
+ 30, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(31, "XRTS1", UNIPHIER_PIN_IECTRL_EXIST,
+ 8, UNIPHIER_PIN_DRV_3BIT,
+ 31, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(32, "XDTR1", UNIPHIER_PIN_IECTRL_EXIST,
+ 9, UNIPHIER_PIN_DRV_3BIT,
+ 32, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(33, "XCTS1", UNIPHIER_PIN_IECTRL_EXIST,
+ 10, UNIPHIER_PIN_DRV_3BIT,
+ 33, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(34, "XDSR1", UNIPHIER_PIN_IECTRL_EXIST,
+ 11, UNIPHIER_PIN_DRV_3BIT,
+ 34, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(35, "XDCD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 12, UNIPHIER_PIN_DRV_3BIT,
+ 35, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(36, "TXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 13, UNIPHIER_PIN_DRV_3BIT,
+ 36, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(37, "RXD2", UNIPHIER_PIN_IECTRL_EXIST,
+ 14, UNIPHIER_PIN_DRV_3BIT,
+ 37, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(38, "XRTS2", UNIPHIER_PIN_IECTRL_EXIST,
+ 15, UNIPHIER_PIN_DRV_3BIT,
+ 38, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(39, "XCTS2", UNIPHIER_PIN_IECTRL_EXIST,
+ 16, UNIPHIER_PIN_DRV_3BIT,
+ 39, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(40, "TXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 17, UNIPHIER_PIN_DRV_3BIT,
+ 40, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(41, "RXD3", UNIPHIER_PIN_IECTRL_EXIST,
+ 18, UNIPHIER_PIN_DRV_3BIT,
+ 41, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(42, "SPISYNC0", UNIPHIER_PIN_IECTRL_EXIST,
+ 19, UNIPHIER_PIN_DRV_3BIT,
+ 42, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(43, "SPISCLK0", UNIPHIER_PIN_IECTRL_EXIST,
+ 20, UNIPHIER_PIN_DRV_3BIT,
+ 43, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(44, "SPITXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 21, UNIPHIER_PIN_DRV_3BIT,
+ 44, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(45, "SPIRXD0", UNIPHIER_PIN_IECTRL_EXIST,
+ 22, UNIPHIER_PIN_DRV_3BIT,
+ 45, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(46, "SPISYNC1", UNIPHIER_PIN_IECTRL_EXIST,
+ 23, UNIPHIER_PIN_DRV_3BIT,
+ 46, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(47, "SPISCLK1", UNIPHIER_PIN_IECTRL_EXIST,
+ 24, UNIPHIER_PIN_DRV_3BIT,
+ 47, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(48, "SPITXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 25, UNIPHIER_PIN_DRV_3BIT,
+ 48, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(49, "SPIRXD1", UNIPHIER_PIN_IECTRL_EXIST,
+ 26, UNIPHIER_PIN_DRV_3BIT,
+ 49, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(50, "SDA0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(51, "SCL0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(52, "SDA1", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(53, "SCL1", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(54, "SDA2", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(55, "SCL2", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(56, "SDA3", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(57, "SCL3", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(58, "XIRQ0", UNIPHIER_PIN_IECTRL_EXIST,
+ 27, UNIPHIER_PIN_DRV_3BIT,
+ 58, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(59, "XIRQ1", UNIPHIER_PIN_IECTRL_EXIST,
+ 28, UNIPHIER_PIN_DRV_3BIT,
+ 59, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(60, "XIRQ2", UNIPHIER_PIN_IECTRL_EXIST,
+ 29, UNIPHIER_PIN_DRV_3BIT,
+ 60, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(61, "XIRQ3", UNIPHIER_PIN_IECTRL_EXIST,
+ 30, UNIPHIER_PIN_DRV_3BIT,
+ 61, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(62, "XIRQ4", UNIPHIER_PIN_IECTRL_EXIST,
+ 31, UNIPHIER_PIN_DRV_3BIT,
+ 62, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(63, "XIRQ5", UNIPHIER_PIN_IECTRL_EXIST,
+ 32, UNIPHIER_PIN_DRV_3BIT,
+ 63, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(64, "PORT00", UNIPHIER_PIN_IECTRL_EXIST,
+ 33, UNIPHIER_PIN_DRV_3BIT,
+ 64, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(65, "PORT01", UNIPHIER_PIN_IECTRL_EXIST,
+ 34, UNIPHIER_PIN_DRV_3BIT,
+ 65, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(66, "PORT02", UNIPHIER_PIN_IECTRL_EXIST,
+ 35, UNIPHIER_PIN_DRV_3BIT,
+ 66, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(67, "PORT03", UNIPHIER_PIN_IECTRL_EXIST,
+ 36, UNIPHIER_PIN_DRV_3BIT,
+ 67, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(68, "PORT04", UNIPHIER_PIN_IECTRL_EXIST,
+ 37, UNIPHIER_PIN_DRV_3BIT,
+ 68, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(69, "PORT05", UNIPHIER_PIN_IECTRL_EXIST,
+ 38, UNIPHIER_PIN_DRV_3BIT,
+ 69, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(70, "PORT06", UNIPHIER_PIN_IECTRL_EXIST,
+ 39, UNIPHIER_PIN_DRV_3BIT,
+ 70, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(71, "PORT07", UNIPHIER_PIN_IECTRL_EXIST,
+ 40, UNIPHIER_PIN_DRV_3BIT,
+ 71, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(72, "PORT10", UNIPHIER_PIN_IECTRL_EXIST,
+ 41, UNIPHIER_PIN_DRV_3BIT,
+ 72, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(73, "PORT11", UNIPHIER_PIN_IECTRL_EXIST,
+ 42, UNIPHIER_PIN_DRV_3BIT,
+ 73, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(74, "PORT12", UNIPHIER_PIN_IECTRL_EXIST,
+ 43, UNIPHIER_PIN_DRV_3BIT,
+ 74, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(75, "PORT13", UNIPHIER_PIN_IECTRL_EXIST,
+ 44, UNIPHIER_PIN_DRV_3BIT,
+ 75, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(76, "PORT14", UNIPHIER_PIN_IECTRL_EXIST,
+ 45, UNIPHIER_PIN_DRV_3BIT,
+ 76, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(77, "PORT15", UNIPHIER_PIN_IECTRL_EXIST,
+ 46, UNIPHIER_PIN_DRV_3BIT,
+ 77, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(78, "USBAVBUS", UNIPHIER_PIN_IECTRL_EXIST,
+ 47, UNIPHIER_PIN_DRV_3BIT,
+ 78, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(79, "USBAOD", UNIPHIER_PIN_IECTRL_EXIST,
+ 48, UNIPHIER_PIN_DRV_3BIT,
+ 79, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(80, "USBBVBUS", UNIPHIER_PIN_IECTRL_EXIST,
+ 49, UNIPHIER_PIN_DRV_3BIT,
+ 80, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(81, "USBBOD", UNIPHIER_PIN_IECTRL_EXIST,
+ 50, UNIPHIER_PIN_DRV_3BIT,
+ 81, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(82, "HTDDCSDA0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(83, "HTDDCSCL0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(84, "HTHPDI0", UNIPHIER_PIN_IECTRL_EXIST,
+ -1, UNIPHIER_PIN_DRV_FIXED4,
+ -1, UNIPHIER_PIN_PULL_NONE),
+ UNIPHIER_PINCTRL_PIN(85, "MMCCLK", UNIPHIER_PIN_IECTRL_EXIST,
+ 1, UNIPHIER_PIN_DRV_2BIT,
+ 85, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(86, "MMCCMD", UNIPHIER_PIN_IECTRL_EXIST,
+ 2, UNIPHIER_PIN_DRV_2BIT,
+ 86, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(87, "MMCDS", UNIPHIER_PIN_IECTRL_EXIST,
+ 3, UNIPHIER_PIN_DRV_2BIT,
+ 87, UNIPHIER_PIN_PULL_DOWN),
+ UNIPHIER_PINCTRL_PIN(88, "MMCDAT0", UNIPHIER_PIN_IECTRL_EXIST,
+ 4, UNIPHIER_PIN_DRV_2BIT,
+ 88, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(89, "MMCDAT1", UNIPHIER_PIN_IECTRL_EXIST,
+ 5, UNIPHIER_PIN_DRV_2BIT,
+ 89, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(90, "MMCDAT2", UNIPHIER_PIN_IECTRL_EXIST,
+ 6, UNIPHIER_PIN_DRV_2BIT,
+ 90, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(91, "MMCDAT3", UNIPHIER_PIN_IECTRL_EXIST,
+ 7, UNIPHIER_PIN_DRV_2BIT,
+ 91, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(92, "MMCDAT4", UNIPHIER_PIN_IECTRL_EXIST,
+ 8, UNIPHIER_PIN_DRV_2BIT,
+ 92, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(93, "MMCDAT5", UNIPHIER_PIN_IECTRL_EXIST,
+ 9, UNIPHIER_PIN_DRV_2BIT,
+ 93, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(94, "MMCDAT6", UNIPHIER_PIN_IECTRL_EXIST,
+ 10, UNIPHIER_PIN_DRV_2BIT,
+ 94, UNIPHIER_PIN_PULL_UP),
+ UNIPHIER_PINCTRL_PIN(95, "MMCDAT7", UNIPHIER_PIN_IECTRL_EXIST,
+ 11, UNIPHIER_PIN_DRV_2BIT,
+ 95, UNIPHIER_PIN_PULL_UP),
+};
+
+static const unsigned int emmc_pins[] = {85, 86, 87, 88, 89, 90, 91};
+static const int emmc_muxvals[] = {-1, -1, -1, -1, -1, -1, -1};
+static const unsigned int emmc_dat8_pins[] = {92, 93, 94, 95};
+static const int emmc_dat8_muxvals[] = {-1, -1, -1, -1};
+static const unsigned int ether_rgmii_pins[] = {11, 12, 13, 14, 15, 16, 17, 18,
+ 19, 20, 21, 22, 23, 24, 25, 26};
+static const int ether_rgmii_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0};
+static const unsigned int ether_rmii_pins[] = {11, 12, 13, 14, 15, 16, 17, 18,
+ 20, 22, 23, 26};
+static const int ether_rmii_muxvals[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1};
+static const unsigned int i2c0_pins[] = {50, 51};
+static const int i2c0_muxvals[] = {0, 0};
+static const unsigned int i2c1_pins[] = {52, 53};
+static const int i2c1_muxvals[] = {0, 0};
+static const unsigned int i2c2_pins[] = {54, 55};
+static const int i2c2_muxvals[] = {0, 0};
+static const unsigned int i2c3_pins[] = {56, 57};
+static const int i2c3_muxvals[] = {0, 0};
+static const unsigned int i2c4_pins[] = {72, 73};
+static const int i2c4_muxvals[] = {1, 1};
+static const unsigned int i2c5_pins[] = {74, 75};
+static const int i2c5_muxvals[] = {1, 1};
+static const unsigned int i2c6_pins[] = {82, 83};
+static const int i2c6_muxvals[] = {1, 1};
+static const unsigned int sd_pins[] = {1, 2, 3, 4, 5, 6, 7, 8, 9};
+static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0};
+static const unsigned spi0_pins[] = {42, 43, 44, 45};
+static const int spi0_muxvals[] = {0, 0, 0, 0};
+static const unsigned spi1_pins[] = {46, 47, 48, 49};
+static const int spi1_muxvals[] = {0, 0, 0, 0};
+static const unsigned int uart0_pins[] = {27, 28};
+static const int uart0_muxvals[] = {0, 0};
+static const unsigned int uart1_pins[] = {29, 30};
+static const int uart1_muxvals[] = {0, 0};
+static const unsigned int uart1_ctsrts_pins[] = {31, 33};
+static const int uart1_ctsrts_muxvals[] = {0, 0};
+static const unsigned int uart1_modem_pins[] = {32, 34, 35};
+static const int uart1_modem_muxvals[] = {0, 0, 0};
+static const unsigned int uart2_pins[] = {36, 37};
+static const int uart2_muxvals[] = {0, 0};
+static const unsigned int uart2_ctsrts_pins[] = {38, 39};
+static const int uart2_ctsrts_muxvals[] = {0, 0};
+static const unsigned int uart3_pins[] = {40, 41};
+static const int uart3_muxvals[] = {0, 0};
+static const unsigned int usb0_pins[] = {78, 79};
+static const int usb0_muxvals[] = {0, 0};
+static const unsigned int usb1_pins[] = {80, 81};
+static const int usb1_muxvals[] = {0, 0};
+static const unsigned int gpio_range0_pins[] = {
+ 64, 65, 66, 67, 68, 69, 70, 71, /* PORT0x */
+ 72, 73, 74, 75, 76, 77, 0, 1, /* PORT1x */
+ 2, 3, 4, 5, 6, 7, 8, 9, /* PORT2x */
+ 10, 78, 79, 80, 81, /* PORT30-34 */
+};
+static const unsigned int gpio_range1_pins[] = {
+ 11, 12, 13, /* PORT61-63 */
+};
+static const unsigned int gpio_range2_pins[] = {
+ 15, 16, 17, /* PORT65-67 */
+ 18, 19, 20, 21, 22, 23, 24, 25, /* PORT7x */
+ 26, 27, 28, 29, 30, 31, 32, 33, /* PORT8x */
+ 34, 35, 36, 37, 38, 39, 40, 41, /* PORT9x */
+ 42, 43, 44, 45, 46, 47, 48, 49, /* PORT10x */
+};
+static const unsigned int gpio_range3_pins[] = {
+ 58, 59, 60, 61, 62, 63, /* PORT12x */
+};
+static const unsigned int gpio_range4_pins[] = {
+ 58, 59, 60, 61, 62, 63, /* XIRQ0-5 */
+};
+
+static const struct uniphier_pinctrl_group uniphier_nx1_groups[] = {
+ UNIPHIER_PINCTRL_GROUP(emmc),
+ UNIPHIER_PINCTRL_GROUP(emmc_dat8),
+ UNIPHIER_PINCTRL_GROUP(ether_rgmii),
+ UNIPHIER_PINCTRL_GROUP(ether_rmii),
+ UNIPHIER_PINCTRL_GROUP(i2c0),
+ UNIPHIER_PINCTRL_GROUP(i2c1),
+ UNIPHIER_PINCTRL_GROUP(i2c2),
+ UNIPHIER_PINCTRL_GROUP(i2c3),
+ UNIPHIER_PINCTRL_GROUP(i2c4),
+ UNIPHIER_PINCTRL_GROUP(i2c5),
+ UNIPHIER_PINCTRL_GROUP(i2c6),
+ UNIPHIER_PINCTRL_GROUP(sd),
+ UNIPHIER_PINCTRL_GROUP(spi0),
+ UNIPHIER_PINCTRL_GROUP(spi1),
+ UNIPHIER_PINCTRL_GROUP(uart0),
+ UNIPHIER_PINCTRL_GROUP(uart1),
+ UNIPHIER_PINCTRL_GROUP(uart1_ctsrts),
+ UNIPHIER_PINCTRL_GROUP(uart1_modem),
+ UNIPHIER_PINCTRL_GROUP(uart2),
+ UNIPHIER_PINCTRL_GROUP(uart2_ctsrts),
+ UNIPHIER_PINCTRL_GROUP(uart3),
+ UNIPHIER_PINCTRL_GROUP(usb0),
+ UNIPHIER_PINCTRL_GROUP(usb1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range0),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range1),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range3),
+ UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range4),
+};
+
+static const char * const emmc_groups[] = {"emmc", "emmc_dat8"};
+static const char * const ether_rgmii_groups[] = {"ether_rgmii"};
+static const char * const ether_rmii_groups[] = {"ether_rmii"};
+static const char * const i2c0_groups[] = {"i2c0"};
+static const char * const i2c1_groups[] = {"i2c1"};
+static const char * const i2c2_groups[] = {"i2c2"};
+static const char * const i2c3_groups[] = {"i2c3"};
+static const char * const i2c4_groups[] = {"i2c4"};
+static const char * const i2c5_groups[] = {"i2c5"};
+static const char * const i2c6_groups[] = {"i2c6"};
+static const char * const sd_groups[] = {"sd"};
+static const char * const spi0_groups[] = {"spi0"};
+static const char * const spi1_groups[] = {"spi1"};
+static const char * const uart0_groups[] = {"uart0"};
+static const char * const uart1_groups[] = {"uart1", "uart1_ctsrts",
+ "uart1_modem"};
+static const char * const uart2_groups[] = {"uart2", "uart2_ctsrts"};
+static const char * const uart3_groups[] = {"uart3"};
+static const char * const usb0_groups[] = {"usb0"};
+static const char * const usb1_groups[] = {"usb1"};
+
+static const struct uniphier_pinmux_function uniphier_nx1_functions[] = {
+ UNIPHIER_PINMUX_FUNCTION(emmc),
+ UNIPHIER_PINMUX_FUNCTION(ether_rgmii),
+ UNIPHIER_PINMUX_FUNCTION(ether_rmii),
+ UNIPHIER_PINMUX_FUNCTION(i2c0),
+ UNIPHIER_PINMUX_FUNCTION(i2c1),
+ UNIPHIER_PINMUX_FUNCTION(i2c2),
+ UNIPHIER_PINMUX_FUNCTION(i2c3),
+ UNIPHIER_PINMUX_FUNCTION(i2c4),
+ UNIPHIER_PINMUX_FUNCTION(i2c5),
+ UNIPHIER_PINMUX_FUNCTION(i2c6),
+ UNIPHIER_PINMUX_FUNCTION(sd),
+ UNIPHIER_PINMUX_FUNCTION(spi0),
+ UNIPHIER_PINMUX_FUNCTION(spi1),
+ UNIPHIER_PINMUX_FUNCTION(uart0),
+ UNIPHIER_PINMUX_FUNCTION(uart1),
+ UNIPHIER_PINMUX_FUNCTION(uart2),
+ UNIPHIER_PINMUX_FUNCTION(uart3),
+ UNIPHIER_PINMUX_FUNCTION(usb0),
+ UNIPHIER_PINMUX_FUNCTION(usb1),
+};
+
+static int uniphier_nx1_get_gpio_muxval(unsigned int pin,
+ unsigned int gpio_offset)
+{
+ if (gpio_offset >= 120) /* XIRQx */
+ return 14;
+
+ return 15;
+}
+
+static const struct uniphier_pinctrl_socdata uniphier_nx1_pindata = {
+ .pins = uniphier_nx1_pins,
+ .npins = ARRAY_SIZE(uniphier_nx1_pins),
+ .groups = uniphier_nx1_groups,
+ .groups_count = ARRAY_SIZE(uniphier_nx1_groups),
+ .functions = uniphier_nx1_functions,
+ .functions_count = ARRAY_SIZE(uniphier_nx1_functions),
+ .get_gpio_muxval = uniphier_nx1_get_gpio_muxval,
+ .caps = UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL,
+};
+
+static int uniphier_nx1_pinctrl_probe(struct platform_device *pdev)
+{
+ return uniphier_pinctrl_probe(pdev, &uniphier_nx1_pindata);
+}
+
+static const struct of_device_id uniphier_nx1_pinctrl_match[] = {
+ { .compatible = "socionext,uniphier-nx1-pinctrl" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver uniphier_nx1_pinctrl_driver = {
+ .probe = uniphier_nx1_pinctrl_probe,
+ .driver = {
+ .name = "uniphier-nx1-pinctrl",
+ .of_match_table = uniphier_nx1_pinctrl_match,
+ .pm = &uniphier_pinctrl_pm_ops,
+ },
+};
+builtin_platform_driver(uniphier_nx1_pinctrl_driver);
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
2021-10-06 11:10 ` Kunihiko Hayashi
@ 2021-10-06 19:08 ` Rob Herring
-1 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2021-10-06 19:08 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Rob Herring, Linus Walleij, linux-arm-kernel, linux-gpio,
Masami Hiramatsu, devicetree, linux-kernel
On Wed, 06 Oct 2021 20:10:05 +0900, Kunihiko Hayashi wrote:
> Update pinctrl binding document for UniPhier NX1 SoC.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1537066
pinctrl: 'ain1', 'ain2', 'ainiec1', 'aout', 'aout1', 'aout2', 'aout3', 'aoutiec1', 'aoutiec2', 'emmc', 'ether-mii', 'ether-rgmii', 'ether-rmii', 'ether1-rgmii', 'ether1-rmii', 'i2c0', 'i2c1', 'i2c2', 'i2c3', 'i2c4', 'i2c5', 'i2c6', 'nand', 'nand2cs', 'pcie', 'sd', 'sd-uhs', 'sd1', 'spi0', 'spi1', 'spi2', 'spi3', 'system-bus', 'uart0', 'uart1', 'uart2', 'uart3', 'usb0', 'usb1', 'usb2', 'usb3' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/socionext/uniphier-ld11-global.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-global.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dt.yaml
arch/arm/boot/dts/uniphier-ld4-ref.dt.yaml
arch/arm/boot/dts/uniphier-ld6b-ref.dt.yaml
arch/arm/boot/dts/uniphier-pro4-ace.dt.yaml
arch/arm/boot/dts/uniphier-pro4-ref.dt.yaml
arch/arm/boot/dts/uniphier-pro4-sanji.dt.yaml
arch/arm/boot/dts/uniphier-pxs2-gentil.dt.yaml
arch/arm/boot/dts/uniphier-pxs2-vodka.dt.yaml
arch/arm/boot/dts/uniphier-sld8-ref.dt.yaml
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding
@ 2021-10-06 19:08 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2021-10-06 19:08 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Rob Herring, Linus Walleij, linux-arm-kernel, linux-gpio,
Masami Hiramatsu, devicetree, linux-kernel
On Wed, 06 Oct 2021 20:10:05 +0900, Kunihiko Hayashi wrote:
> Update pinctrl binding document for UniPhier NX1 SoC.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> .../devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1537066
pinctrl: 'ain1', 'ain2', 'ainiec1', 'aout', 'aout1', 'aout2', 'aout3', 'aoutiec1', 'aoutiec2', 'emmc', 'ether-mii', 'ether-rgmii', 'ether-rmii', 'ether1-rgmii', 'ether1-rmii', 'i2c0', 'i2c1', 'i2c2', 'i2c3', 'i2c4', 'i2c5', 'i2c6', 'nand', 'nand2cs', 'pcie', 'sd', 'sd-uhs', 'sd1', 'spi0', 'spi1', 'spi2', 'spi3', 'system-bus', 'uart0', 'uart1', 'uart2', 'uart3', 'usb0', 'usb1', 'usb2', 'usb3' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/socionext/uniphier-ld11-global.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-global.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dt.yaml
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dt.yaml
arch/arm/boot/dts/uniphier-ld4-ref.dt.yaml
arch/arm/boot/dts/uniphier-ld6b-ref.dt.yaml
arch/arm/boot/dts/uniphier-pro4-ace.dt.yaml
arch/arm/boot/dts/uniphier-pro4-ref.dt.yaml
arch/arm/boot/dts/uniphier-pro4-sanji.dt.yaml
arch/arm/boot/dts/uniphier-pxs2-gentil.dt.yaml
arch/arm/boot/dts/uniphier-pxs2-vodka.dt.yaml
arch/arm/boot/dts/uniphier-sld8-ref.dt.yaml
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
2021-10-06 11:10 ` Kunihiko Hayashi
@ 2021-10-13 0:14 ` Linus Walleij
-1 siblings, 0 replies; 14+ messages in thread
From: Linus Walleij @ 2021-10-13 0:14 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Rob Herring, Masami Hiramatsu, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel
On Wed, Oct 6, 2021 at 1:10 PM Kunihiko Hayashi
<hayashi.kunihiko@socionext.com> wrote:
> This series includes the patches to add audio pinmux settings for LD11/LD20/PXs3
> SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
> the same kinds of pinmux settings as the other UniPhier SoCs.
>
> ---
> Change since v1:
> - Remove non-existent groups "usb2" and "usb3" in NX1 patch
This v2 patch set applied.
Rob's checker is complaining on patch 2 but that patch just adds
a compatible so the warnings must be old? Please look into them
anyways.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
@ 2021-10-13 0:14 ` Linus Walleij
0 siblings, 0 replies; 14+ messages in thread
From: Linus Walleij @ 2021-10-13 0:14 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: Rob Herring, Masami Hiramatsu, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel
On Wed, Oct 6, 2021 at 1:10 PM Kunihiko Hayashi
<hayashi.kunihiko@socionext.com> wrote:
> This series includes the patches to add audio pinmux settings for LD11/LD20/PXs3
> SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
> the same kinds of pinmux settings as the other UniPhier SoCs.
>
> ---
> Change since v1:
> - Remove non-existent groups "usb2" and "usb3" in NX1 patch
This v2 patch set applied.
Rob's checker is complaining on patch 2 but that patch just adds
a compatible so the warnings must be old? Please look into them
anyways.
Yours,
Linus Walleij
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
2021-10-13 0:14 ` Linus Walleij
@ 2021-10-13 1:09 ` Kunihiko Hayashi
-1 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-13 1:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Masami Hiramatsu, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel
Hi Linus,
On 2021/10/13 9:14, Linus Walleij wrote:
> On Wed, Oct 6, 2021 at 1:10 PM Kunihiko Hayashi
> <hayashi.kunihiko@socionext.com> wrote:
>
>> This series includes the patches to add audio pinmux settings for
>> LD11/LD20/PXs3
>> SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
>> the same kinds of pinmux settings as the other UniPhier SoCs.
>>
>> ---
>> Change since v1:
>> - Remove non-existent groups "usb2" and "usb3" in NX1 patch
>
> This v2 patch set applied.
Thank you.
> Rob's checker is complaining on patch 2 but that patch just adds
> a compatible so the warnings must be old? Please look into them
> anyways.
Yes, the warnings are old. I think that there are some descriptions
in devicetree that do not fit the dt-bindings pattern.
I'll investigate and fix them.
Thank you,
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support
@ 2021-10-13 1:09 ` Kunihiko Hayashi
0 siblings, 0 replies; 14+ messages in thread
From: Kunihiko Hayashi @ 2021-10-13 1:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Masami Hiramatsu, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-kernel
Hi Linus,
On 2021/10/13 9:14, Linus Walleij wrote:
> On Wed, Oct 6, 2021 at 1:10 PM Kunihiko Hayashi
> <hayashi.kunihiko@socionext.com> wrote:
>
>> This series includes the patches to add audio pinmux settings for
>> LD11/LD20/PXs3
>> SoCs and basic pinmux settings for new UniPhier NX1 SoC. NX1 SoC also has
>> the same kinds of pinmux settings as the other UniPhier SoCs.
>>
>> ---
>> Change since v1:
>> - Remove non-existent groups "usb2" and "usb3" in NX1 patch
>
> This v2 patch set applied.
Thank you.
> Rob's checker is complaining on patch 2 but that patch just adds
> a compatible so the warnings must be old? Please look into them
> anyways.
Yes, the warnings are old. I think that there are some descriptions
in devicetree that do not fit the dt-bindings pattern.
I'll investigate and fix them.
Thank you,
---
Best Regards
Kunihiko Hayashi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2021-10-13 1:11 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-06 11:10 [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support Kunihiko Hayashi
2021-10-06 11:10 ` Kunihiko Hayashi
2021-10-06 11:10 ` [PATCH v2 1/3] pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCs Kunihiko Hayashi
2021-10-06 11:10 ` Kunihiko Hayashi
2021-10-06 11:10 ` [PATCH v2 2/3] dt-bindings: pinctrl: uniphier: Add NX1 pinctrl binding Kunihiko Hayashi
2021-10-06 11:10 ` Kunihiko Hayashi
2021-10-06 19:08 ` Rob Herring
2021-10-06 19:08 ` Rob Herring
2021-10-06 11:10 ` [PATCH v2 3/3] pinctrl: uniphier: Add UniPhier NX1 pinctrl driver Kunihiko Hayashi
2021-10-06 11:10 ` Kunihiko Hayashi
2021-10-13 0:14 ` [PATCH v2 0/3] pinctrl: uniphier: Introduce some features and NX1 support Linus Walleij
2021-10-13 0:14 ` Linus Walleij
2021-10-13 1:09 ` Kunihiko Hayashi
2021-10-13 1:09 ` Kunihiko Hayashi
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