* [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers
@ 2021-10-07 20:35 Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
` (18 more replies)
0 siblings, 19 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
This patchset adds a descriptor table for all modifiers used by i915,
which deduplicates the listing of supported modifiers during plane
initialization and during checking for a modifier support on a plane.
This also simplifies getting some modifier attributes like checking
if a plane is a CCS modifier. The motivation is to make it easier to
add and maintain new CCS modifier sets, which will be needed for at
least ADL-P and another upcoming platform.
Tested with igt/kms_plane,kms_ccs on CHV,HSW,TGL,ADLP.
The patches are also avaiable at:
https://github.com/ideak/linux/commits/modifier-descriptors
Imre Deak (11):
drm/i915: Add a table with a descriptor for all i915 modifiers
drm/i915: Move intel_get_format_info() to intel_fb.c
drm/i915: Add tiling attribute to the modifier descriptor
drm/i915: Simplify the modifier check for interlaced scanout support
drm/i915: Unexport is_semiplanar_uv_plane()
drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
drm/i915: Add a platform independent way to get the RC CCS CC plane
drm/i915: Handle CCS CC planes separately from CCS control planes
drm/i915: Add a platform independent way to check for CCS control
planes
drm/i915: Move is_ccs_modifier() to intel_fb.c
drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 150 +----
drivers/gpu/drm/i915/display/intel_display.h | 4 -
.../drm/i915/display/intel_display_types.h | 17 -
drivers/gpu/drm/i915/display/intel_fb.c | 536 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_fb.h | 25 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +-
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 165 +-----
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
12 files changed, 569 insertions(+), 388 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-07 21:10 ` Ville Syrjälä
` (2 more replies)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak
` (17 subsequent siblings)
18 siblings, 3 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 8 +
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 137 +-------------
drivers/gpu/drm/i915/i915_drv.h | 3 +
8 files changed, 218 insertions(+), 164 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f64..bcd44ff30ce5b 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB8888,
};
-static const u64 cursor_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
@@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- return modifier == DRM_FORMAT_MOD_LINEAR &&
- format == DRM_FORMAT_ARGB8888;
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
+ return false;
+
+ return format == DRM_FORMAT_ARGB8888;
}
static int
@@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
{
struct intel_plane *cursor;
int ret, zpos;
+ u64 *modifiers;
cursor = intel_plane_alloc();
if (IS_ERR(cursor))
@@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
cursor->cursor.size = ~0;
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
+
ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
0, &intel_cursor_plane_funcs,
intel_cursor_formats,
ARRAY_SIZE(intel_cursor_formats),
- cursor_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_CURSOR,
"cursor %c", pipe_name(pipe));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 21ce8bccc645a..bb53b01f07aee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1336,7 +1336,6 @@ struct intel_plane {
enum plane_id id;
enum pipe pipe;
bool has_fbc;
- bool has_ccs;
bool need_async_flip_disable_wa;
u32 frontbuffer_bit;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index fa1f375e696bf..aefae988b620b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -13,6 +13,184 @@
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
+const struct intel_modifier_desc {
+ u64 id;
+ u64 display_versions;
+
+ struct {
+#define INTEL_CCS_RC BIT(0)
+#define INTEL_CCS_RC_CC BIT(1)
+#define INTEL_CCS_MC BIT(2)
+
+#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
+ u8 type:3;
+ } ccs;
+} intel_modifiers[] = {
+ {
+ .id = DRM_FORMAT_MOD_LINEAR,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ },
+ {
+ .id = I915_FORMAT_MOD_X_TILED,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 13),
+ },
+ {
+ .id = I915_FORMAT_MOD_Yf_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_CCS,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Yf_TILED_CCS,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_RC_CC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_MC,
+ },
+};
+
+static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
+{
+ return md->ccs.type & ccs_type;
+}
+
+static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ if (plane_id == PLANE_CURSOR)
+ return false;
+
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ if (DISPLAY_VER(i915) >= 11)
+ return true;
+
+ if (IS_GEMINILAKE(i915))
+ return pipe != PIPE_C;
+
+ return pipe != PIPE_C &&
+ (plane_id == PLANE_PRIMARY ||
+ plane_id == PLANE_SPRITE0);
+}
+
+static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
+ enum plane_id plane_id)
+{
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
+ IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+ return false;
+
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ return plane_id < PLANE_SPRITE4;
+}
+
+static bool plane_has_modifier(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id,
+ const struct intel_modifier_desc *md)
+{
+ if (!(DISPLAY_VER_BIT(DISPLAY_VER(i915)) & md->display_versions))
+ return false;
+
+ if (plane_id == PLANE_CURSOR && md->id != DRM_FORMAT_MOD_LINEAR)
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) &&
+ !skl_plane_has_rc_ccs(i915, pipe, plane_id))
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_MC) &&
+ !gen12_plane_has_mc_ccs(i915, plane_id))
+ return false;
+
+ return true;
+}
+
+/**
+ * intel_fb_plane_get_modifiers: Get the modifiers supported by the given pipe and plane
+ * @i915: i915 device instance
+ * @pipe: pipe to check the modifier support for
+ * @plane_id: plane to check the modifier support for
+ *
+ * Returns:
+ * Returns the list of modifiers supported by the @pipe / @plane_id
+ * combination. The caller should free the returned buffer.
+ */
+u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ u64 *list, *p;
+ int count = 1; /* +1 for invalid modifier terminator */
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
+ if (plane_has_modifier(i915, pipe, plane_id, &intel_modifiers[i]))
+ count++;
+ }
+
+ list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
+ if (drm_WARN_ON(&i915->drm, !list))
+ return NULL;
+
+ p = list;
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
+ if (plane_has_modifier(i915, pipe, plane_id, &intel_modifiers[i]))
+ *p++ = intel_modifiers[i].id;
+ }
+ *p++ = DRM_FORMAT_MOD_INVALID;
+
+ return list;
+}
+
+/**
+ * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
+ * @plane: Plane to check the modifier support for
+ * @modifier: The modifier to check the support for
+ *
+ * Returns:
+ * %true if the @modifier is supported on @plane.
+ */
+bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
+{
+ int i;
+
+ for (i = 0; i < plane->base.modifier_count; i++)
+ if (plane->base.modifiers[i] == modifier)
+ return true;
+
+ return false;
+}
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 1cbdd84502bdd..e2845fdda4312 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -8,6 +8,9 @@
#include <linux/types.h>
+enum pipe;
+enum plane_id;
+
struct drm_device;
struct drm_file;
struct drm_framebuffer;
@@ -16,6 +19,7 @@ struct drm_i915_private;
struct drm_mode_fb_cmd2;
struct intel_fb_view;
struct intel_framebuffer;
+struct intel_plane;
struct intel_plane_state;
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
@@ -23,6 +27,10 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
+u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id);
+bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 08116f41da26a..722f73a970041 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -45,6 +45,7 @@
#include "intel_atomic_plane.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_frontbuffer.h"
#include "intel_sprite.h"
#include "i9xx_plane.h"
@@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const u64 i9xx_plane_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static const u32 snb_plane_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
@@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = {
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
formats = vlv_plane_formats;
num_formats = ARRAY_SIZE(vlv_plane_formats);
}
- modifiers = i9xx_plane_format_modifiers;
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
@@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
- modifiers = i9xx_plane_format_modifiers;
plane_funcs = &snb_sprite_funcs;
} else {
@@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->max_stride = g4x_sprite_max_stride;
plane->min_cdclk = g4x_sprite_min_cdclk;
- modifiers = i9xx_plane_format_modifiers;
if (IS_SANDYBRIDGE(dev_priv)) {
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->id = PLANE_SPRITE0 + sprite;
plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, plane->id);
+
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
DRM_PLANE_TYPE_OVERLAY,
"sprite %c", sprite_name(pipe, sprite));
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 37eabeff8197f..c2e94118566b6 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -4,6 +4,7 @@
*/
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a0e53a3b267aa..cebd688ab1a22 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU16161616,
};
-static const u64 skl_plane_format_modifiers_noccs[] = {
- I915_FORMAT_MOD_Yf_TILED,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 skl_plane_format_modifiers_ccs[] = {
- I915_FORMAT_MOD_Yf_TILED_CCS,
- I915_FORMAT_MOD_Y_TILED_CCS,
- I915_FORMAT_MOD_Yf_TILED,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
- I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 adlp_step_a_plane_format_modifiers[] = {
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -1870,42 +1826,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
-static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum plane_id plane_id)
-{
- if (plane_id == PLANE_CURSOR)
- return false;
-
- if (DISPLAY_VER(dev_priv) >= 11)
- return true;
-
- if (IS_GEMINILAKE(dev_priv))
- return pipe != PIPE_C;
-
- return pipe != PIPE_C &&
- (plane_id == PLANE_PRIMARY ||
- plane_id == PLANE_SPRITE0);
-}
-
static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
struct intel_plane *plane = to_intel_plane(_plane);
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Yf_TILED:
- break;
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (!plane->has_ccs)
- return false;
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(plane, modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1953,45 +1880,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
-static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
- enum plane_id plane_id)
-{
- /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
- return false;
-
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return false;
-
- return plane_id < PLANE_SPRITE4;
-}
-
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- struct drm_i915_private *dev_priv = to_i915(_plane->dev);
struct intel_plane *plane = to_intel_plane(_plane);
- switch (modifier) {
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
- return false;
- fallthrough;
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- break;
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return false;
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(plane, modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -2039,18 +1934,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
}
}
-static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
- enum plane_id plane_id)
-{
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return adlp_step_a_plane_format_modifiers;
- else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
- return gen12_plane_format_modifiers_mc_ccs;
- else
- return gen12_plane_format_modifiers_rc_ccs;
-}
-
static const struct drm_plane_funcs skl_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2159,29 +2042,27 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
- if (DISPLAY_VER(dev_priv) >= 12) {
- modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
+ if (DISPLAY_VER(dev_priv) >= 12)
plane_funcs = &gen12_plane_funcs;
- } else {
- if (plane->has_ccs)
- modifiers = skl_plane_format_modifiers_ccs;
- else
- modifiers = skl_plane_format_modifiers_noccs;
+ else
plane_funcs = &skl_plane_funcs;
- }
if (plane_id == PLANE_PRIMARY)
plane_type = DRM_PLANE_TYPE_PRIMARY;
else
plane_type = DRM_PLANE_TYPE_OVERLAY;
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, plane_id);
+
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
plane_type,
"plane %d%c", plane_id + 1,
pipe_name(pipe));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f4..a92228c922a54 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
+#define DISPLAY_VER_BIT(d) BIT_ULL(d)
+#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
+#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak
` (16 subsequent siblings)
18 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +---------------
drivers/gpu/drm/i915/display/intel_fb.c | 155 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 159 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbba..90802d16fbf91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P012, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P016, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
-};
-
-/*
- * Same as gen12_ccs_formats[] above, but with additional surface used
- * to pass Clear Color information in plane 2 with 64 bits of data.
- */
-static const struct drm_format_info gen12_ccs_cc_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
-};
-
-static const struct drm_format_info *
-lookup_format_info(const struct drm_format_info formats[],
- int num_formats, u32 format)
-{
- int i;
-
- for (i = 0; i < num_formats; i++) {
- if (formats[i].format == format)
- return &formats[i];
- }
-
- return NULL;
-}
-
-static const struct drm_format_info *
-intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
-{
- switch (cmd->modifier[0]) {
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(skl_ccs_formats,
- ARRAY_SIZE(skl_ccs_formats),
- cmd->pixel_format);
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return lookup_format_info(gen12_ccs_formats,
- ARRAY_SIZE(gen12_ccs_formats),
- cmd->pixel_format);
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- return lookup_format_info(gen12_ccs_cc_formats,
- ARRAY_SIZE(gen12_ccs_cc_formats),
- cmd->pixel_format);
- default:
- return NULL;
- }
-}
-
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
@@ -11270,7 +11140,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
static const struct drm_mode_config_funcs intel_mode_funcs = {
.fb_create = intel_user_framebuffer_create,
- .get_format_info = intel_get_format_info,
+ .get_format_info = intel_fb_get_format_info,
.output_poll_changed = intel_fbdev_output_poll_changed,
.mode_valid = intel_mode_valid,
.atomic_check = intel_atomic_check,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index aefae988b620b..2543232580885 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -13,9 +13,108 @@
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
+/*
+ * From the Sky Lake PRM:
+ * "The Color Control Surface (CCS) contains the compression status of
+ * the cache-line pairs. The compression state of the cache-line pair
+ * is specified by 2 bits in the CCS. Each CCS cache-line represents
+ * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
+ * cache-line-pairs. CCS is always Y tiled."
+ *
+ * Since cache line pairs refers to horizontally adjacent cache lines,
+ * each cache line in the CCS corresponds to an area of 32x16 cache
+ * lines on the main surface. Since each pixel is 4 bytes, this gives
+ * us a ratio of one byte in the CCS for each 8x16 pixels in the
+ * main surface.
+ */
+static const struct drm_format_info skl_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+};
+
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_YVYU, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_UYVY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_VYUY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P010, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+};
+
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
+#define FORMAT_OVERRIDE(format_list) \
+ .formats = format_list, \
+ .format_count = ARRAY_SIZE(format_list)
+
const struct intel_modifier_desc {
u64 id;
u64 display_versions;
+ const struct drm_format_info *formats;
+ int format_count;
struct {
#define INTEL_CCS_RC BIT(0)
@@ -47,33 +146,89 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(skl_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Yf_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(skl_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(gen12_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_RC_CC,
+
+ FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_MC,
+
+ FORMAT_OVERRIDE(gen12_ccs_formats),
},
};
+static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
+ if (intel_modifiers[i].id == modifier)
+ return &intel_modifiers[i];
+
+ MISSING_CASE(modifier);
+
+ return &intel_modifiers[0];
+}
+
+static const struct drm_format_info *
+lookup_format_info(const struct drm_format_info formats[],
+ int num_formats, u32 format)
+{
+ int i;
+
+ for (i = 0; i < num_formats; i++) {
+ if (formats[i].format == format)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+/**
+ * intel_fb_get_format_info: Get a modifier specific format information
+ * @cmd: FB add command structure
+ *
+ * Returns:
+ * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
+ * or %NULL if the modifier doesn't override the format.
+ */
+const struct drm_format_info *
+intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(cmd->modifier[0]);
+
+ if (!md->formats)
+ return NULL;
+
+ return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
+}
+
static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
{
return md->ccs.type & ccs_type;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index e2845fdda4312..67c20451ae63f 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -31,6 +31,9 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
+const struct drm_format_info *
+intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:18 ` [Intel-gfx] [PATCH " Ville Syrjälä
2021-10-07 20:35 ` [Intel-gfx] [PATCH 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak
` (15 subsequent siblings)
18 siblings, 2 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 2543232580885..ef3cd375c9942 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -115,6 +115,7 @@ const struct intel_modifier_desc {
u64 display_versions;
const struct drm_format_info *formats;
int format_count;
+ u8 tiling;
struct {
#define INTEL_CCS_RC BIT(0)
@@ -132,10 +133,12 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_X_TILED,
.display_versions = DISPLAY_VER_MASK_ALL,
+ .tiling = I915_TILING_X,
},
{
.id = I915_FORMAT_MOD_Y_TILED,
.display_versions = DISPLAY_VER_MASK(9, 13),
+ .tiling = I915_TILING_Y,
},
{
.id = I915_FORMAT_MOD_Yf_TILED,
@@ -144,6 +147,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -160,6 +164,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -168,6 +173,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -176,6 +182,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -556,18 +563,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 04/11] drm/i915: Simplify the modifier check for interlaced scanout support
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (2 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak
` (14 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Checking the modifiers that support interlacing makes the condition
simpler and avoids us having to add new modifiers to the list (presuming
all/most of the new modifiers won't support interlacing).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index cebd688ab1a22..4f0dbb00ea28c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1240,13 +1240,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
/* Y-tiling is not supported in IF-ID Interlace mode */
if (crtc_state->hw.enable &&
crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
- (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) {
+ fb->modifier != DRM_FORMAT_MOD_LINEAR &&
+ fb->modifier != I915_FORMAT_MOD_X_TILED) {
drm_dbg_kms(&dev_priv->drm,
"Y/Yf tiling not supported in IF-ID mode\n");
return -EINVAL;
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane()
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (3 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak
` (13 subsequent siblings)
18 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
This function is only used by intel_fb.c, so unexport it.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index ef3cd375c9942..19aa99375502a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -372,7 +372,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
plane == 2;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 67c20451ae63f..a198914c0088b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -25,7 +25,6 @@ struct intel_plane_state;
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (4 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak
` (12 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Move intel_format_info_is_yuv_semiplanar() to intel_fb.c . The number of
planes for YUV semiplanar formats using CCS modifiers will change on
future platforms. We can use the modifier descriptors to simplify
getting the plane numbers for all modifiers, prepare for that here.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 8 -----
drivers/gpu/drm/i915/display/intel_display.h | 4 ---
drivers/gpu/drm/i915/display/intel_fb.c | 30 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 4 +++
drivers/gpu/drm/i915/intel_pm.c | 1 +
6 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 47234d8985490..0eb7323717d30 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_pm.h"
#include "intel_sprite.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 90802d16fbf91..8043a9fd665a5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -821,14 +821,6 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
intel_wait_for_pipe_off(old_crtc_state);
}
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier)
-{
- return info->is_yuv &&
- info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
-}
-
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
{
unsigned int size = 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 3028072c2cf35..84ae8b555ea0f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -619,10 +619,6 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state);
-bool
-intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
- u64 modifier);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
struct intel_encoder *
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 19aa99375502a..f0d8c848b23e1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -353,6 +353,36 @@ bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
return false;
}
+static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
+ const struct drm_format_info *info)
+{
+ int yuv_planes;
+
+ if (!info->is_yuv)
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_ANY))
+ yuv_planes = 4;
+ else
+ yuv_planes = 2;
+
+ return info->num_planes == yuv_planes;
+}
+
+/**
+ * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
+ * @info: format to check
+ * @modifier: modifier used with the format
+ *
+ * Returns:
+ * %true if @info / @modifier is YUV semiplanar.
+ */
+bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+ u64 modifier)
+{
+ return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
+}
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index a198914c0088b..d9693fc767c54 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -33,6 +33,10 @@ bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
const struct drm_format_info *
intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+bool
+intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
+ u64 modifier);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8dbf8ec0d8905..bafcac58ac096 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -37,6 +37,7 @@
#include "display/intel_bw.h"
#include "display/intel_de.h"
#include "display/intel_display_types.h"
+#include "display/intel_fb.h"
#include "display/intel_fbc.h"
#include "display/intel_sprite.h"
#include "display/skl_universal_plane.h"
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (5 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 08/11] drm/i915: Handle CCS CC planes separately from CCS control planes Imre Deak
` (11 subsequent siblings)
18 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
On future platforms the index of the color-clear plane will change from
the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve
the index independently of the platform/modifier.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++---
drivers/gpu/drm/i915/display/intel_fb.c | 25 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8043a9fd665a5..bfb9120cb31ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10031,10 +10031,14 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct drm_framebuffer *fb = plane_state->hw.fb;
+ int cc_plane;
int ret;
- if (!fb ||
- fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (!fb)
+ continue;
+
+ cc_plane = intel_fb_rc_ccs_cc_plane(fb);
+ if (cc_plane < 0)
continue;
/*
@@ -10051,7 +10055,7 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
* GPU write on it.
*/
ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
- fb->offsets[2] + 16,
+ fb->offsets[cc_plane] + 16,
&plane_state->ccval,
sizeof(plane_state->ccval));
/* The above could only fail if the FB obj has an unexpected backing store type. */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index f0d8c848b23e1..f18fab9c3b941 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -124,6 +124,7 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
+ u8 cc_planes:3;
} ccs;
} intel_modifiers[] = {
{
@@ -176,6 +177,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
@@ -396,10 +398,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+/**
+ * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
+ * @fb: Framebuffer
+ *
+ * Returns:
+ * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
+ * framebuffer using a render compression/color clear modifier.
+ */
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ if (!md->ccs.cc_planes)
+ return -1;
+
+ drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
+
+ return ilog2((int)md->ccs.cc_planes);
+}
+
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
- return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
- plane == 2;
+ return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index d9693fc767c54..5affcc834e045 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -26,6 +26,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
+
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 08/11] drm/i915: Handle CCS CC planes separately from CCS control planes
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (6 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for " Imre Deak
` (10 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
CCS CC planes are quite different from CCS control planes, even though
we regard the CC planes as a linear buffer having a 64 byte stride.
Thus it's clearer to check for either CCS plane types explicitly when we
need to handle them; add the required CCS CC planes check here, while
the next patch will change all is_ccs_plane()/is_gen12_ccs_plane()
checks to consider only the CCS control planes.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index f18fab9c3b941..e8fe198b1b6a1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -432,7 +432,8 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
- is_gen12_ccs_plane(fb, color_plane);
+ is_gen12_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane);
}
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
@@ -525,7 +526,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (is_ccs_plane(fb, color_plane) ||
+ is_gen12_ccs_cc_plane(fb, color_plane))
return 64;
fallthrough;
case I915_FORMAT_MOD_Y_TILED:
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (7 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 08/11] drm/i915: Handle CCS CC planes separately from CCS control planes Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:27 ` [Intel-gfx] [PATCH " Ville Syrjälä
2021-10-07 20:35 ` [Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak
` (9 subsequent siblings)
18 siblings, 2 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Future platforms change the location of CCS control planes in CCS
framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in control planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 73 ++++++++++++++-----
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c | 3 +-
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bb53b01f07aee..b4b6a31caf4e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index e8fe198b1b6a1..392f89e659eb6 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -125,6 +125,8 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_ctrl_planes:4;
+ u8 planar_ctrl_planes:4;
} ccs;
} intel_modifiers[] = {
{
@@ -151,6 +153,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -159,6 +162,7 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -168,6 +172,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -177,6 +182,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_ctrl_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -187,6 +193,8 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_ctrl_planes = BIT(1),
+ .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -385,17 +393,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
+ const struct drm_format_info *format)
{
- if (!is_ccs_modifier(fb->modifier))
- return false;
+ if (format_is_yuv_semiplanar(md, format))
+ return md->ccs.planar_ctrl_planes;
+ else
+ return md->ccs.packed_ctrl_planes;
+}
+
+/**
+ * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a CCS control plane.
+ */
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
- return plane >= fb->format->num_planes / 2;
+ return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+/**
+ * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer color plane is a GEN12 CCS control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a GEN12 CCS control plane.
+ */
+static bool intel_fb_is_gen12_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
{
- return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ return md->display_versions & (DISPLAY_VER_MASK(12, 13)) &&
+ ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
/**
@@ -418,7 +453,7 @@ int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
return ilog2((int)md->ccs.cc_planes);
}
-bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
@@ -432,7 +467,7 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
- is_gen12_ccs_plane(fb, color_plane) ||
+ intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane) ||
is_gen12_ccs_cc_plane(fb, color_plane);
}
@@ -520,13 +555,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_Y_TILED_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 128;
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_ccs_plane(fb, color_plane) ||
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane) ||
is_gen12_ccs_cc_plane(fb, color_plane))
return 64;
fallthrough;
@@ -536,7 +571,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 128;
fallthrough;
case I915_FORMAT_MOD_Yf_TILED:
@@ -592,7 +627,7 @@ static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_pl
{
intel_tile_dims(fb, color_plane, tile_width, tile_height);
- if (is_gen12_ccs_plane(fb, color_plane))
+ if (intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane))
*tile_height = 1;
}
@@ -653,7 +688,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 512 * 4096;
/* AUX_DIST needs only 4K alignment */
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 4096;
if (is_semiplanar_uv_plane(fb, color_plane)) {
@@ -712,7 +747,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
* TODO: Deduct the subsampling from the char block for all CCS
* formats and planes.
*/
- if (!is_gen12_ccs_plane(fb, color_plane)) {
+ if (!intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane)) {
*hsub = fb->format->hsub;
*vsub = fb->format->vsub;
@@ -740,7 +775,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
{
struct drm_i915_private *i915 = to_i915(fb->base.dev);
- int main_plane = is_ccs_plane(&fb->base, color_plane) ?
+ int main_plane = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ?
skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
unsigned int main_width = fb->base.width;
unsigned int main_height = fb->base.height;
@@ -753,7 +788,7 @@ static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_pl
* stride in the allocated FB object may not be power-of-two
* sized, in which case it is auto-padded to the POT size.
*/
- if (IS_ALDERLAKE_P(i915) && is_ccs_plane(&fb->base, color_plane))
+ if (IS_ALDERLAKE_P(i915) && intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane))
main_width = gen12_aligned_scanout_stride(fb, 0) /
fb->base.format->cpp[0];
@@ -992,7 +1027,7 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane
int ccs_x, ccs_y;
int main_x, main_y;
- if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
+ if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
return 0;
/*
@@ -1196,7 +1231,7 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
unsigned int pitch_tiles)
{
if (intel_fb_needs_pot_stride_remap(fb)) {
- unsigned int min_stride = is_ccs_plane(&fb->base, color_plane) ? 2 : 8;
+ unsigned int min_stride = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ? 2 : 8;
/*
* ADL_P, the only platform needing a POT stride has a minimum
* of 8 main surface and 2 CCS AUX stride tiles.
@@ -1812,7 +1847,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
+ if (intel_fb_is_gen12_ccs_ctrl_plane(fb, i)) {
int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
if (fb->pitches[i] != ccs_aux_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 5affcc834e045..baa5b538b4be7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -22,10 +22,7 @@ struct intel_framebuffer;
struct intel_plane;
struct intel_plane_state;
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
-bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4f0dbb00ea28c..95900b631aa7c 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1607,8 +1607,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int hsub, vsub;
int x, y;
- if (!is_ccs_plane(fb, ccs_plane) ||
- is_gen12_ccs_cc_plane(fb, ccs_plane))
+ if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
continue;
intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (8 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for " Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak
` (8 subsequent siblings)
18 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Move the function to intel_fb.c and rename it adding the intel_fb_
prefix following the naming of exported functions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 9 ------
drivers/gpu/drm/i915/display/intel_fb.c | 29 ++++++++++++++-----
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 12 ++++----
4 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b4b6a31caf4e3..f38b70ef6afaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2041,13 +2041,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 392f89e659eb6..b68bda0845c56 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -251,6 +251,19 @@ static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_ty
return md->ccs.type & ccs_type;
}
+/**
+ * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier.
+ */
+bool intel_fb_is_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
+}
+
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
@@ -473,7 +486,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
(main_plane && main_plane >= fb->format->num_planes / 2));
return fb->format->num_planes / 2 + main_plane;
@@ -481,7 +494,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
if (is_gen12_ccs_cc_plane(fb, ccs_plane))
@@ -526,7 +539,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
{
struct drm_i915_private *i915 = to_i915(fb->dev);
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
@@ -1090,7 +1103,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
* The new CCS hash mode isn't compatible with remapping as
* the virtual address of the pages affects the compressed data.
*/
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return false;
/* Linear needs a page aligned stride for remapping */
@@ -1497,7 +1510,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier));
+ drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
drm_rect_translate(&plane_state->uapi.src,
@@ -1560,7 +1573,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
intel_modifier_uses_dpt(dev_priv, modifier))
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
else if (DISPLAY_VER(dev_priv) >= 7)
@@ -1585,14 +1598,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* we need the stride to be page aligned.
*/
if (fb->pitches[color_plane] > max_stride &&
- !is_ccs_modifier(fb->modifier))
+ !intel_fb_is_ccs_modifier(fb->modifier))
return intel_tile_size(dev_priv);
else
return 64;
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
/*
* On ADL-P the stride must be either 8 tiles or a stride
* that is aligned to 16 tiles, required by the 16 tiles =
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index baa5b538b4be7..af8097699dac5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -22,6 +22,8 @@ struct intel_framebuffer;
struct intel_plane;
struct intel_plane_state;
+bool intel_fb_is_ccs_modifier(u64 modifier);
+
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 95900b631aa7c..d29ad180f8477 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1188,7 +1188,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return 0;
if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
- is_ccs_modifier(fb->modifier)) {
+ intel_fb_is_ccs_modifier(fb->modifier)) {
drm_dbg_kms(&dev_priv->drm,
"RC support only with 0/180 degree rotation (%x)\n",
rotation);
@@ -1487,7 +1487,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* CCS AUX surface doesn't have its own x/y offsets, we must make sure
* they match with the main surface x/y offsets.
*/
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
while (!skl_check_main_ccs_coordinates(plane_state, x, y,
offset, aux_plane)) {
if (offset == 0)
@@ -1551,7 +1551,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
offset = intel_plane_compute_aligned_offset(&x, &y,
plane_state, uv_plane);
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
int ccs_plane = main_to_ccs_plane(fb, uv_plane);
u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
u32 alignment = intel_surf_alignment(fb, uv_plane);
@@ -1649,7 +1649,7 @@ static int skl_check_plane_surface(struct intel_plane_state *plane_state)
* Handle the AUX surface first since the main surface setup depends on
* it.
*/
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
ret = skl_check_ccs_aux_surface(plane_state);
if (ret)
return ret;
@@ -1833,7 +1833,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
- if (is_ccs_modifier(modifier))
+ if (intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
@@ -1887,7 +1887,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
- if (is_ccs_modifier(modifier))
+ if (intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_YUYV:
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (9 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak
@ 2021-10-07 20:35 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 21:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers Patchwork
` (7 subsequent siblings)
18 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 20:35 UTC (permalink / raw)
To: intel-gfx
Instead of open-coding the checks add functions for this, simplifying
the handling of CCS modifiers on future platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 4 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index b68bda0845c56..e8d37f0678741 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -264,6 +264,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
}
+/**
+ * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render with color clear modifier.
+ */
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC);
+}
+
+/**
+ * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a media compression modifier.
+ */
+bool intel_fb_is_mc_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC);
+}
+
static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index af8097699dac5..cb5bc6304011a 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -23,6 +23,8 @@ struct intel_plane;
struct intel_plane_state;
bool intel_fb_is_ccs_modifier(u64 modifier);
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
+bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d29ad180f8477..9cff6cc2bdf4f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1067,7 +1067,7 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
intel_uncore_write64_fw(&dev_priv->uncore,
PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
@@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
- if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ if (intel_fb_is_mc_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
@ 2021-10-07 21:10 ` Ville Syrjälä
2021-10-07 21:26 ` Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-14 14:07 ` [Intel-gfx] [PATCH " Jani Nikula
2 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-07 21:10 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> Add a table describing all the framebuffer modifiers used by i915 at one
> place. This has the benefit of deduplicating the listing of supported
> modifiers for each platform and checking the support of these modifiers
> on a given plane. This also simplifies in a similar way getting some
> attribute for a modifier, for instance checking if the modifier is a
> CCS modifier type.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> .../drm/i915/display/intel_display_types.h | 1 -
> drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 8 files changed, 218 insertions(+), 164 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index f6dcb5aa63f64..bcd44ff30ce5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> };
>
> -static const u64 cursor_format_modifiers[] = {
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR &&
> - format == DRM_FORMAT_ARGB8888;
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> + return false;
> +
> + return format == DRM_FORMAT_ARGB8888;
> }
>
> static int
> @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> {
> struct intel_plane *cursor;
> int ret, zpos;
> + u64 *modifiers;
>
> cursor = intel_plane_alloc();
> if (IS_ERR(cursor))
> @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> cursor->cursor.size = ~0;
>
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> +
> ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> 0, &intel_cursor_plane_funcs,
> intel_cursor_formats,
> ARRAY_SIZE(intel_cursor_formats),
> - cursor_format_modifiers,
> + modifiers,
> DRM_PLANE_TYPE_CURSOR,
> "cursor %c", pipe_name(pipe));
> +
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 21ce8bccc645a..bb53b01f07aee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1336,7 +1336,6 @@ struct intel_plane {
> enum plane_id id;
> enum pipe pipe;
> bool has_fbc;
> - bool has_ccs;
> bool need_async_flip_disable_wa;
> u32 frontbuffer_bit;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index fa1f375e696bf..aefae988b620b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -13,6 +13,184 @@
>
> #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
>
> +const struct intel_modifier_desc {
> + u64 id;
> + u64 display_versions;
> +
> + struct {
> +#define INTEL_CCS_RC BIT(0)
> +#define INTEL_CCS_RC_CC BIT(1)
> +#define INTEL_CCS_MC BIT(2)
> +
> +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> + u8 type:3;
> + } ccs;
> +} intel_modifiers[] = {
> + {
> + .id = DRM_FORMAT_MOD_LINEAR,
> + .display_versions = DISPLAY_VER_MASK_ALL,
> + },
> + {
> + .id = I915_FORMAT_MOD_X_TILED,
> + .display_versions = DISPLAY_VER_MASK_ALL,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED,
> + .display_versions = DISPLAY_VER_MASK(9, 13),
> + },
> + {
> + .id = I915_FORMAT_MOD_Yf_TILED,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_RC_CC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_MC,
> + },
> +};
> +
> +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> +{
> + return md->ccs.type & ccs_type;
> +}
> +
> +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> + if (plane_id == PLANE_CURSOR)
> + return false;
> +
> + /* Wa_22011186057 */
> + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + return false;
> +
> + if (DISPLAY_VER(i915) >= 11)
> + return true;
> +
> + if (IS_GEMINILAKE(i915))
> + return pipe != PIPE_C;
> +
> + return pipe != PIPE_C &&
> + (plane_id == PLANE_PRIMARY ||
> + plane_id == PLANE_SPRITE0);
> +}
This part I don't really like. IMO the plane capabilities should
be listed in the plane code, not anywhere else.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 21:10 ` Ville Syrjälä
@ 2021-10-07 21:26 ` Imre Deak
2021-10-07 21:32 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 21:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h | 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 8 files changed, 218 insertions(+), 164 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB8888,
> > };
> >
> > -static const u64 cursor_format_modifiers[] = {
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > - format == DRM_FORMAT_ARGB8888;
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > + return false;
> > +
> > + return format == DRM_FORMAT_ARGB8888;
> > }
> >
> > static int
> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > {
> > struct intel_plane *cursor;
> > int ret, zpos;
> > + u64 *modifiers;
> >
> > cursor = intel_plane_alloc();
> > if (IS_ERR(cursor))
> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > cursor->cursor.size = ~0;
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > 0, &intel_cursor_plane_funcs,
> > intel_cursor_formats,
> > ARRAY_SIZE(intel_cursor_formats),
> > - cursor_format_modifiers,
> > + modifiers,
> > DRM_PLANE_TYPE_CURSOR,
> > "cursor %c", pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645a..bb53b01f07aee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > enum plane_id id;
> > enum pipe pipe;
> > bool has_fbc;
> > - bool has_ccs;
> > bool need_async_flip_disable_wa;
> > u32 frontbuffer_bit;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index fa1f375e696bf..aefae988b620b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,6 +13,184 @@
> >
> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> >
> > +const struct intel_modifier_desc {
> > + u64 id;
> > + u64 display_versions;
> > +
> > + struct {
> > +#define INTEL_CCS_RC BIT(0)
> > +#define INTEL_CCS_RC_CC BIT(1)
> > +#define INTEL_CCS_MC BIT(2)
> > +
> > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > + u8 type:3;
> > + } ccs;
> > +} intel_modifiers[] = {
> > + {
> > + .id = DRM_FORMAT_MOD_LINEAR,
> > + .display_versions = DISPLAY_VER_MASK_ALL,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_X_TILED,
> > + .display_versions = DISPLAY_VER_MASK_ALL,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED,
> > + .display_versions = DISPLAY_VER_MASK(9, 13),
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Yf_TILED,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_RC_CC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_MC,
> > + },
> > +};
> > +
> > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > +{
> > + return md->ccs.type & ccs_type;
> > +}
> > +
> > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > + enum pipe pipe, enum plane_id plane_id)
> > +{
> > + if (plane_id == PLANE_CURSOR)
> > + return false;
> > +
> > + /* Wa_22011186057 */
> > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > + return false;
> > +
> > + if (DISPLAY_VER(i915) >= 11)
> > + return true;
> > +
> > + if (IS_GEMINILAKE(i915))
> > + return pipe != PIPE_C;
> > +
> > + return pipe != PIPE_C &&
> > + (plane_id == PLANE_PRIMARY ||
> > + plane_id == PLANE_SPRITE0);
> > +}
>
> This part I don't really like. IMO the plane capabilities should
> be listed in the plane code, not anywhere else.
Ok. How about adding back plane->has_rc_ccs and also adding
plane->has_mc_ccs and initing these before calling
intel_fb_plane_get_modifiers() (as before)?
What about the
plane_id == PLANE_CURSOR && md->id != DRM_FORMAT_MOD_LINEAR
check in plane_has_modifier()?
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 21:26 ` Imre Deak
@ 2021-10-07 21:32 ` Ville Syrjälä
2021-10-07 22:00 ` Imre Deak
0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-07 21:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 12:26:11AM +0300, Imre Deak wrote:
> On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > > Add a table describing all the framebuffer modifiers used by i915 at one
> > > place. This has the benefit of deduplicating the listing of supported
> > > modifiers for each platform and checking the support of these modifiers
> > > on a given plane. This also simplifies in a similar way getting some
> > > attribute for a modifier, for instance checking if the modifier is a
> > > CCS modifier type.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > > .../drm/i915/display/intel_display_types.h | 1 -
> > > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > 8 files changed, 218 insertions(+), 164 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > > DRM_FORMAT_ARGB8888,
> > > };
> > >
> > > -static const u64 cursor_format_modifiers[] = {
> > > - DRM_FORMAT_MOD_LINEAR,
> > > - DRM_FORMAT_MOD_INVALID
> > > -};
> > > -
> > > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > > {
> > > struct drm_i915_private *dev_priv =
> > > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > > u32 format, u64 modifier)
> > > {
> > > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > > - format == DRM_FORMAT_ARGB8888;
> > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > > + return false;
> > > +
> > > + return format == DRM_FORMAT_ARGB8888;
> > > }
> > >
> > > static int
> > > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > {
> > > struct intel_plane *cursor;
> > > int ret, zpos;
> > > + u64 *modifiers;
> > >
> > > cursor = intel_plane_alloc();
> > > if (IS_ERR(cursor))
> > > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > > cursor->cursor.size = ~0;
> > >
> > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > > +
> > > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > > 0, &intel_cursor_plane_funcs,
> > > intel_cursor_formats,
> > > ARRAY_SIZE(intel_cursor_formats),
> > > - cursor_format_modifiers,
> > > + modifiers,
> > > DRM_PLANE_TYPE_CURSOR,
> > > "cursor %c", pipe_name(pipe));
> > > +
> > > + kfree(modifiers);
> > > +
> > > if (ret)
> > > goto fail;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 21ce8bccc645a..bb53b01f07aee 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > > enum plane_id id;
> > > enum pipe pipe;
> > > bool has_fbc;
> > > - bool has_ccs;
> > > bool need_async_flip_disable_wa;
> > > u32 frontbuffer_bit;
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index fa1f375e696bf..aefae988b620b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -13,6 +13,184 @@
> > >
> > > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> > >
> > > +const struct intel_modifier_desc {
> > > + u64 id;
> > > + u64 display_versions;
> > > +
> > > + struct {
> > > +#define INTEL_CCS_RC BIT(0)
> > > +#define INTEL_CCS_RC_CC BIT(1)
> > > +#define INTEL_CCS_MC BIT(2)
> > > +
> > > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > > + u8 type:3;
> > > + } ccs;
> > > +} intel_modifiers[] = {
> > > + {
> > > + .id = DRM_FORMAT_MOD_LINEAR,
> > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_X_TILED,
> > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Y_TILED,
> > > + .display_versions = DISPLAY_VER_MASK(9, 13),
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Yf_TILED,
> > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > +
> > > + .ccs.type = INTEL_CCS_RC,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > +
> > > + .ccs.type = INTEL_CCS_RC,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > +
> > > + .ccs.type = INTEL_CCS_RC,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > +
> > > + .ccs.type = INTEL_CCS_RC_CC,
> > > + },
> > > + {
> > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > +
> > > + .ccs.type = INTEL_CCS_MC,
> > > + },
> > > +};
> > > +
> > > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > > +{
> > > + return md->ccs.type & ccs_type;
> > > +}
> > > +
> > > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > > + enum pipe pipe, enum plane_id plane_id)
> > > +{
> > > + if (plane_id == PLANE_CURSOR)
> > > + return false;
> > > +
> > > + /* Wa_22011186057 */
> > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > > + return false;
> > > +
> > > + if (DISPLAY_VER(i915) >= 11)
> > > + return true;
> > > +
> > > + if (IS_GEMINILAKE(i915))
> > > + return pipe != PIPE_C;
> > > +
> > > + return pipe != PIPE_C &&
> > > + (plane_id == PLANE_PRIMARY ||
> > > + plane_id == PLANE_SPRITE0);
> > > +}
> >
> > This part I don't really like. IMO the plane capabilities should
> > be listed in the plane code, not anywhere else.
>
> Ok. How about adding back plane->has_rc_ccs and also adding
> plane->has_mc_ccs and initing these before calling
> intel_fb_plane_get_modifiers() (as before)?
Yeah, maybe something like that. Ie. basically reduce the full list
of modifiers to a set of higher level classes, which each plane could
declare in a more compact form. I guess we could have some kind of small
plane_caps structure for it this even?
We would lose the direct info in the plane code for eg. "is Yf
supported?", but since that's a platform wide thing I don't think
it's a problem. Just the info about the individual planes and their
special little exceptions I'd really would want in the plane code.
>
> What about the
> plane_id == PLANE_CURSOR && md->id != DRM_FORMAT_MOD_LINEAR
> check in plane_has_modifier()?
Maybe we reduce that to .has_tiling or something?
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (10 preceding siblings ...)
2021-10-07 20:35 ` [Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak
@ 2021-10-07 21:33 ` Patchwork
2021-10-07 21:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-07 21:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Simplify handling of modifiers
URL : https://patchwork.freedesktop.org/series/95579/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b43f636afaea drm/i915: Add a table with a descriptor for all i915 modifiers
147f27b14377 drm/i915: Move intel_get_format_info() to intel_fb.c
-:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'format_list' - possible side-effects?
#264: FILE: drivers/gpu/drm/i915/display/intel_fb.c:109:
+#define FORMAT_OVERRIDE(format_list) \
+ .formats = format_list, \
+ .format_count = ARRAY_SIZE(format_list)
total: 0 errors, 0 warnings, 1 checks, 350 lines checked
00315bd9b13a drm/i915: Add tiling attribute to the modifier descriptor
a07b18ff79b6 drm/i915: Simplify the modifier check for interlaced scanout support
6c7f82cfed4e drm/i915: Unexport is_semiplanar_uv_plane()
2b0fae99dcf3 drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
049969f74a95 drm/i915: Add a platform independent way to get the RC CCS CC plane
26e6af6207e8 drm/i915: Handle CCS CC planes separately from CCS control planes
14c507bc8eb3 drm/i915: Add a platform independent way to check for CCS control planes
-:247: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#247: FILE: drivers/gpu/drm/i915/display/intel_fb.c:1234:
+ unsigned int min_stride = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ? 2 : 8;
total: 0 errors, 1 warnings, 0 checks, 228 lines checked
4dfe4cce0fad drm/i915: Move is_ccs_modifier() to intel_fb.c
656646ce1dc3 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Simplify handling of modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (11 preceding siblings ...)
2021-10-07 21:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers Patchwork
@ 2021-10-07 21:35 ` Patchwork
2021-10-07 21:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-07 21:35 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Simplify handling of modifiers
URL : https://patchwork.freedesktop.org/series/95579/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_fb.c:131:3: warning: symbol 'intel_modifiers' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Simplify handling of modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (12 preceding siblings ...)
2021-10-07 21:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-07 21:50 ` Patchwork
2021-10-08 0:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev9) Patchwork
` (4 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-07 21:50 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20368 bytes --]
== Series Details ==
Series: drm/i915: Simplify handling of modifiers
URL : https://patchwork.freedesktop.org/series/95579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10696 -> Patchwork_21283
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21283 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21283, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21283:
### IGT changes ###
#### Possible regressions ####
* igt@kms_addfb_basic@addfb25-bad-modifier:
- fi-icl-y: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-icl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-icl-y/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bwr-2160: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bwr-2160/igt@kms_addfb_basic@addfb25-bad-modifier.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bwr-2160/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-rkl-11600: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-rkl-11600/igt@kms_addfb_basic@addfb25-bad-modifier.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-rkl-11600/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-skl-guc: [PASS][7] -> [DMESG-WARN][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-skl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-skl-6600u: [PASS][9] -> [DMESG-WARN][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-skl-6600u/igt@kms_addfb_basic@addfb25-bad-modifier.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6600u/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-pnv-d510: [PASS][11] -> [DMESG-WARN][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-pnv-d510/igt@kms_addfb_basic@addfb25-bad-modifier.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-pnv-d510/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bdw-5557u: [PASS][13] -> [DMESG-WARN][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bdw-5557u/igt@kms_addfb_basic@addfb25-bad-modifier.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bdw-5557u/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-7567u: [PASS][15] -> [DMESG-WARN][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-7567u/igt@kms_addfb_basic@addfb25-bad-modifier.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-7567u/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-snb-2520m: [PASS][17] -> [DMESG-WARN][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-snb-2520m/igt@kms_addfb_basic@addfb25-bad-modifier.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-snb-2520m/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-tgl-1115g4: [PASS][19] -> [DMESG-WARN][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-1115g4/igt@kms_addfb_basic@addfb25-bad-modifier.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-tgl-1115g4/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-hsw-4770: [PASS][21] -> [DMESG-WARN][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-hsw-4770/igt@kms_addfb_basic@addfb25-bad-modifier.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-hsw-4770/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bxt-dsi: [PASS][23] -> [DMESG-WARN][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bxt-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bxt-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-cfl-8700k: [PASS][25] -> [DMESG-WARN][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cfl-8700k/igt@kms_addfb_basic@addfb25-bad-modifier.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-8700k/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-skl-6700k2: NOTRUN -> [DMESG-WARN][27]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6700k2/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-icl-u2: [PASS][28] -> [DMESG-WARN][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-icl-u2/igt@kms_addfb_basic@addfb25-bad-modifier.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-icl-u2/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-elk-e7500: [PASS][30] -> [DMESG-WARN][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-elk-e7500/igt@kms_addfb_basic@addfb25-bad-modifier.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-elk-e7500/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-cml-u2: [PASS][32] -> [DMESG-WARN][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cml-u2/igt@kms_addfb_basic@addfb25-bad-modifier.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cml-u2/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-ivb-3770: [PASS][34] -> [DMESG-WARN][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-ivb-3770/igt@kms_addfb_basic@addfb25-bad-modifier.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-ivb-3770/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bsw-n3050: [PASS][36] -> [DMESG-WARN][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bsw-n3050/igt@kms_addfb_basic@addfb25-bad-modifier.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-n3050/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-snb-2600: [PASS][38] -> [DMESG-WARN][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-snb-2600/igt@kms_addfb_basic@addfb25-bad-modifier.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-snb-2600/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-cfl-guc: [PASS][40] -> [DMESG-WARN][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cfl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-soraka: [PASS][42] -> [DMESG-WARN][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-soraka/igt@kms_addfb_basic@addfb25-bad-modifier.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-soraka/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-glk-dsi: [PASS][44] -> [DMESG-WARN][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-glk-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-glk-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bsw-kefka: [PASS][46] -> [DMESG-WARN][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bsw-kefka/igt@kms_addfb_basic@addfb25-bad-modifier.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-kefka/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-r: [PASS][48] -> [DMESG-WARN][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-r/igt@kms_addfb_basic@addfb25-bad-modifier.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-r/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-8809g: [PASS][50] -> [DMESG-WARN][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-8809g/igt@kms_addfb_basic@addfb25-bad-modifier.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-8809g/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-7500u: [PASS][52] -> [DMESG-WARN][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-7500u/igt@kms_addfb_basic@addfb25-bad-modifier.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-7500u/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-bsw-nick: [PASS][54] -> [DMESG-WARN][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bsw-nick/igt@kms_addfb_basic@addfb25-bad-modifier.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-nick/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-rkl-guc: [PASS][56] -> [DMESG-WARN][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-rkl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-rkl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-cfl-8109u: [PASS][58] -> [DMESG-WARN][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cfl-8109u/igt@kms_addfb_basic@addfb25-bad-modifier.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-8109u/igt@kms_addfb_basic@addfb25-bad-modifier.html
- fi-kbl-guc: [PASS][60] -> [DMESG-WARN][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-guc/igt@kms_addfb_basic@addfb25-bad-modifier.html
* igt@runner@aborted:
- fi-rkl-11600: NOTRUN -> [FAIL][62]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-rkl-11600/igt@runner@aborted.html
- fi-snb-2600: NOTRUN -> [FAIL][63]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-snb-2600/igt@runner@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][64]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-kefka/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][65]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-nick/igt@runner@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][66]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-snb-2520m/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][67]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bdw-5557u/igt@runner@aborted.html
- fi-bwr-2160: NOTRUN -> [FAIL][68]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bwr-2160/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][69]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-hsw-4770/igt@runner@aborted.html
- fi-rkl-guc: NOTRUN -> [FAIL][70]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-rkl-guc/igt@runner@aborted.html
- fi-ivb-3770: NOTRUN -> [FAIL][71]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-ivb-3770/igt@runner@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][72]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-tgl-1115g4/igt@runner@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][73]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-elk-e7500/igt@runner@aborted.html
- fi-icl-y: NOTRUN -> [FAIL][74]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-icl-y/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][75]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bsw-n3050/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@addfb25-bad-modifier:
- {fi-hsw-gt1}: [PASS][76] -> [DMESG-WARN][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-hsw-gt1/igt@kms_addfb_basic@addfb25-bad-modifier.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-hsw-gt1/igt@kms_addfb_basic@addfb25-bad-modifier.html
- {fi-tgl-dsi}: [PASS][78] -> [DMESG-WARN][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-tgl-dsi/igt@kms_addfb_basic@addfb25-bad-modifier.html
- {fi-jsl-1}: [PASS][80] -> [DMESG-WARN][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-jsl-1/igt@kms_addfb_basic@addfb25-bad-modifier.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-jsl-1/igt@kms_addfb_basic@addfb25-bad-modifier.html
- {fi-ehl-2}: [PASS][82] -> [DMESG-WARN][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-ehl-2/igt@kms_addfb_basic@addfb25-bad-modifier.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-ehl-2/igt@kms_addfb_basic@addfb25-bad-modifier.html
* igt@runner@aborted:
- {fi-hsw-gt1}: NOTRUN -> [FAIL][84]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-hsw-gt1/igt@runner@aborted.html
- {fi-tgl-dsi}: NOTRUN -> [FAIL][85]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-tgl-dsi/igt@runner@aborted.html
- {fi-jsl-1}: NOTRUN -> [FAIL][86]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-jsl-1/igt@runner@aborted.html
- {fi-ehl-2}: NOTRUN -> [FAIL][87]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-ehl-2/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_21283 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-skl-6700k2: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#2190])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][89] ([i915#2403])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-pnv-d510/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][90] ([i915#3363])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-8700k/igt@runner@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][91] ([i915#3363])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6600u/igt@runner@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][92] ([i915#3363])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-8109u/igt@runner@aborted.html
- fi-icl-u2: NOTRUN -> [FAIL][93] ([i915#3363])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-icl-u2/igt@runner@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][94] ([i915#3363] / [k.org#202321])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-glk-dsi/igt@runner@aborted.html
- fi-kbl-8809g: NOTRUN -> [FAIL][95] ([i915#3363])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-8809g/igt@runner@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][96] ([i915#3363])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-r/igt@runner@aborted.html
- fi-kbl-soraka: NOTRUN -> [FAIL][97] ([i915#3363])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-soraka/igt@runner@aborted.html
- fi-kbl-7500u: NOTRUN -> [FAIL][98] ([i915#3363])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-7500u/igt@runner@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][99] ([i915#3363])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-guc/igt@runner@aborted.html
- fi-cml-u2: NOTRUN -> [FAIL][100] ([i915#3363])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cml-u2/igt@runner@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][101] ([i915#3363])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-bxt-dsi/igt@runner@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][102] ([i915#3363])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-cfl-guc/igt@runner@aborted.html
- fi-kbl-7567u: NOTRUN -> [FAIL][103] ([i915#3363])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-kbl-7567u/igt@runner@aborted.html
- fi-skl-guc: NOTRUN -> [FAIL][104] ([i915#3363])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-guc/igt@runner@aborted.html
- fi-skl-6700k2: NOTRUN -> [FAIL][105] ([i915#3363])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6700k2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][106] ([i915#1888]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
- fi-skl-6700k2: [INCOMPLETE][108] ([i915#146] / [i915#198]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (44 -> 37)
------------------------------
Missing (7): fi-ilk-m540 bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10696 -> Patchwork_21283
CI-20190529: 20190529
CI_DRM_10696: 58a206ae5bf2f81a11e4408d10a3e1b445d6eebb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6237: 910b5caac6625d2bf0b6c1dde502451431bd0159 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21283: 656646ce1dc3186b6e31faa2a02f974c6251e8ee @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
656646ce1dc3 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
4dfe4cce0fad drm/i915: Move is_ccs_modifier() to intel_fb.c
14c507bc8eb3 drm/i915: Add a platform independent way to check for CCS control planes
26e6af6207e8 drm/i915: Handle CCS CC planes separately from CCS control planes
049969f74a95 drm/i915: Add a platform independent way to get the RC CCS CC plane
2b0fae99dcf3 drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
6c7f82cfed4e drm/i915: Unexport is_semiplanar_uv_plane()
a07b18ff79b6 drm/i915: Simplify the modifier check for interlaced scanout support
00315bd9b13a drm/i915: Add tiling attribute to the modifier descriptor
147f27b14377 drm/i915: Move intel_get_format_info() to intel_fb.c
b43f636afaea drm/i915: Add a table with a descriptor for all i915 modifiers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21283/index.html
[-- Attachment #2: Type: text/html, Size: 23142 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 21:32 ` Ville Syrjälä
@ 2021-10-07 22:00 ` Imre Deak
2021-10-08 9:41 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-07 22:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 12:32:57AM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 12:26:11AM +0300, Imre Deak wrote:
> > On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > > > Add a table describing all the framebuffer modifiers used by i915 at one
> > > > place. This has the benefit of deduplicating the listing of supported
> > > > modifiers for each platform and checking the support of these modifiers
> > > > on a given plane. This also simplifies in a similar way getting some
> > > > attribute for a modifier, for instance checking if the modifier is a
> > > > CCS modifier type.
> > > >
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > > > .../drm/i915/display/intel_display_types.h | 1 -
> > > > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > > > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > > > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > > > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> > > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > > 8 files changed, 218 insertions(+), 164 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > > > DRM_FORMAT_ARGB8888,
> > > > };
> > > >
> > > > -static const u64 cursor_format_modifiers[] = {
> > > > - DRM_FORMAT_MOD_LINEAR,
> > > > - DRM_FORMAT_MOD_INVALID
> > > > -};
> > > > -
> > > > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > > > {
> > > > struct drm_i915_private *dev_priv =
> > > > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > > > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > > > u32 format, u64 modifier)
> > > > {
> > > > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > > > - format == DRM_FORMAT_ARGB8888;
> > > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > > > + return false;
> > > > +
> > > > + return format == DRM_FORMAT_ARGB8888;
> > > > }
> > > >
> > > > static int
> > > > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > > {
> > > > struct intel_plane *cursor;
> > > > int ret, zpos;
> > > > + u64 *modifiers;
> > > >
> > > > cursor = intel_plane_alloc();
> > > > if (IS_ERR(cursor))
> > > > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > > > cursor->cursor.size = ~0;
> > > >
> > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > > > +
> > > > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > > > 0, &intel_cursor_plane_funcs,
> > > > intel_cursor_formats,
> > > > ARRAY_SIZE(intel_cursor_formats),
> > > > - cursor_format_modifiers,
> > > > + modifiers,
> > > > DRM_PLANE_TYPE_CURSOR,
> > > > "cursor %c", pipe_name(pipe));
> > > > +
> > > > + kfree(modifiers);
> > > > +
> > > > if (ret)
> > > > goto fail;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 21ce8bccc645a..bb53b01f07aee 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > > > enum plane_id id;
> > > > enum pipe pipe;
> > > > bool has_fbc;
> > > > - bool has_ccs;
> > > > bool need_async_flip_disable_wa;
> > > > u32 frontbuffer_bit;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > index fa1f375e696bf..aefae988b620b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > @@ -13,6 +13,184 @@
> > > >
> > > > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> > > >
> > > > +const struct intel_modifier_desc {
> > > > + u64 id;
> > > > + u64 display_versions;
> > > > +
> > > > + struct {
> > > > +#define INTEL_CCS_RC BIT(0)
> > > > +#define INTEL_CCS_RC_CC BIT(1)
> > > > +#define INTEL_CCS_MC BIT(2)
> > > > +
> > > > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > > > + u8 type:3;
> > > > + } ccs;
> > > > +} intel_modifiers[] = {
> > > > + {
> > > > + .id = DRM_FORMAT_MOD_LINEAR,
> > > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_X_TILED,
> > > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Y_TILED,
> > > > + .display_versions = DISPLAY_VER_MASK(9, 13),
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Yf_TILED,
> > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > +
> > > > + .ccs.type = INTEL_CCS_RC,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > +
> > > > + .ccs.type = INTEL_CCS_RC,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > +
> > > > + .ccs.type = INTEL_CCS_RC,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > +
> > > > + .ccs.type = INTEL_CCS_RC_CC,
> > > > + },
> > > > + {
> > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > +
> > > > + .ccs.type = INTEL_CCS_MC,
> > > > + },
> > > > +};
> > > > +
> > > > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > > > +{
> > > > + return md->ccs.type & ccs_type;
> > > > +}
> > > > +
> > > > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > > > + enum pipe pipe, enum plane_id plane_id)
> > > > +{
> > > > + if (plane_id == PLANE_CURSOR)
> > > > + return false;
> > > > +
> > > > + /* Wa_22011186057 */
> > > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > > > + return false;
> > > > +
> > > > + if (DISPLAY_VER(i915) >= 11)
> > > > + return true;
> > > > +
> > > > + if (IS_GEMINILAKE(i915))
> > > > + return pipe != PIPE_C;
> > > > +
> > > > + return pipe != PIPE_C &&
> > > > + (plane_id == PLANE_PRIMARY ||
> > > > + plane_id == PLANE_SPRITE0);
> > > > +}
> > >
> > > This part I don't really like. IMO the plane capabilities should
> > > be listed in the plane code, not anywhere else.
> >
> > Ok. How about adding back plane->has_rc_ccs and also adding
> > plane->has_mc_ccs and initing these before calling
> > intel_fb_plane_get_modifiers() (as before)?
>
> Yeah, maybe something like that. Ie. basically reduce the full list
> of modifiers to a set of higher level classes, which each plane could
> declare in a more compact form. I guess we could have some kind of small
> plane_caps structure for it this even?
So also including the cursor case below something like a plane_caps enum
with bitfields for PLANE_HAS_CCS_RC (applying to both RC and RC_CC since
no point to differentiate even on SKL for this), PLANE_HAS_CCS_MC and
PLANE_HAS_TILING? This enum could be just passed then to
intel_fb_plane_get_modifiers() instead of pipe and plane_id.
> We would lose the direct info in the plane code for eg. "is Yf
> supported?",
If becomes an issue could this be a new cap?
> but since that's a platform wide thing I don't think
> it's a problem. Just the info about the individual planes and their
> special little exceptions I'd really would want in the plane code.
>
> > What about the
> > plane_id == PLANE_CURSOR && md->id != DRM_FORMAT_MOD_LINEAR
> > check in plane_has_modifier()?
>
> Maybe we reduce that to .has_tiling or something?
So the above PLANE_HAS_TILING and to keep initialization simple an
.linear field in intel_modifier_desc?
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
2021-10-07 21:10 ` Ville Syrjälä
@ 2021-10-08 0:19 ` Imre Deak
2021-10-13 20:14 ` Ville Syrjälä
2021-10-13 20:40 ` Ville Syrjälä
2021-10-14 14:07 ` [Intel-gfx] [PATCH " Jani Nikula
2 siblings, 2 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Ville Syrjälä
Add a table describing all the framebuffer modifiers used by i915 at one
place. This has the benefit of deduplicating the listing of supported
modifiers for each platform and checking the support of these modifiers
on a given plane. This also simplifies in a similar way getting some
attribute for a modifier, for instance checking if the modifier is a
CCS modifier type.
v2:
- Keep the plane caps calculation in the plane code and pass an enum
with these caps to intel_fb_get_modifiers(). (Ville)
- Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
well.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
.../drm/i915/display/intel_display_types.h | 1 -
drivers/gpu/drm/i915/display/intel_fb.c | 143 ++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 16 ++
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 181 +++++-------------
drivers/gpu/drm/i915/i915_drv.h | 3 +
9 files changed, 245 insertions(+), 184 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1439ba78f67b..a939accff7ee2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
DRM_FORMAT_XBGR16161616F,
};
-static const u64 i9xx_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
struct intel_plane *plane;
const struct drm_plane_funcs *plane_funcs;
unsigned int supported_rotations;
+ const u64 *modifiers;
const u32 *formats;
int num_formats;
int ret, zpos;
@@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
plane->disable_flip_done = ilk_primary_disable_flip_done;
}
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
+
if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"primary %c", pipe_name(pipe));
else
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats,
- i9xx_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_PRIMARY,
"plane %c",
plane_name(plane->i9xx_plane));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f64..1f764c6d59583 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
DRM_FORMAT_ARGB8888,
};
-static const u64 cursor_format_modifiers[] = {
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
@@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- return modifier == DRM_FORMAT_MOD_LINEAR &&
- format == DRM_FORMAT_ARGB8888;
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
+ return false;
+
+ return format == DRM_FORMAT_ARGB8888;
}
static int
@@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
{
struct intel_plane *cursor;
int ret, zpos;
+ u64 *modifiers;
cursor = intel_plane_alloc();
if (IS_ERR(cursor))
@@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
cursor->cursor.size = ~0;
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS);
+
ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
0, &intel_cursor_plane_funcs,
intel_cursor_formats,
ARRAY_SIZE(intel_cursor_formats),
- cursor_format_modifiers,
+ modifiers,
DRM_PLANE_TYPE_CURSOR,
"cursor %c", pipe_name(pipe));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 21ce8bccc645a..bb53b01f07aee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1336,7 +1336,6 @@ struct intel_plane {
enum plane_id id;
enum pipe pipe;
bool has_fbc;
- bool has_ccs;
bool need_async_flip_disable_wa;
u32 frontbuffer_bit;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index fa1f375e696bf..11a4c3e81cead 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -13,6 +13,149 @@
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
+const struct intel_modifier_desc {
+ u64 id;
+ u64 display_versions;
+ u8 is_linear:1;
+
+ struct {
+#define INTEL_CCS_RC BIT(0)
+#define INTEL_CCS_RC_CC BIT(1)
+#define INTEL_CCS_MC BIT(2)
+
+#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
+ u8 type:3;
+ } ccs;
+} intel_modifiers[] = {
+ {
+ .id = DRM_FORMAT_MOD_LINEAR,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ .is_linear = true,
+ },
+ {
+ .id = I915_FORMAT_MOD_X_TILED,
+ .display_versions = DISPLAY_VER_MASK_ALL,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 13),
+ },
+ {
+ .id = I915_FORMAT_MOD_Yf_TILED,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_CCS,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Yf_TILED_CCS,
+ .display_versions = DISPLAY_VER_MASK(9, 11),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_RC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_RC_CC,
+ },
+ {
+ .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
+ .display_versions = DISPLAY_VER_MASK(12, 13),
+
+ .ccs.type = INTEL_CCS_MC,
+ },
+};
+
+static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
+{
+ return md->ccs.type & ccs_type;
+}
+
+static bool plane_has_modifier(struct drm_i915_private *i915,
+ enum intel_plane_caps plane_caps,
+ const struct intel_modifier_desc *md)
+{
+ if (!(DISPLAY_VER_BIT(DISPLAY_VER(i915)) & md->display_versions))
+ return false;
+
+ if (!(plane_caps & PLANE_HAS_TILING) && !md->is_linear)
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) &&
+ !(plane_caps & PLANE_HAS_CCS_RC))
+ return false;
+
+ if (is_ccs_type_modifier(md, INTEL_CCS_MC) &&
+ !(plane_caps & PLANE_HAS_CCS_MC))
+ return false;
+
+ return true;
+}
+
+/**
+ * intel_fb_plane_get_modifiers: Get the modifiers supported by the given pipe and plane
+ * @i915: i915 device instance
+ * @plane_caps: capabilities for the plane the modifiers are queried for
+ *
+ * Returns:
+ * Returns the list of modifiers as allowed by @plane_caps.
+ * The caller must free the returned buffer.
+ */
+u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
+ enum intel_plane_caps plane_caps)
+{
+ u64 *list, *p;
+ int count = 1; /* +1 for invalid modifier terminator */
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
+ if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
+ count++;
+ }
+
+ list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
+ if (drm_WARN_ON(&i915->drm, !list))
+ return NULL;
+
+ p = list;
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
+ if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
+ *p++ = intel_modifiers[i].id;
+ }
+ *p++ = DRM_FORMAT_MOD_INVALID;
+
+ return list;
+}
+
+/**
+ * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
+ * @plane: Plane to check the modifier support for
+ * @modifier: The modifier to check the support for
+ *
+ * Returns:
+ * %true if the @modifier is supported on @plane.
+ */
+bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
+{
+ int i;
+
+ for (i = 0; i < plane->base.modifier_count; i++)
+ if (plane->base.modifiers[i] == modifier)
+ return true;
+
+ return false;
+}
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
{
if (!is_ccs_modifier(fb->modifier))
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 1cbdd84502bdd..5bff88ccb9372 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -6,8 +6,12 @@
#ifndef __INTEL_FB_H__
#define __INTEL_FB_H__
+#include <linux/bits.h>
#include <linux/types.h>
+enum pipe;
+enum plane_id;
+
struct drm_device;
struct drm_file;
struct drm_framebuffer;
@@ -16,13 +20,25 @@ struct drm_i915_private;
struct drm_mode_fb_cmd2;
struct intel_fb_view;
struct intel_framebuffer;
+struct intel_plane;
struct intel_plane_state;
+enum intel_plane_caps {
+ PLANE_HAS_NO_CAPS = 0,
+ PLANE_HAS_TILING = BIT(0),
+ PLANE_HAS_CCS_RC = BIT(1),
+ PLANE_HAS_CCS_MC = BIT(2),
+};
+
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
+u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
+ enum intel_plane_caps plane_caps);
+bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 08116f41da26a..2f4f47ab9da03 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -45,6 +45,7 @@
#include "intel_atomic_plane.h"
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "intel_frontbuffer.h"
#include "intel_sprite.h"
#include "i9xx_plane.h"
@@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = {
DRM_FORMAT_VYUY,
};
-static const u64 i9xx_plane_format_modifiers[] = {
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
static const u32 snb_plane_formats[] = {
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
@@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = {
static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_C8:
@@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
formats = vlv_plane_formats;
num_formats = ARRAY_SIZE(vlv_plane_formats);
}
- modifiers = i9xx_plane_format_modifiers;
plane_funcs = &vlv_sprite_funcs;
} else if (DISPLAY_VER(dev_priv) >= 7) {
@@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
- modifiers = i9xx_plane_format_modifiers;
plane_funcs = &snb_sprite_funcs;
} else {
@@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->max_stride = g4x_sprite_max_stride;
plane->min_cdclk = g4x_sprite_min_cdclk;
- modifiers = i9xx_plane_format_modifiers;
if (IS_SANDYBRIDGE(dev_priv)) {
formats = snb_plane_formats;
num_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane->id = PLANE_SPRITE0 + sprite;
plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
+
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
DRM_PLANE_TYPE_OVERLAY,
"sprite %c", sprite_name(pipe, sprite));
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index 37eabeff8197f..c2e94118566b6 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -4,6 +4,7 @@
*/
#include "intel_de.h"
#include "intel_display_types.h"
+#include "intel_fb.h"
#include "skl_scaler.h"
#include "skl_universal_plane.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a0e53a3b267aa..908eb87d9cf8f 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = {
DRM_FORMAT_XVYU16161616,
};
-static const u64 skl_plane_format_modifiers_noccs[] = {
- I915_FORMAT_MOD_Yf_TILED,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 skl_plane_format_modifiers_ccs[] = {
- I915_FORMAT_MOD_Yf_TILED_CCS,
- I915_FORMAT_MOD_Y_TILED_CCS,
- I915_FORMAT_MOD_Yf_TILED,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
- I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
- I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
-static const u64 adlp_step_a_plane_format_modifiers[] = {
- I915_FORMAT_MOD_Y_TILED,
- I915_FORMAT_MOD_X_TILED,
- DRM_FORMAT_MOD_LINEAR,
- DRM_FORMAT_MOD_INVALID
-};
-
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
{
switch (format) {
@@ -1870,42 +1826,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
}
}
-static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
- enum pipe pipe, enum plane_id plane_id)
-{
- if (plane_id == PLANE_CURSOR)
- return false;
-
- if (DISPLAY_VER(dev_priv) >= 11)
- return true;
-
- if (IS_GEMINILAKE(dev_priv))
- return pipe != PIPE_C;
-
- return pipe != PIPE_C &&
- (plane_id == PLANE_PRIMARY ||
- plane_id == PLANE_SPRITE0);
-}
-
static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
struct intel_plane *plane = to_intel_plane(_plane);
- switch (modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Yf_TILED:
- break;
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (!plane->has_ccs)
- return false;
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(plane, modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -1953,45 +1880,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
}
}
-static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
- enum plane_id plane_id)
-{
- /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
- if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
- IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
- return false;
-
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return false;
-
- return plane_id < PLANE_SPRITE4;
-}
-
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier)
{
- struct drm_i915_private *dev_priv = to_i915(_plane->dev);
struct intel_plane *plane = to_intel_plane(_plane);
- switch (modifier) {
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
- return false;
- fallthrough;
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- break;
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return false;
- break;
- default:
+ if (!intel_fb_plane_supports_modifier(plane, modifier))
return false;
- }
switch (format) {
case DRM_FORMAT_XRGB8888:
@@ -2039,18 +1934,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
}
}
-static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
- enum plane_id plane_id)
-{
- /* Wa_22011186057 */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- return adlp_step_a_plane_format_modifiers;
- else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
- return gen12_plane_format_modifiers_mc_ccs;
- else
- return gen12_plane_format_modifiers_rc_ccs;
-}
-
static const struct drm_plane_funcs skl_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane,
@@ -2091,6 +1974,42 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
spin_unlock_irq(&i915->irq_lock);
}
+static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
+ enum pipe pipe, enum plane_id plane_id)
+{
+ if (plane_id == PLANE_CURSOR)
+ return false;
+
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ if (DISPLAY_VER(i915) >= 11)
+ return true;
+
+ if (IS_GEMINILAKE(i915))
+ return pipe != PIPE_C;
+
+ return pipe != PIPE_C &&
+ (plane_id == PLANE_PRIMARY ||
+ plane_id == PLANE_SPRITE0);
+}
+
+static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
+ enum plane_id plane_id)
+{
+ /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
+ if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
+ IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
+ return false;
+
+ /* Wa_22011186057 */
+ if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
+ return false;
+
+ return plane_id < PLANE_SPRITE4;
+}
+
struct intel_plane *
skl_universal_plane_create(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id)
@@ -2098,6 +2017,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
const struct drm_plane_funcs *plane_funcs;
struct intel_plane *plane;
enum drm_plane_type plane_type;
+ enum intel_plane_caps plane_caps;
unsigned int supported_rotations;
unsigned int supported_csc;
const u64 *modifiers;
@@ -2159,29 +2079,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
formats = skl_get_plane_formats(dev_priv, pipe,
plane_id, &num_formats);
- plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
- if (DISPLAY_VER(dev_priv) >= 12) {
- modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
+ if (DISPLAY_VER(dev_priv) >= 12)
plane_funcs = &gen12_plane_funcs;
- } else {
- if (plane->has_ccs)
- modifiers = skl_plane_format_modifiers_ccs;
- else
- modifiers = skl_plane_format_modifiers_noccs;
+ else
plane_funcs = &skl_plane_funcs;
- }
if (plane_id == PLANE_PRIMARY)
plane_type = DRM_PLANE_TYPE_PRIMARY;
else
plane_type = DRM_PLANE_TYPE_OVERLAY;
+ plane_caps = PLANE_HAS_TILING;
+ if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id))
+ plane_caps |= PLANE_HAS_CCS_RC;
+
+ if (gen12_plane_has_mc_ccs(dev_priv, plane_id))
+ plane_caps |= PLANE_HAS_CCS_MC;
+
+ modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps);
+
ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
0, plane_funcs,
formats, num_formats, modifiers,
plane_type,
"plane %d%c", plane_id + 1,
pipe_name(pipe));
+
+ kfree(modifiers);
+
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f4..a92228c922a54 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
#define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
+#define DISPLAY_VER_BIT(d) BIT_ULL(d)
+#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
+#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
#define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
2021-10-07 20:35 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
2021-10-13 20:17 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
Move the function retrieving the format override information for a given
format/modifier to intel_fb.c. We can store a pointer to the format list
in each modifier's descriptor instead of the corresponding switch/case
logic, avoiding the listing of the modifiers twice.
v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
userspace.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 132 +--------------
drivers/gpu/drm/i915/display/intel_fb.c | 163 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 3 +
3 files changed, 167 insertions(+), 131 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbba..90802d16fbf91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
*y += state->view.color_plane[color_plane].y;
}
-/*
- * From the Sky Lake PRM:
- * "The Color Control Surface (CCS) contains the compression status of
- * the cache-line pairs. The compression state of the cache-line pair
- * is specified by 2 bits in the CCS. Each CCS cache-line represents
- * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
- * cache-line-pairs. CCS is always Y tiled."
- *
- * Since cache line pairs refers to horizontally adjacent cache lines,
- * each cache line in the CCS corresponds to an area of 32x16 cache
- * lines on the main surface. Since each pixel is 4 bytes, this gives
- * us a ratio of one byte in the CCS for each 8x16 pixels in the
- * main surface.
- */
-static const struct drm_format_info skl_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
- .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
-};
-
-/*
- * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
- * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
- * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
- * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
- * the main surface.
- */
-static const struct drm_format_info gen12_ccs_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_YUYV, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_YVYU, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_UYVY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_VYUY, .num_planes = 2,
- .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 2, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
- .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
- .hsub = 1, .vsub = 1, .is_yuv = true },
- { .format = DRM_FORMAT_NV12, .num_planes = 4,
- .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P010, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P012, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
- { .format = DRM_FORMAT_P016, .num_planes = 4,
- .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
- .hsub = 2, .vsub = 2, .is_yuv = true },
-};
-
-/*
- * Same as gen12_ccs_formats[] above, but with additional surface used
- * to pass Clear Color information in plane 2 with 64 bits of data.
- */
-static const struct drm_format_info gen12_ccs_cc_formats[] = {
- { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, },
- { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
- { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
- .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
- .hsub = 1, .vsub = 1, .has_alpha = true },
-};
-
-static const struct drm_format_info *
-lookup_format_info(const struct drm_format_info formats[],
- int num_formats, u32 format)
-{
- int i;
-
- for (i = 0; i < num_formats; i++) {
- if (formats[i].format == format)
- return &formats[i];
- }
-
- return NULL;
-}
-
-static const struct drm_format_info *
-intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
-{
- switch (cmd->modifier[0]) {
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Yf_TILED_CCS:
- return lookup_format_info(skl_ccs_formats,
- ARRAY_SIZE(skl_ccs_formats),
- cmd->pixel_format);
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return lookup_format_info(gen12_ccs_formats,
- ARRAY_SIZE(gen12_ccs_formats),
- cmd->pixel_format);
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- return lookup_format_info(gen12_ccs_cc_formats,
- ARRAY_SIZE(gen12_ccs_cc_formats),
- cmd->pixel_format);
- default:
- return NULL;
- }
-}
-
u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
@@ -11270,7 +11140,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
static const struct drm_mode_config_funcs intel_mode_funcs = {
.fb_create = intel_user_framebuffer_create,
- .get_format_info = intel_get_format_info,
+ .get_format_info = intel_fb_get_format_info,
.output_poll_changed = intel_fbdev_output_poll_changed,
.mode_valid = intel_mode_valid,
.atomic_check = intel_atomic_check,
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 11a4c3e81cead..920de857ffa28 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -13,9 +13,108 @@
#define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
+/*
+ * From the Sky Lake PRM:
+ * "The Color Control Surface (CCS) contains the compression status of
+ * the cache-line pairs. The compression state of the cache-line pair
+ * is specified by 2 bits in the CCS. Each CCS cache-line represents
+ * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
+ * cache-line-pairs. CCS is always Y tiled."
+ *
+ * Since cache line pairs refers to horizontally adjacent cache lines,
+ * each cache line in the CCS corresponds to an area of 32x16 cache
+ * lines on the main surface. Since each pixel is 4 bytes, this gives
+ * us a ratio of one byte in the CCS for each 8x16 pixels in the
+ * main surface.
+ */
+static const struct drm_format_info skl_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
+};
+
+/*
+ * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
+ * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
+ * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
+ * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
+ * the main surface.
+ */
+static const struct drm_format_info gen12_ccs_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_YUYV, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_YVYU, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_UYVY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_VYUY, .num_planes = 2,
+ .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
+ .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+ .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_NV12, .num_planes = 4,
+ .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P010, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P012, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+ { .format = DRM_FORMAT_P016, .num_planes = 4,
+ .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
+ .hsub = 2, .vsub = 2, .is_yuv = true },
+};
+
+/*
+ * Same as gen12_ccs_formats[] above, but with additional surface used
+ * to pass Clear Color information in plane 2 with 64 bits of data.
+ */
+static const struct drm_format_info gen12_ccs_cc_formats[] = {
+ { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, },
+ { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+ { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
+ .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
+#define FORMAT_OVERRIDE(format_list) \
+ .formats = format_list, \
+ .format_count = ARRAY_SIZE(format_list)
+
const struct intel_modifier_desc {
u64 id;
u64 display_versions;
+ const struct drm_format_info *formats;
+ int format_count;
u8 is_linear:1;
struct {
@@ -49,33 +148,97 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(skl_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Yf_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(skl_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_RC,
+
+ FORMAT_OVERRIDE(gen12_ccs_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_RC_CC,
+
+ FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
.ccs.type = INTEL_CCS_MC,
+
+ FORMAT_OVERRIDE(gen12_ccs_formats),
},
};
+static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
+ if (intel_modifiers[i].id == modifier)
+ return &intel_modifiers[i];
+
+ return NULL;
+}
+
+static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
+{
+ const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
+
+ if (WARN_ON(!md))
+ return &intel_modifiers[0];
+
+ return md;
+}
+
+static const struct drm_format_info *
+lookup_format_info(const struct drm_format_info formats[],
+ int num_formats, u32 format)
+{
+ int i;
+
+ for (i = 0; i < num_formats; i++) {
+ if (formats[i].format == format)
+ return &formats[i];
+ }
+
+ return NULL;
+}
+
+/**
+ * intel_fb_get_format_info: Get a modifier specific format information
+ * @cmd: FB add command structure
+ *
+ * Returns:
+ * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
+ * or %NULL if the modifier doesn't override the format.
+ */
+const struct drm_format_info *
+intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
+{
+ const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
+
+ if (!md || !md->formats)
+ return NULL;
+
+ return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
+}
+
static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
{
return md->ccs.type & ccs_type;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 5bff88ccb9372..a87c58a3219cd 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -39,6 +39,9 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
+const struct drm_format_info *
+intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
+
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 03/11] drm/i915: Add tiling attribute to the modifier descriptor
2021-10-07 20:35 ` [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
2021-10-13 20:18 ` [Intel-gfx] [PATCH " Ville Syrjälä
1 sibling, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
Add a tiling atttribute to the modifier descriptor, which let's us
get the tiling without listing the modifiers twice.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 920de857ffa28..c15d17d2983d4 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -116,6 +116,7 @@ const struct intel_modifier_desc {
const struct drm_format_info *formats;
int format_count;
u8 is_linear:1;
+ u8 tiling;
struct {
#define INTEL_CCS_RC BIT(0)
@@ -134,10 +135,12 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_X_TILED,
.display_versions = DISPLAY_VER_MASK_ALL,
+ .tiling = I915_TILING_X,
},
{
.id = I915_FORMAT_MOD_Y_TILED,
.display_versions = DISPLAY_VER_MASK(9, 13),
+ .tiling = I915_TILING_Y,
},
{
.id = I915_FORMAT_MOD_Yf_TILED,
@@ -146,6 +149,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_CCS,
.display_versions = DISPLAY_VER_MASK(9, 11),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -162,6 +166,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
@@ -170,6 +175,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
@@ -178,6 +184,7 @@ const struct intel_modifier_desc {
{
.id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
.display_versions = DISPLAY_VER_MASK(12, 13),
+ .tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
@@ -529,18 +536,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
{
- switch (fb_modifier) {
- case I915_FORMAT_MOD_X_TILED:
- return I915_TILING_X;
- case I915_FORMAT_MOD_Y_TILED:
- case I915_FORMAT_MOD_Y_TILED_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
- case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
- case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- return I915_TILING_Y;
- default:
- return I915_TILING_NONE;
- }
+ return lookup_modifier(fb_modifier)->tiling;
}
unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 05/11] drm/i915: Unexport is_semiplanar_uv_plane()
2021-10-07 20:35 ` [Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
This function is only used by intel_fb.c, so unexport it.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index c15d17d2983d4..2523d5baf59ae 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -345,7 +345,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
plane == 2;
}
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
+static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
{
return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
color_plane == 1;
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index a87c58a3219cd..65b5dd9468ff2 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -33,7 +33,6 @@ enum intel_plane_caps {
bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane
2021-10-07 20:35 ` [Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
On future platforms the index of the color-clear plane will change from
the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve
the index independently of the platform/modifier.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++---
drivers/gpu/drm/i915/display/intel_fb.c | 25 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
3 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8043a9fd665a5..bfb9120cb31ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -10031,10 +10031,14 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
struct drm_framebuffer *fb = plane_state->hw.fb;
+ int cc_plane;
int ret;
- if (!fb ||
- fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (!fb)
+ continue;
+
+ cc_plane = intel_fb_rc_ccs_cc_plane(fb);
+ if (cc_plane < 0)
continue;
/*
@@ -10051,7 +10055,7 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
* GPU write on it.
*/
ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
- fb->offsets[2] + 16,
+ fb->offsets[cc_plane] + 16,
&plane_state->ccval,
sizeof(plane_state->ccval));
/* The above could only fail if the FB obj has an unexpected backing store type. */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index bca9176e3e905..ead1f69a1873c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -125,6 +125,7 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
+ u8 cc_planes:3;
} ccs;
} intel_modifiers[] = {
{
@@ -178,6 +179,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
},
@@ -369,10 +371,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
}
+/**
+ * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
+ * @fb: Framebuffer
+ *
+ * Returns:
+ * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
+ * framebuffer using a render compression/color clear modifier.
+ */
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ if (!md->ccs.cc_planes)
+ return -1;
+
+ drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
+
+ return ilog2((int)md->ccs.cc_planes);
+}
+
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
- return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC &&
- plane == 2;
+ return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 442d8d084f100..7bcfc5517a2e7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -34,6 +34,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
+int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
+
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps);
bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-07 20:35 ` [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for " Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
2021-10-13 20:27 ` [Intel-gfx] [PATCH " Ville Syrjälä
1 sibling, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
Future platforms change the location of CCS control planes in CCS
framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
planes independently of the platform. This function can be used
everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
since all the callers are only interested in control planes (and not CCS
color-clear planes).
Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
used everywhere instead of is_gen12_ccs_plane(), based on the above
explanation.
This change also unexports the is_gen12_ccs_modifier(),
is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
used in intel_fb.c
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 7 --
drivers/gpu/drm/i915/display/intel_fb.c | 73 ++++++++++++++-----
drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
.../drm/i915/display/skl_universal_plane.c | 3 +-
4 files changed, 56 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bb53b01f07aee..b4b6a31caf4e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
-static inline bool is_gen12_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index d2491a73d255b..85a2eaaa7cad8 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -126,6 +126,8 @@ const struct intel_modifier_desc {
#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
u8 type:3;
u8 cc_planes:3;
+ u8 packed_ctrl_planes:4;
+ u8 planar_ctrl_planes:4;
} ccs;
} intel_modifiers[] = {
{
@@ -153,6 +155,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -161,6 +164,7 @@ const struct intel_modifier_desc {
.display_versions = DISPLAY_VER_MASK(9, 11),
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(skl_ccs_formats),
},
@@ -170,6 +174,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC,
+ .ccs.packed_ctrl_planes = BIT(1),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -179,6 +184,7 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_RC_CC,
+ .ccs.packed_ctrl_planes = BIT(1),
.ccs.cc_planes = BIT(2),
FORMAT_OVERRIDE(gen12_ccs_cc_formats),
@@ -189,6 +195,8 @@ const struct intel_modifier_desc {
.tiling = I915_TILING_Y,
.ccs.type = INTEL_CCS_MC,
+ .ccs.packed_ctrl_planes = BIT(1),
+ .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
FORMAT_OVERRIDE(gen12_ccs_formats),
},
@@ -358,17 +366,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
}
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
+static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
+ const struct drm_format_info *format)
{
- if (!is_ccs_modifier(fb->modifier))
- return false;
+ if (format_is_yuv_semiplanar(md, format))
+ return md->ccs.planar_ctrl_planes;
+ else
+ return md->ccs.packed_ctrl_planes;
+}
+
+/**
+ * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a CCS control plane.
+ */
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
+{
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
- return plane >= fb->format->num_planes / 2;
+ return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
+/**
+ * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer color plane is a GEN12 CCS control plane
+ * @fb: Framebuffer
+ * @plane: color plane index to check
+ *
+ * Returns:
+ * Returns %true if @fb's color plane at index @plane is a GEN12 CCS control plane.
+ */
+static bool intel_fb_is_gen12_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
{
- return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
+ const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
+
+ return md->display_versions & (DISPLAY_VER_MASK(12, 13)) &&
+ ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
}
/**
@@ -391,7 +426,7 @@ int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
return ilog2((int)md->ccs.cc_planes);
}
-bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
+static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
{
return intel_fb_rc_ccs_cc_plane(fb) == plane;
}
@@ -405,7 +440,7 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p
bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
{
return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
- is_gen12_ccs_plane(fb, color_plane) ||
+ intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane) ||
is_gen12_ccs_cc_plane(fb, color_plane);
}
@@ -493,13 +528,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_Y_TILED_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 128;
fallthrough;
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
- if (is_ccs_plane(fb, color_plane) ||
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane) ||
is_gen12_ccs_cc_plane(fb, color_plane))
return 64;
fallthrough;
@@ -509,7 +544,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
else
return 512;
case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 128;
fallthrough;
case I915_FORMAT_MOD_Yf_TILED:
@@ -565,7 +600,7 @@ static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_pl
{
intel_tile_dims(fb, color_plane, tile_width, tile_height);
- if (is_gen12_ccs_plane(fb, color_plane))
+ if (intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane))
*tile_height = 1;
}
@@ -626,7 +661,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
return 512 * 4096;
/* AUX_DIST needs only 4K alignment */
- if (is_ccs_plane(fb, color_plane))
+ if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
return 4096;
if (is_semiplanar_uv_plane(fb, color_plane)) {
@@ -685,7 +720,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
* TODO: Deduct the subsampling from the char block for all CCS
* formats and planes.
*/
- if (!is_gen12_ccs_plane(fb, color_plane)) {
+ if (!intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane)) {
*hsub = fb->format->hsub;
*vsub = fb->format->vsub;
@@ -713,7 +748,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
{
struct drm_i915_private *i915 = to_i915(fb->base.dev);
- int main_plane = is_ccs_plane(&fb->base, color_plane) ?
+ int main_plane = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ?
skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
unsigned int main_width = fb->base.width;
unsigned int main_height = fb->base.height;
@@ -726,7 +761,7 @@ static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_pl
* stride in the allocated FB object may not be power-of-two
* sized, in which case it is auto-padded to the POT size.
*/
- if (IS_ALDERLAKE_P(i915) && is_ccs_plane(&fb->base, color_plane))
+ if (IS_ALDERLAKE_P(i915) && intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane))
main_width = gen12_aligned_scanout_stride(fb, 0) /
fb->base.format->cpp[0];
@@ -965,7 +1000,7 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane
int ccs_x, ccs_y;
int main_x, main_y;
- if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
+ if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
return 0;
/*
@@ -1169,7 +1204,7 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
unsigned int pitch_tiles)
{
if (intel_fb_needs_pot_stride_remap(fb)) {
- unsigned int min_stride = is_ccs_plane(&fb->base, color_plane) ? 2 : 8;
+ unsigned int min_stride = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ? 2 : 8;
/*
* ADL_P, the only platform needing a POT stride has a minimum
* of 8 main surface and 2 CCS AUX stride tiles.
@@ -1785,7 +1820,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
+ if (intel_fb_is_gen12_ccs_ctrl_plane(fb, i)) {
int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
if (fb->pitches[i] != ccs_aux_stride) {
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 7bcfc5517a2e7..11b37a1acb7bb 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -30,10 +30,7 @@ enum intel_plane_caps {
PLANE_HAS_CCS_MC = BIT(2),
};
-bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
-bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
-bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
-
+bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index a2f89be146212..5fa05231a37a7 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1607,8 +1607,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int hsub, vsub;
int x, y;
- if (!is_ccs_plane(fb, ccs_plane) ||
- is_gen12_ccs_cc_plane(fb, ccs_plane))
+ if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
continue;
intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c
2021-10-07 20:35 ` [Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
Move the function to intel_fb.c and rename it adding the intel_fb_
prefix following the naming of exported functions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 9 ------
drivers/gpu/drm/i915/display/intel_fb.c | 29 ++++++++++++++-----
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 12 ++++----
4 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b4b6a31caf4e3..f38b70ef6afaa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2041,13 +2041,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
-static inline bool is_ccs_modifier(u64 modifier)
-{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
- modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
-}
-
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 85a2eaaa7cad8..cf84b1ce6a485 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -261,6 +261,19 @@ static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_ty
return md->ccs.type & ccs_type;
}
+/**
+ * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render, render with color clear or
+ * media compression modifier.
+ */
+bool intel_fb_is_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
@@ -446,7 +459,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
(main_plane && main_plane >= fb->format->num_planes / 2));
return fb->format->num_planes / 2 + main_plane;
@@ -454,7 +467,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
{
- drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||
+ drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
ccs_plane < fb->format->num_planes / 2);
if (is_gen12_ccs_cc_plane(fb, ccs_plane))
@@ -499,7 +512,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
{
struct drm_i915_private *i915 = to_i915(fb->dev);
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return main_to_ccs_plane(fb, main_plane);
else if (DISPLAY_VER(i915) < 11 &&
intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
@@ -1063,7 +1076,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
* The new CCS hash mode isn't compatible with remapping as
* the virtual address of the pages affects the compressed data.
*/
- if (is_ccs_modifier(fb->modifier))
+ if (intel_fb_is_ccs_modifier(fb->modifier))
return false;
/* Linear needs a page aligned stride for remapping */
@@ -1470,7 +1483,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier));
+ drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
/* Make src coordinates relative to the viewport */
drm_rect_translate(&plane_state->uapi.src,
@@ -1533,7 +1546,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
*
* The new CCS hash mode makes remapping impossible
*/
- if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) ||
+ if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
intel_modifier_uses_dpt(dev_priv, modifier))
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
else if (DISPLAY_VER(dev_priv) >= 7)
@@ -1558,14 +1571,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
* we need the stride to be page aligned.
*/
if (fb->pitches[color_plane] > max_stride &&
- !is_ccs_modifier(fb->modifier))
+ !intel_fb_is_ccs_modifier(fb->modifier))
return intel_tile_size(dev_priv);
else
return 64;
}
tile_width = intel_tile_width_bytes(fb, color_plane);
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
/*
* On ADL-P the stride must be either 8 tiles or a stride
* that is aligned to 16 tiles, required by the 16 tiles =
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index 11b37a1acb7bb..b05c3f64b6f0c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -30,6 +30,8 @@ enum intel_plane_caps {
PLANE_HAS_CCS_MC = BIT(2),
};
+bool intel_fb_is_ccs_modifier(u64 modifier);
+
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 5fa05231a37a7..82dd3c0cc49ea 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1188,7 +1188,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return 0;
if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
- is_ccs_modifier(fb->modifier)) {
+ intel_fb_is_ccs_modifier(fb->modifier)) {
drm_dbg_kms(&dev_priv->drm,
"RC support only with 0/180 degree rotation (%x)\n",
rotation);
@@ -1487,7 +1487,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
* CCS AUX surface doesn't have its own x/y offsets, we must make sure
* they match with the main surface x/y offsets.
*/
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
while (!skl_check_main_ccs_coordinates(plane_state, x, y,
offset, aux_plane)) {
if (offset == 0)
@@ -1551,7 +1551,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
offset = intel_plane_compute_aligned_offset(&x, &y,
plane_state, uv_plane);
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
int ccs_plane = main_to_ccs_plane(fb, uv_plane);
u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
u32 alignment = intel_surf_alignment(fb, uv_plane);
@@ -1649,7 +1649,7 @@ static int skl_check_plane_surface(struct intel_plane_state *plane_state)
* Handle the AUX surface first since the main surface setup depends on
* it.
*/
- if (is_ccs_modifier(fb->modifier)) {
+ if (intel_fb_is_ccs_modifier(fb->modifier)) {
ret = skl_check_ccs_aux_surface(plane_state);
if (ret)
return ret;
@@ -1833,7 +1833,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
- if (is_ccs_modifier(modifier))
+ if (intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
@@ -1887,7 +1887,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_ABGR8888:
- if (is_ccs_modifier(modifier))
+ if (intel_fb_is_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_YUYV:
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] [PATCH v2 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
2021-10-07 20:35 ` [Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak
@ 2021-10-08 0:19 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-08 0:19 UTC (permalink / raw)
To: intel-gfx
Instead of open-coding the checks add functions for this, simplifying
the handling of CCS modifiers on future platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 24 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_fb.h | 2 ++
.../drm/i915/display/skl_universal_plane.c | 4 ++--
3 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index cf84b1ce6a485..da8cc5e47aa1b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -274,6 +274,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier)
return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY);
}
+/**
+ * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a render with color clear modifier.
+ */
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC);
+}
+
+/**
+ * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
+ * @modifier: Modifier to check
+ *
+ * Returns:
+ * Returns %true if @modifier is a media compression modifier.
+ */
+bool intel_fb_is_mc_ccs_modifier(u64 modifier)
+{
+ return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC);
+}
+
static bool plane_has_modifier(struct drm_i915_private *i915,
enum intel_plane_caps plane_caps,
const struct intel_modifier_desc *md)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index b05c3f64b6f0c..c39bf840edb2c 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -31,6 +31,8 @@ enum intel_plane_caps {
};
bool intel_fb_is_ccs_modifier(u64 modifier);
+bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);
+bool intel_fb_is_mc_ccs_modifier(u64 modifier);
bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 82dd3c0cc49ea..e3346da4884d1 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1067,7 +1067,7 @@ skl_program_plane(struct intel_plane *plane,
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
- if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)
+ if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier))
intel_uncore_write64_fw(&dev_priv->uncore,
PLANE_CC_VAL(pipe, plane_id), plane_state->ccval);
@@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
case DRM_FORMAT_P010:
case DRM_FORMAT_P012:
case DRM_FORMAT_P016:
- if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)
+ if (intel_fb_is_mc_ccs_modifier(modifier))
return true;
fallthrough;
case DRM_FORMAT_RGB565:
--
2.27.0
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev9)
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (13 preceding siblings ...)
2021-10-07 21:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-10-08 0:34 ` Patchwork
2021-10-08 0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-08 0:34 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Simplify handling of modifiers (rev9)
URL : https://patchwork.freedesktop.org/series/95579/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bdfa60b8fbc5 drm/i915: Add a table with a descriptor for all i915 modifiers
e97b1f8c3ad0 drm/i915: Move intel_get_format_info() to intel_fb.c
-:267: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'format_list' - possible side-effects?
#267: FILE: drivers/gpu/drm/i915/display/intel_fb.c:109:
+#define FORMAT_OVERRIDE(format_list) \
+ .formats = format_list, \
+ .format_count = ARRAY_SIZE(format_list)
total: 0 errors, 0 warnings, 1 checks, 358 lines checked
06b0cc3e787d drm/i915: Add tiling attribute to the modifier descriptor
bc77c73f768e drm/i915: Simplify the modifier check for interlaced scanout support
5cd326dde5f2 drm/i915: Unexport is_semiplanar_uv_plane()
5282dd95ba72 drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
a143347efd15 drm/i915: Add a platform independent way to get the RC CCS CC plane
749c3e2b2297 drm/i915: Handle CCS CC planes separately from CCS control planes
5af0a07cd551 drm/i915: Add a platform independent way to check for CCS control planes
-:247: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#247: FILE: drivers/gpu/drm/i915/display/intel_fb.c:1207:
+ unsigned int min_stride = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ? 2 : 8;
total: 0 errors, 1 warnings, 0 checks, 228 lines checked
69716ae77a44 drm/i915: Move is_ccs_modifier() to intel_fb.c
cd25a5607e73 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Simplify handling of modifiers (rev9)
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (14 preceding siblings ...)
2021-10-08 0:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev9) Patchwork
@ 2021-10-08 0:35 ` Patchwork
2021-10-08 1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-08 0:35 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Simplify handling of modifiers (rev9)
URL : https://patchwork.freedesktop.org/series/95579/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_fb.c:132:3: warning: symbol 'intel_modifiers' was not declared. Should it be static?
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Simplify handling of modifiers (rev9)
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (15 preceding siblings ...)
2021-10-08 0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-10-08 1:06 ` Patchwork
2021-10-08 2:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-13 19:41 ` [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Juha-Pekka Heikkila
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-08 1:06 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6660 bytes --]
== Series Details ==
Series: drm/i915: Simplify handling of modifiers (rev9)
URL : https://patchwork.freedesktop.org/series/95579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10696 -> Patchwork_21287
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/index.html
Known issues
------------
Here are the changes found in Patchwork_21287 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-skl-6700k2: NOTRUN -> [SKIP][1] ([fdo#109271]) +31 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html
* igt@core_hotunplug@unbind-rebind:
- fi-bwr-2160: [PASS][2] -> [FAIL][3] ([i915#3194])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6700k2: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html
* igt@i915_selftest@live@gt_lrc:
- fi-bsw-n3050: [PASS][5] -> [DMESG-FAIL][6] ([i915#2373])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-bsw-n3050/igt@i915_selftest@live@gt_lrc.html
* igt@kms_flip@basic-flip-vs-modeset@c-dp1:
- fi-cfl-8109u: [PASS][7] -> [FAIL][8] ([i915#4165]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#295]) +18 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6700k2: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-1115g4: [FAIL][12] ([i915#1888]) -> [PASS][13] +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
- fi-skl-6700k2: [INCOMPLETE][14] ([i915#146] / [i915#198]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-skl-6700k2/igt@gem_exec_suspend@basic-s3.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-r: [DMESG-FAIL][16] ([i915#2291] / [i915#541]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-kbl-r/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-gt1}: [DMESG-WARN][18] ([i915#3303]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (44 -> 37)
------------------------------
Missing (7): fi-ilk-m540 bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 bat-jsl-1
Build changes
-------------
* Linux: CI_DRM_10696 -> Patchwork_21287
CI-20190529: 20190529
CI_DRM_10696: 58a206ae5bf2f81a11e4408d10a3e1b445d6eebb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6237: 910b5caac6625d2bf0b6c1dde502451431bd0159 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21287: cd25a5607e73c768362e3f40ab1638f90a6f086b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
cd25a5607e73 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
69716ae77a44 drm/i915: Move is_ccs_modifier() to intel_fb.c
5af0a07cd551 drm/i915: Add a platform independent way to check for CCS control planes
749c3e2b2297 drm/i915: Handle CCS CC planes separately from CCS control planes
a143347efd15 drm/i915: Add a platform independent way to get the RC CCS CC plane
5282dd95ba72 drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
5cd326dde5f2 drm/i915: Unexport is_semiplanar_uv_plane()
bc77c73f768e drm/i915: Simplify the modifier check for interlaced scanout support
06b0cc3e787d drm/i915: Add tiling attribute to the modifier descriptor
e97b1f8c3ad0 drm/i915: Move intel_get_format_info() to intel_fb.c
bdfa60b8fbc5 drm/i915: Add a table with a descriptor for all i915 modifiers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/index.html
[-- Attachment #2: Type: text/html, Size: 7724 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Simplify handling of modifiers (rev9)
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (16 preceding siblings ...)
2021-10-08 1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2021-10-08 2:15 ` Patchwork
2021-10-13 19:41 ` [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Juha-Pekka Heikkila
18 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2021-10-08 2:15 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30270 bytes --]
== Series Details ==
Series: drm/i915: Simplify handling of modifiers (rev9)
URL : https://patchwork.freedesktop.org/series/95579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10696_full -> Patchwork_21287_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21287_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21287_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21287_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_invalid_mode@clock-too-high:
- shard-tglb: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-c:
- shard-tglb: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb1/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb8/igt@kms_universal_plane@cursor-fb-leak-pipe-c.html
Known issues
------------
Here are the changes found in Patchwork_21287_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][4] ([fdo#111827])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb5/igt@feature_discovery@chamelium.html
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb5/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-args:
- shard-tglb: NOTRUN -> [SKIP][8] ([i915#280])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@in-flight-suspend:
- shard-apl: NOTRUN -> [DMESG-WARN][9] ([i915#180]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@unwedge-stress:
- shard-skl: [PASS][10] -> [TIMEOUT][11] ([i915#2369] / [i915#3063])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl3/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl4/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][12] ([i915#3354])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglb: NOTRUN -> [FAIL][15] ([i915#2842]) +3 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_reloc@basic-write-gtt:
- shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl1/igt@gem_exec_reloc@basic-write-gtt.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl8/igt@gem_exec_reloc@basic-write-gtt.html
* igt@gem_exec_whisper@basic-contexts:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#118])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk2/igt@gem_exec_whisper@basic-contexts.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-glk1/igt@gem_exec_whisper@basic-contexts.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][22] ([i915#2658]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@gem_pread@exhaustion.html
- shard-snb: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb5/igt@gem_pread@exhaustion.html
- shard-skl: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl4/igt@gem_pread@exhaustion.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#4270]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109312])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_sync@basic-many-each:
- shard-snb: NOTRUN -> [INCOMPLETE][27] ([i915#2055])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb5/igt@gem_sync@basic-many-each.html
- shard-kbl: [PASS][28] -> [INCOMPLETE][29] ([i915#4274])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl2/igt@gem_sync@basic-many-each.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@gem_sync@basic-many-each.html
- shard-iclb: [PASS][30] -> [INCOMPLETE][31] ([i915#4274])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@gem_sync@basic-many-each.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-iclb4/igt@gem_sync@basic-many-each.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][32] ([i915#3002])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl7/igt@gem_userptr_blits@input-checking.html
- shard-snb: NOTRUN -> [DMESG-WARN][33] ([i915#3002])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@readonly-unsync:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#3297])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gem_userptr_blits@readonly-unsync.html
* igt@gen3_render_linear_blits:
- shard-tglb: NOTRUN -> [SKIP][35] ([fdo#109289]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@bb-start-param:
- shard-tglb: NOTRUN -> [SKIP][36] ([i915#2856]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: NOTRUN -> [FAIL][37] ([i915#454])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111644] / [i915#1397] / [i915#2411])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb5/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-pc8-residency-stress:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#109506] / [i915#2411])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@i915_pm_rpm@modeset-pc8-residency-stress.html
* igt@i915_query@query-topology-unsupported:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109302])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@i915_query@query-topology-unsupported.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#111614])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-tglb: NOTRUN -> [SKIP][43] ([fdo#111615]) +8 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3689]) +12 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +10 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][46] ([fdo#109271]) +282 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb6/igt@kms_ccs@pipe-b-bad-pixel-format-y_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl1/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3689] / [i915#3886]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +10 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-tglb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +10 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +5 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +9 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-0-75.html
* igt@kms_content_protection@atomic-dpms:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#111828])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb5/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][55] ([i915#1319])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][56] ([i915#2105])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3359]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109279] / [i915#3359]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
* igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen:
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271]) +74 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#2828] / [i915#456])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3319]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111825]) +44 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [PASS][64] -> [FAIL][65] ([i915#2346] / [i915#533])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#4103])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-tglb: NOTRUN -> [SKIP][68] ([i915#3788])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a.html
* igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][69] -> [FAIL][70] ([i915#2122])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-glk4/igt@kms_flip@2x-plain-flip-ts-check@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +6 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-iclb: [PASS][73] -> [SKIP][74] ([i915#3701])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-snb: [PASS][75] -> [SKIP][76] ([fdo#109271])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +23 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][78] -> [FAIL][79] ([i915#1188])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl1/igt@kms_hdr@bpc-switch.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl8/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#533]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#658])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][83] ([fdo#109271] / [i915#658]) +5 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#2920]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-tglb: NOTRUN -> [FAIL][85] ([i915#132] / [i915#3467]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][86] -> [SKIP][87] ([fdo#109441]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-iclb5/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-skl: [PASS][88] -> [INCOMPLETE][89] ([i915#198])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl9/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl2/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-source-outp-complete:
- shard-tglb: NOTRUN -> [SKIP][91] ([i915#2530]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@nouveau_crc@pipe-c-source-outp-complete.html
* igt@perf@polling:
- shard-skl: [PASS][92] -> [FAIL][93] ([i915#1542])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl6/igt@perf@polling.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl5/igt@perf@polling.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][94] -> [FAIL][95] ([i915#1722])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl8/igt@perf@polling-small-buf.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl2/igt@perf@polling-small-buf.html
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +172 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl8/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][97] ([fdo#109291]) +4 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@prime_nv_pcopy@test3_1.html
* igt@prime_vgem@fence-read-hang:
- shard-tglb: NOTRUN -> [SKIP][98] ([fdo#109295]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@prime_vgem@fence-read-hang.html
* igt@sysfs_clients@create:
- shard-tglb: NOTRUN -> [SKIP][99] ([i915#2994]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-1:
- shard-apl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl3/igt@sysfs_clients@fair-1.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][101] ([i915#2842]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [FAIL][103] ([i915#2842]) -> [PASS][104] +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl3/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][105] ([i915#2842]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][107] ([i915#2842]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_sync@basic-many-each:
- shard-apl: [INCOMPLETE][109] ([i915#4274]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl1/igt@gem_sync@basic-many-each.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl7/igt@gem_sync@basic-many-each.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [FAIL][111] ([i915#4275]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-iclb5/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][113] ([i915#3921]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-snb2/igt@i915_selftest@live@hangcheck.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@forcewake:
- shard-tglb: [INCOMPLETE][115] ([i915#2411] / [i915#456]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@i915_suspend@forcewake.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@i915_suspend@forcewake.html
* igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a:
- shard-skl: [DMESG-WARN][117] ([i915#1982]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl7/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl10/igt@kms_atomic_transition@plane-use-after-nonblocking-unbind-fencing@edp-1-pipe-a.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][119] ([i915#118]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-glk6/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-glk3/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][121] ([i915#180]) -> [PASS][122] +4 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [INCOMPLETE][123] ([i915#2411] / [i915#4211]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][125] ([i915#79]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][127] ([i915#180] / [i915#1982]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl6/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@a-edp1:
- shard-tglb: [INCOMPLETE][129] ([i915#456]) -> [PASS][130] +1 similar issue
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@kms_flip@flip-vs-suspend@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-skl: [FAIL][131] ([i915#2122]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl5/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][133] ([i915#1188]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [DMESG-WARN][135] ([i915#180]) -> [PASS][136] +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-apl1/igt@kms_hdr@bpc-switch-suspend.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-apl7/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-tglb: [INCOMPLETE][137] ([i915#4182]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10696/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][139] ([fdo#108145] / [i915#265]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/d
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21287/index.html
[-- Attachment #2: Type: text/html, Size: 33580 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 22:00 ` Imre Deak
@ 2021-10-08 9:41 ` Ville Syrjälä
0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-08 9:41 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 01:00:06AM +0300, Imre Deak wrote:
> On Fri, Oct 08, 2021 at 12:32:57AM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 08, 2021 at 12:26:11AM +0300, Imre Deak wrote:
> > > On Fri, Oct 08, 2021 at 12:10:00AM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 07, 2021 at 11:35:07PM +0300, Imre Deak wrote:
> > > > > Add a table describing all the framebuffer modifiers used by i915 at one
> > > > > place. This has the benefit of deduplicating the listing of supported
> > > > > modifiers for each platform and checking the support of these modifiers
> > > > > on a given plane. This also simplifies in a similar way getting some
> > > > > attribute for a modifier, for instance checking if the modifier is a
> > > > > CCS modifier type.
> > > > >
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > > > > .../drm/i915/display/intel_display_types.h | 1 -
> > > > > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> > > > > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > > > > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > > > > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > > > > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> > > > > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > > > > 8 files changed, 218 insertions(+), 164 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > > > > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > > > > DRM_FORMAT_ARGB8888,
> > > > > };
> > > > >
> > > > > -static const u64 cursor_format_modifiers[] = {
> > > > > - DRM_FORMAT_MOD_LINEAR,
> > > > > - DRM_FORMAT_MOD_INVALID
> > > > > -};
> > > > > -
> > > > > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > > > > {
> > > > > struct drm_i915_private *dev_priv =
> > > > > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > > > > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > > > > u32 format, u64 modifier)
> > > > > {
> > > > > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > > > > - format == DRM_FORMAT_ARGB8888;
> > > > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > > > > + return false;
> > > > > +
> > > > > + return format == DRM_FORMAT_ARGB8888;
> > > > > }
> > > > >
> > > > > static int
> > > > > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > > > {
> > > > > struct intel_plane *cursor;
> > > > > int ret, zpos;
> > > > > + u64 *modifiers;
> > > > >
> > > > > cursor = intel_plane_alloc();
> > > > > if (IS_ERR(cursor))
> > > > > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > > > > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > > > > cursor->cursor.size = ~0;
> > > > >
> > > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > > > > +
> > > > > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > > > > 0, &intel_cursor_plane_funcs,
> > > > > intel_cursor_formats,
> > > > > ARRAY_SIZE(intel_cursor_formats),
> > > > > - cursor_format_modifiers,
> > > > > + modifiers,
> > > > > DRM_PLANE_TYPE_CURSOR,
> > > > > "cursor %c", pipe_name(pipe));
> > > > > +
> > > > > + kfree(modifiers);
> > > > > +
> > > > > if (ret)
> > > > > goto fail;
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 21ce8bccc645a..bb53b01f07aee 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > > > > enum plane_id id;
> > > > > enum pipe pipe;
> > > > > bool has_fbc;
> > > > > - bool has_ccs;
> > > > > bool need_async_flip_disable_wa;
> > > > > u32 frontbuffer_bit;
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > index fa1f375e696bf..aefae988b620b 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > > > @@ -13,6 +13,184 @@
> > > > >
> > > > > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> > > > >
> > > > > +const struct intel_modifier_desc {
> > > > > + u64 id;
> > > > > + u64 display_versions;
> > > > > +
> > > > > + struct {
> > > > > +#define INTEL_CCS_RC BIT(0)
> > > > > +#define INTEL_CCS_RC_CC BIT(1)
> > > > > +#define INTEL_CCS_MC BIT(2)
> > > > > +
> > > > > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > > > > + u8 type:3;
> > > > > + } ccs;
> > > > > +} intel_modifiers[] = {
> > > > > + {
> > > > > + .id = DRM_FORMAT_MOD_LINEAR,
> > > > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_X_TILED,
> > > > > + .display_versions = DISPLAY_VER_MASK_ALL,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Y_TILED,
> > > > > + .display_versions = DISPLAY_VER_MASK(9, 13),
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Yf_TILED,
> > > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > > +
> > > > > + .ccs.type = INTEL_CCS_RC,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > > > > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > > > > +
> > > > > + .ccs.type = INTEL_CCS_RC,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > > +
> > > > > + .ccs.type = INTEL_CCS_RC,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > > +
> > > > > + .ccs.type = INTEL_CCS_RC_CC,
> > > > > + },
> > > > > + {
> > > > > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > > > > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > > > > +
> > > > > + .ccs.type = INTEL_CCS_MC,
> > > > > + },
> > > > > +};
> > > > > +
> > > > > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > > > > +{
> > > > > + return md->ccs.type & ccs_type;
> > > > > +}
> > > > > +
> > > > > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > > > > + enum pipe pipe, enum plane_id plane_id)
> > > > > +{
> > > > > + if (plane_id == PLANE_CURSOR)
> > > > > + return false;
> > > > > +
> > > > > + /* Wa_22011186057 */
> > > > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > > > > + return false;
> > > > > +
> > > > > + if (DISPLAY_VER(i915) >= 11)
> > > > > + return true;
> > > > > +
> > > > > + if (IS_GEMINILAKE(i915))
> > > > > + return pipe != PIPE_C;
> > > > > +
> > > > > + return pipe != PIPE_C &&
> > > > > + (plane_id == PLANE_PRIMARY ||
> > > > > + plane_id == PLANE_SPRITE0);
> > > > > +}
> > > >
> > > > This part I don't really like. IMO the plane capabilities should
> > > > be listed in the plane code, not anywhere else.
> > >
> > > Ok. How about adding back plane->has_rc_ccs and also adding
> > > plane->has_mc_ccs and initing these before calling
> > > intel_fb_plane_get_modifiers() (as before)?
> >
> > Yeah, maybe something like that. Ie. basically reduce the full list
> > of modifiers to a set of higher level classes, which each plane could
> > declare in a more compact form. I guess we could have some kind of small
> > plane_caps structure for it this even?
>
> So also including the cursor case below something like a plane_caps enum
> with bitfields for PLANE_HAS_CCS_RC (applying to both RC and RC_CC since
> no point to differentiate even on SKL for this), PLANE_HAS_CCS_MC and
> PLANE_HAS_TILING? This enum could be just passed then to
> intel_fb_plane_get_modifiers() instead of pipe and plane_id.
I was thinking it could be a struct in case there's a need for more
than bools. Or could just stick those in the plane itself, but then
we have to pass that around before it's fully initialized. Not sure
if that's a good idea. But a bitmask would work I suppose if we don't
need anything but yes/no type of stuff.
> > We would lose the direct info in the plane code for eg. "is Yf
> > supported?",
>
> If becomes an issue could this be a new cap?
>
> > but since that's a platform wide thing I don't think
> > it's a problem. Just the info about the individual planes and their
> > special little exceptions I'd really would want in the plane code.
> >
> > > What about the
> > > plane_id == PLANE_CURSOR && md->id != DRM_FORMAT_MOD_LINEAR
> > > check in plane_has_modifier()?
> >
> > Maybe we reduce that to .has_tiling or something?
>
> So the above PLANE_HAS_TILING and to keep initialization simple an
> .linear field in intel_modifier_desc?
Yeah maybe. I probably have to see it to know if I like it
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
` (17 preceding siblings ...)
2021-10-08 2:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-10-13 19:41 ` Juha-Pekka Heikkila
18 siblings, 0 replies; 53+ messages in thread
From: Juha-Pekka Heikkila @ 2021-10-13 19:41 UTC (permalink / raw)
To: Imre Deak, intel-gfx
Set look all ok to me, including v2 patches.
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
On 7.10.2021 23.35, Imre Deak wrote:
> This patchset adds a descriptor table for all modifiers used by i915,
> which deduplicates the listing of supported modifiers during plane
> initialization and during checking for a modifier support on a plane.
> This also simplifies getting some modifier attributes like checking
> if a plane is a CCS modifier. The motivation is to make it easier to
> add and maintain new CCS modifier sets, which will be needed for at
> least ADL-P and another upcoming platform.
>
> Tested with igt/kms_plane,kms_ccs on CHV,HSW,TGL,ADLP.
>
> The patches are also avaiable at:
> https://github.com/ideak/linux/commits/modifier-descriptors
>
> Imre Deak (11):
> drm/i915: Add a table with a descriptor for all i915 modifiers
> drm/i915: Move intel_get_format_info() to intel_fb.c
> drm/i915: Add tiling attribute to the modifier descriptor
> drm/i915: Simplify the modifier check for interlaced scanout support
> drm/i915: Unexport is_semiplanar_uv_plane()
> drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
> drm/i915: Add a platform independent way to get the RC CCS CC plane
> drm/i915: Handle CCS CC planes separately from CCS control planes
> drm/i915: Add a platform independent way to check for CCS control
> planes
> drm/i915: Move is_ccs_modifier() to intel_fb.c
> drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
>
> .../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
> drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> drivers/gpu/drm/i915/display/intel_display.c | 150 +----
> drivers/gpu/drm/i915/display/intel_display.h | 4 -
> .../drm/i915/display/intel_display_types.h | 17 -
> drivers/gpu/drm/i915/display/intel_fb.c | 536 ++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_fb.h | 25 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 35 +-
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 165 +-----
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> 12 files changed, 569 insertions(+), 388 deletions(-)
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2021-10-13 20:14 ` Ville Syrjälä
2021-10-13 21:01 ` Imre Deak
2021-10-13 20:40 ` Ville Syrjälä
1 sibling, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> Add a table describing all the framebuffer modifiers used by i915 at one
> place. This has the benefit of deduplicating the listing of supported
> modifiers for each platform and checking the support of these modifiers
> on a given plane. This also simplifies in a similar way getting some
> attribute for a modifier, for instance checking if the modifier is a
> CCS modifier type.
>
> v2:
> - Keep the plane caps calculation in the plane code and pass an enum
> with these caps to intel_fb_get_modifiers(). (Ville)
> - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
> well.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
> drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> .../drm/i915/display/intel_display_types.h | 1 -
> drivers/gpu/drm/i915/display/intel_fb.c | 143 ++++++++++++++
> drivers/gpu/drm/i915/display/intel_fb.h | 16 ++
> drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 181 +++++-------------
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 9 files changed, 245 insertions(+), 184 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1439ba78f67b..a939accff7ee2 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
> DRM_FORMAT_XBGR16161616F,
> };
>
> -static const u64 i9xx_format_modifiers[] = {
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_C8:
> @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_C8:
> @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> struct intel_plane *plane;
> const struct drm_plane_funcs *plane_funcs;
> unsigned int supported_rotations;
> + const u64 *modifiers;
> const u32 *formats;
> int num_formats;
> int ret, zpos;
> @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> plane->disable_flip_done = ilk_primary_disable_flip_done;
> }
>
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
> +
> if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> formats, num_formats,
> - i9xx_format_modifiers,
> + modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "primary %c", pipe_name(pipe));
> else
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> formats, num_formats,
> - i9xx_format_modifiers,
> + modifiers,
> DRM_PLANE_TYPE_PRIMARY,
> "plane %c",
> plane_name(plane->i9xx_plane));
> +
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index f6dcb5aa63f64..1f764c6d59583 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> };
>
> -static const u64 cursor_format_modifiers[] = {
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR &&
> - format == DRM_FORMAT_ARGB8888;
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> + return false;
> +
> + return format == DRM_FORMAT_ARGB8888;
> }
>
> static int
> @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> {
> struct intel_plane *cursor;
> int ret, zpos;
> + u64 *modifiers;
>
> cursor = intel_plane_alloc();
> if (IS_ERR(cursor))
> @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> cursor->cursor.size = ~0;
>
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS);
> +
> ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> 0, &intel_cursor_plane_funcs,
> intel_cursor_formats,
> ARRAY_SIZE(intel_cursor_formats),
> - cursor_format_modifiers,
> + modifiers,
> DRM_PLANE_TYPE_CURSOR,
> "cursor %c", pipe_name(pipe));
> +
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 21ce8bccc645a..bb53b01f07aee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1336,7 +1336,6 @@ struct intel_plane {
> enum plane_id id;
> enum pipe pipe;
> bool has_fbc;
> - bool has_ccs;
> bool need_async_flip_disable_wa;
> u32 frontbuffer_bit;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index fa1f375e696bf..11a4c3e81cead 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -13,6 +13,149 @@
>
> #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
>
> +const struct intel_modifier_desc {
> + u64 id;
s/id/modifier/ ?
> + u64 display_versions;
> + u8 is_linear:1;
> +
> + struct {
> +#define INTEL_CCS_RC BIT(0)
> +#define INTEL_CCS_RC_CC BIT(1)
> +#define INTEL_CCS_MC BIT(2)
> +
> +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> + u8 type:3;
> + } ccs;
> +} intel_modifiers[] = {
> + {
> + .id = DRM_FORMAT_MOD_LINEAR,
> + .display_versions = DISPLAY_VER_MASK_ALL,
> + .is_linear = true,
> + },
> + {
> + .id = I915_FORMAT_MOD_X_TILED,
> + .display_versions = DISPLAY_VER_MASK_ALL,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED,
> + .display_versions = DISPLAY_VER_MASK(9, 13),
> + },
> + {
> + .id = I915_FORMAT_MOD_Yf_TILED,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> + .display_versions = DISPLAY_VER_MASK(9, 11),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_RC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_RC_CC,
> + },
> + {
> + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> + .display_versions = DISPLAY_VER_MASK(12, 13),
> +
> + .ccs.type = INTEL_CCS_MC,
> + },
> +};
> +
> +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> +{
> + return md->ccs.type & ccs_type;
> +}
> +
> +static bool plane_has_modifier(struct drm_i915_private *i915,
> + enum intel_plane_caps plane_caps,
> + const struct intel_modifier_desc *md)
> +{
> + if (!(DISPLAY_VER_BIT(DISPLAY_VER(i915)) & md->display_versions))
> + return false;
I guess I'd typically have the bitmask vs. the bit we're checking
the other way around. Feels a bit RPN :P
> +
> + if (!(plane_caps & PLANE_HAS_TILING) && !md->is_linear)
> + return false;
This has the plane_caps part on the left of && ...
> +
> + if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) &&
> + !(plane_caps & PLANE_HAS_CCS_RC))
> + return false;
> +
> + if (is_ccs_type_modifier(md, INTEL_CCS_MC) &&
> + !(plane_caps & PLANE_HAS_CCS_MC))
> + return false;
...these have it on the right.
My poor brain would like things to be consistent ;)
> +
> + return true;
> +}
> +
> +/**
> + * intel_fb_plane_get_modifiers: Get the modifiers supported by the given pipe and plane
> + * @i915: i915 device instance
> + * @plane_caps: capabilities for the plane the modifiers are queried for
> + *
> + * Returns:
> + * Returns the list of modifiers as allowed by @plane_caps.
> + * The caller must free the returned buffer.
> + */
> +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> + enum intel_plane_caps plane_caps)
> +{
> + u64 *list, *p;
> + int count = 1; /* +1 for invalid modifier terminator */
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> + count++;
> + }
> +
> + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
> + if (drm_WARN_ON(&i915->drm, !list))
> + return NULL;
> +
> + p = list;
> + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> + *p++ = intel_modifiers[i].id;
> + }
> + *p++ = DRM_FORMAT_MOD_INVALID;
> +
> + return list;
> +}
> +
> +/**
> + * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
> + * @plane: Plane to check the modifier support for
> + * @modifier: The modifier to check the support for
> + *
> + * Returns:
> + * %true if the @modifier is supported on @plane.
> + */
> +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
> +{
> + int i;
> +
> + for (i = 0; i < plane->base.modifier_count; i++)
> + if (plane->base.modifiers[i] == modifier)
> + return true;
> +
> + return false;
> +}
> +
> bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> {
> if (!is_ccs_modifier(fb->modifier))
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> index 1cbdd84502bdd..5bff88ccb9372 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -6,8 +6,12 @@
> #ifndef __INTEL_FB_H__
> #define __INTEL_FB_H__
>
> +#include <linux/bits.h>
> #include <linux/types.h>
>
> +enum pipe;
> +enum plane_id;
> +
> struct drm_device;
> struct drm_file;
> struct drm_framebuffer;
> @@ -16,13 +20,25 @@ struct drm_i915_private;
> struct drm_mode_fb_cmd2;
> struct intel_fb_view;
> struct intel_framebuffer;
> +struct intel_plane;
> struct intel_plane_state;
>
> +enum intel_plane_caps {
> + PLANE_HAS_NO_CAPS = 0,
> + PLANE_HAS_TILING = BIT(0),
> + PLANE_HAS_CCS_RC = BIT(1),
> + PLANE_HAS_CCS_MC = BIT(2),
> +};
> +
> bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
> bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
> bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
> bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
>
> +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> + enum intel_plane_caps plane_caps);
> +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
> +
> bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
>
> int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 08116f41da26a..2f4f47ab9da03 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -45,6 +45,7 @@
> #include "intel_atomic_plane.h"
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_fb.h"
> #include "intel_frontbuffer.h"
> #include "intel_sprite.h"
> #include "i9xx_plane.h"
> @@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = {
> DRM_FORMAT_VYUY,
> };
>
> -static const u64 i9xx_plane_format_modifiers[] = {
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> static const u32 snb_plane_formats[] = {
> DRM_FORMAT_XRGB8888,
> DRM_FORMAT_XBGR8888,
> @@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = {
> static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> @@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
> static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> @@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_C8:
> @@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> formats = vlv_plane_formats;
> num_formats = ARRAY_SIZE(vlv_plane_formats);
> }
> - modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (DISPLAY_VER(dev_priv) >= 7) {
> @@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
>
> formats = snb_plane_formats;
> num_formats = ARRAY_SIZE(snb_plane_formats);
> - modifiers = i9xx_plane_format_modifiers;
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> @@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> plane->max_stride = g4x_sprite_max_stride;
> plane->min_cdclk = g4x_sprite_min_cdclk;
>
> - modifiers = i9xx_plane_format_modifiers;
> if (IS_SANDYBRIDGE(dev_priv)) {
> formats = snb_plane_formats;
> num_formats = ARRAY_SIZE(snb_plane_formats);
> @@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> plane->id = PLANE_SPRITE0 + sprite;
> plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
>
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
> +
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> formats, num_formats, modifiers,
> DRM_PLANE_TYPE_OVERLAY,
> "sprite %c", sprite_name(pipe, sprite));
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index 37eabeff8197f..c2e94118566b6 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -4,6 +4,7 @@
> */
> #include "intel_de.h"
> #include "intel_display_types.h"
> +#include "intel_fb.h"
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index a0e53a3b267aa..908eb87d9cf8f 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = {
> DRM_FORMAT_XVYU16161616,
> };
>
> -static const u64 skl_plane_format_modifiers_noccs[] = {
> - I915_FORMAT_MOD_Yf_TILED,
> - I915_FORMAT_MOD_Y_TILED,
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> -static const u64 skl_plane_format_modifiers_ccs[] = {
> - I915_FORMAT_MOD_Yf_TILED_CCS,
> - I915_FORMAT_MOD_Y_TILED_CCS,
> - I915_FORMAT_MOD_Yf_TILED,
> - I915_FORMAT_MOD_Y_TILED,
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> -static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> - I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> - I915_FORMAT_MOD_Y_TILED,
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> -static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> - I915_FORMAT_MOD_Y_TILED,
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> -static const u64 adlp_step_a_plane_format_modifiers[] = {
> - I915_FORMAT_MOD_Y_TILED,
> - I915_FORMAT_MOD_X_TILED,
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> {
> switch (format) {
> @@ -1870,42 +1826,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
> }
> }
>
> -static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> - enum pipe pipe, enum plane_id plane_id)
> -{
> - if (plane_id == PLANE_CURSOR)
> - return false;
> -
> - if (DISPLAY_VER(dev_priv) >= 11)
> - return true;
> -
> - if (IS_GEMINILAKE(dev_priv))
> - return pipe != PIPE_C;
> -
> - return pipe != PIPE_C &&
> - (plane_id == PLANE_PRIMARY ||
> - plane_id == PLANE_SPRITE0);
> -}
> -
> static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> struct intel_plane *plane = to_intel_plane(_plane);
>
> - switch (modifier) {
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - case I915_FORMAT_MOD_Y_TILED:
> - case I915_FORMAT_MOD_Yf_TILED:
> - break;
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (!plane->has_ccs)
> - return false;
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(plane, modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> @@ -1953,45 +1880,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> }
> }
>
> -static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> - enum plane_id plane_id)
> -{
> - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
> - return false;
> -
> - /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - return false;
> -
> - return plane_id < PLANE_SPRITE4;
> -}
> -
> static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - struct drm_i915_private *dev_priv = to_i915(_plane->dev);
> struct intel_plane *plane = to_intel_plane(_plane);
>
> - switch (modifier) {
> - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> - if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
> - return false;
> - fallthrough;
> - case DRM_FORMAT_MOD_LINEAR:
> - case I915_FORMAT_MOD_X_TILED:
> - case I915_FORMAT_MOD_Y_TILED:
> - break;
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> - /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - return false;
> - break;
> - default:
> + if (!intel_fb_plane_supports_modifier(plane, modifier))
> return false;
> - }
>
> switch (format) {
> case DRM_FORMAT_XRGB8888:
> @@ -2039,18 +1934,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> }
> }
>
> -static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> - enum plane_id plane_id)
> -{
> - /* Wa_22011186057 */
> - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> - return adlp_step_a_plane_format_modifiers;
> - else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> - return gen12_plane_format_modifiers_mc_ccs;
> - else
> - return gen12_plane_format_modifiers_rc_ccs;
> -}
> -
> static const struct drm_plane_funcs skl_plane_funcs = {
> .update_plane = drm_atomic_helper_update_plane,
> .disable_plane = drm_atomic_helper_disable_plane,
> @@ -2091,6 +1974,42 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
> spin_unlock_irq(&i915->irq_lock);
> }
>
> +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> + enum pipe pipe, enum plane_id plane_id)
> +{
> + if (plane_id == PLANE_CURSOR)
> + return false;
> +
No cursors here anyway.
> + /* Wa_22011186057 */
> + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + return false;
> +
> + if (DISPLAY_VER(i915) >= 11)
> + return true;
> +
> + if (IS_GEMINILAKE(i915))
> + return pipe != PIPE_C;
> +
> + return pipe != PIPE_C &&
> + (plane_id == PLANE_PRIMARY ||
> + plane_id == PLANE_SPRITE0);
> +}
A bit tempted to say we should chop this up into more
platform specific variants. But that can be left for later I guess.
> +
> +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> + enum plane_id plane_id)
> +{
> + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> + IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> + return false;
> +
> + /* Wa_22011186057 */
> + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> + return false;
> +
> + return plane_id < PLANE_SPRITE4;
> +}
> +
> struct intel_plane *
> skl_universal_plane_create(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id)
> @@ -2098,6 +2017,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> const struct drm_plane_funcs *plane_funcs;
> struct intel_plane *plane;
> enum drm_plane_type plane_type;
> + enum intel_plane_caps plane_caps;
> unsigned int supported_rotations;
> unsigned int supported_csc;
> const u64 *modifiers;
> @@ -2159,29 +2079,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> formats = skl_get_plane_formats(dev_priv, pipe,
> plane_id, &num_formats);
>
> - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> - if (DISPLAY_VER(dev_priv) >= 12) {
> - modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
> + if (DISPLAY_VER(dev_priv) >= 12)
> plane_funcs = &gen12_plane_funcs;
> - } else {
> - if (plane->has_ccs)
> - modifiers = skl_plane_format_modifiers_ccs;
> - else
> - modifiers = skl_plane_format_modifiers_noccs;
> + else
> plane_funcs = &skl_plane_funcs;
> - }
>
> if (plane_id == PLANE_PRIMARY)
> plane_type = DRM_PLANE_TYPE_PRIMARY;
> else
> plane_type = DRM_PLANE_TYPE_OVERLAY;
>
> + plane_caps = PLANE_HAS_TILING;
> + if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id))
> + plane_caps |= PLANE_HAS_CCS_RC;
> +
> + if (gen12_plane_has_mc_ccs(dev_priv, plane_id))
> + plane_caps |= PLANE_HAS_CCS_MC;
> +
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps);
> +
> ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> 0, plane_funcs,
> formats, num_formats, modifiers,
> plane_type,
> "plane %d%c", plane_id + 1,
> pipe_name(pipe));
> +
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12256218634f4..a92228c922a54 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> +#define DISPLAY_VER_BIT(d) BIT_ULL(d)
> +#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
> +#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
>
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>
> --
> 2.27.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2021-10-13 20:17 ` Ville Syrjälä
2021-10-13 21:06 ` Imre Deak
0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:17 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 03:19:09AM +0300, Imre Deak wrote:
> Move the function retrieving the format override information for a given
> format/modifier to intel_fb.c. We can store a pointer to the format list
> in each modifier's descriptor instead of the corresponding switch/case
> logic, avoiding the listing of the modifiers twice.
>
> v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
> userspace.
Do we have any tests for that btw?
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 132 +--------------
> drivers/gpu/drm/i915/display/intel_fb.c | 163 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_fb.h | 3 +
> 3 files changed, 167 insertions(+), 131 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f0badb11bbba..90802d16fbf91 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
> *y += state->view.color_plane[color_plane].y;
> }
>
> -/*
> - * From the Sky Lake PRM:
> - * "The Color Control Surface (CCS) contains the compression status of
> - * the cache-line pairs. The compression state of the cache-line pair
> - * is specified by 2 bits in the CCS. Each CCS cache-line represents
> - * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> - * cache-line-pairs. CCS is always Y tiled."
> - *
> - * Since cache line pairs refers to horizontally adjacent cache lines,
> - * each cache line in the CCS corresponds to an area of 32x16 cache
> - * lines on the main surface. Since each pixel is 4 bytes, this gives
> - * us a ratio of one byte in the CCS for each 8x16 pixels in the
> - * main surface.
> - */
> -static const struct drm_format_info skl_ccs_formats[] = {
> - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> -};
> -
> -/*
> - * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> - * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> - * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> - * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
> - * the main surface.
> - */
> -static const struct drm_format_info gen12_ccs_formats[] = {
> - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 1, .vsub = 1, },
> - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 1, .vsub = 1, },
> - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 1, .vsub = 1, .has_alpha = true },
> - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 1, .vsub = 1, .has_alpha = true },
> - { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_VYUY, .num_planes = 2,
> - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 2, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
> - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> - .hsub = 1, .vsub = 1, .is_yuv = true },
> - { .format = DRM_FORMAT_NV12, .num_planes = 4,
> - .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
> - .hsub = 2, .vsub = 2, .is_yuv = true },
> - { .format = DRM_FORMAT_P010, .num_planes = 4,
> - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> - .hsub = 2, .vsub = 2, .is_yuv = true },
> - { .format = DRM_FORMAT_P012, .num_planes = 4,
> - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> - .hsub = 2, .vsub = 2, .is_yuv = true },
> - { .format = DRM_FORMAT_P016, .num_planes = 4,
> - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> - .hsub = 2, .vsub = 2, .is_yuv = true },
> -};
> -
> -/*
> - * Same as gen12_ccs_formats[] above, but with additional surface used
> - * to pass Clear Color information in plane 2 with 64 bits of data.
> - */
> -static const struct drm_format_info gen12_ccs_cc_formats[] = {
> - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> - .hsub = 1, .vsub = 1, },
> - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> - .hsub = 1, .vsub = 1, },
> - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> - .hsub = 1, .vsub = 1, .has_alpha = true },
> - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> - .hsub = 1, .vsub = 1, .has_alpha = true },
> -};
> -
> -static const struct drm_format_info *
> -lookup_format_info(const struct drm_format_info formats[],
> - int num_formats, u32 format)
> -{
> - int i;
> -
> - for (i = 0; i < num_formats; i++) {
> - if (formats[i].format == format)
> - return &formats[i];
> - }
> -
> - return NULL;
> -}
> -
> -static const struct drm_format_info *
> -intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> -{
> - switch (cmd->modifier[0]) {
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Yf_TILED_CCS:
> - return lookup_format_info(skl_ccs_formats,
> - ARRAY_SIZE(skl_ccs_formats),
> - cmd->pixel_format);
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> - return lookup_format_info(gen12_ccs_formats,
> - ARRAY_SIZE(gen12_ccs_formats),
> - cmd->pixel_format);
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> - return lookup_format_info(gen12_ccs_cc_formats,
> - ARRAY_SIZE(gen12_ccs_cc_formats),
> - cmd->pixel_format);
> - default:
> - return NULL;
> - }
> -}
> -
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier)
> {
> @@ -11270,7 +11140,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
>
> static const struct drm_mode_config_funcs intel_mode_funcs = {
> .fb_create = intel_user_framebuffer_create,
> - .get_format_info = intel_get_format_info,
> + .get_format_info = intel_fb_get_format_info,
> .output_poll_changed = intel_fbdev_output_poll_changed,
> .mode_valid = intel_mode_valid,
> .atomic_check = intel_atomic_check,
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 11a4c3e81cead..920de857ffa28 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -13,9 +13,108 @@
>
> #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
>
> +/*
> + * From the Sky Lake PRM:
> + * "The Color Control Surface (CCS) contains the compression status of
> + * the cache-line pairs. The compression state of the cache-line pair
> + * is specified by 2 bits in the CCS. Each CCS cache-line represents
> + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> + * cache-line-pairs. CCS is always Y tiled."
> + *
> + * Since cache line pairs refers to horizontally adjacent cache lines,
> + * each cache line in the CCS corresponds to an area of 32x16 cache
> + * lines on the main surface. Since each pixel is 4 bytes, this gives
> + * us a ratio of one byte in the CCS for each 8x16 pixels in the
> + * main surface.
> + */
> +static const struct drm_format_info skl_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> +};
> +
> +/*
> + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
> + * the main surface.
> + */
> +static const struct drm_format_info gen12_ccs_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_VYUY, .num_planes = 2,
> + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 2, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
> + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> + .hsub = 1, .vsub = 1, .is_yuv = true },
> + { .format = DRM_FORMAT_NV12, .num_planes = 4,
> + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P010, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P012, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> + { .format = DRM_FORMAT_P016, .num_planes = 4,
> + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> + .hsub = 2, .vsub = 2, .is_yuv = true },
> +};
> +
> +/*
> + * Same as gen12_ccs_formats[] above, but with additional surface used
> + * to pass Clear Color information in plane 2 with 64 bits of data.
> + */
> +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, },
> + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> + .hsub = 1, .vsub = 1, .has_alpha = true },
> +};
> +
> +#define FORMAT_OVERRIDE(format_list) \
> + .formats = format_list, \
> + .format_count = ARRAY_SIZE(format_list)
> +
> const struct intel_modifier_desc {
> u64 id;
> u64 display_versions;
> + const struct drm_format_info *formats;
> + int format_count;
> u8 is_linear:1;
>
> struct {
> @@ -49,33 +148,97 @@ const struct intel_modifier_desc {
> .display_versions = DISPLAY_VER_MASK(9, 11),
>
> .ccs.type = INTEL_CCS_RC,
> +
> + FORMAT_OVERRIDE(skl_ccs_formats),
> },
> {
> .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> .display_versions = DISPLAY_VER_MASK(9, 11),
>
> .ccs.type = INTEL_CCS_RC,
> +
> + FORMAT_OVERRIDE(skl_ccs_formats),
> },
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> .display_versions = DISPLAY_VER_MASK(12, 13),
>
> .ccs.type = INTEL_CCS_RC,
> +
> + FORMAT_OVERRIDE(gen12_ccs_formats),
> },
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> .display_versions = DISPLAY_VER_MASK(12, 13),
>
> .ccs.type = INTEL_CCS_RC_CC,
> +
> + FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> },
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> .display_versions = DISPLAY_VER_MASK(12, 13),
>
> .ccs.type = INTEL_CCS_MC,
> +
> + FORMAT_OVERRIDE(gen12_ccs_formats),
> },
> };
>
> +static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
> + if (intel_modifiers[i].id == modifier)
> + return &intel_modifiers[i];
> +
> + return NULL;
> +}
> +
> +static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
> +{
> + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
> +
> + if (WARN_ON(!md))
> + return &intel_modifiers[0];
> +
> + return md;
> +}
> +
> +static const struct drm_format_info *
> +lookup_format_info(const struct drm_format_info formats[],
> + int num_formats, u32 format)
> +{
> + int i;
> +
> + for (i = 0; i < num_formats; i++) {
> + if (formats[i].format == format)
> + return &formats[i];
> + }
> +
> + return NULL;
> +}
> +
> +/**
> + * intel_fb_get_format_info: Get a modifier specific format information
> + * @cmd: FB add command structure
> + *
> + * Returns:
> + * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
> + * or %NULL if the modifier doesn't override the format.
> + */
> +const struct drm_format_info *
> +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> +{
> + const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
> +
> + if (!md || !md->formats)
> + return NULL;
> +
> + return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
> +}
> +
> static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> {
> return md->ccs.type & ccs_type;
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> index 5bff88ccb9372..a87c58a3219cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -39,6 +39,9 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> enum intel_plane_caps plane_caps);
> bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
>
> +const struct drm_format_info *
> +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
> +
> bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
>
> int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
> --
> 2.27.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor
2021-10-07 20:35 ` [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2021-10-13 20:18 ` Ville Syrjälä
2021-10-13 21:08 ` Imre Deak
1 sibling, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:18 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 07, 2021 at 11:35:09PM +0300, Imre Deak wrote:
> Add a tiling atttribute to the modifier descriptor, which let's us
> get the tiling without listing the modifiers twice.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fb.c | 20 ++++++++------------
> 1 file changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index 2543232580885..ef3cd375c9942 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -115,6 +115,7 @@ const struct intel_modifier_desc {
> u64 display_versions;
> const struct drm_format_info *formats;
> int format_count;
> + u8 tiling;
>
> struct {
> #define INTEL_CCS_RC BIT(0)
> @@ -132,10 +133,12 @@ const struct intel_modifier_desc {
> {
> .id = I915_FORMAT_MOD_X_TILED,
> .display_versions = DISPLAY_VER_MASK_ALL,
> + .tiling = I915_TILING_X,
> },
> {
> .id = I915_FORMAT_MOD_Y_TILED,
> .display_versions = DISPLAY_VER_MASK(9, 13),
> + .tiling = I915_TILING_Y,
> },
> {
> .id = I915_FORMAT_MOD_Yf_TILED,
> @@ -144,6 +147,7 @@ const struct intel_modifier_desc {
> {
> .id = I915_FORMAT_MOD_Y_TILED_CCS,
> .display_versions = DISPLAY_VER_MASK(9, 11),
> + .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC,
>
> @@ -160,6 +164,7 @@ const struct intel_modifier_desc {
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> .display_versions = DISPLAY_VER_MASK(12, 13),
> + .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC,
>
> @@ -168,6 +173,7 @@ const struct intel_modifier_desc {
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> .display_versions = DISPLAY_VER_MASK(12, 13),
> + .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC_CC,
>
> @@ -176,6 +182,7 @@ const struct intel_modifier_desc {
> {
> .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> .display_versions = DISPLAY_VER_MASK(12, 13),
> + .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_MC,
>
> @@ -556,18 +563,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
>
> static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> {
> - switch (fb_modifier) {
> - case I915_FORMAT_MOD_X_TILED:
> - return I915_TILING_X;
> - case I915_FORMAT_MOD_Y_TILED:
> - case I915_FORMAT_MOD_Y_TILED_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> - return I915_TILING_Y;
> - default:
> - return I915_TILING_NONE;
Had to double check that I915_TILING_NONE is really 0. It is.
> - }
> + return lookup_modifier(fb_modifier)->tiling;
> }
>
> unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
> --
> 2.27.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-07 20:35 ` [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for " Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2021-10-13 20:27 ` Ville Syrjälä
2021-10-13 20:45 ` Ville Syrjälä
1 sibling, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:27 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> Future platforms change the location of CCS control planes in CCS
> framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
Don't we use the term 'ccs_plane' everywhere else?
> planes independently of the platform. This function can be used
> everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> since all the callers are only interested in control planes (and not CCS
> color-clear planes).
>
> Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
> used everywhere instead of is_gen12_ccs_plane(), based on the above
> explanation.
>
> This change also unexports the is_gen12_ccs_modifier(),
> is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
> used in intel_fb.c
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 7 --
> drivers/gpu/drm/i915/display/intel_fb.c | 73 ++++++++++++++-----
> drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
> .../drm/i915/display/skl_universal_plane.c | 3 +-
> 4 files changed, 56 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index bb53b01f07aee..b4b6a31caf4e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
>
> -static inline bool is_gen12_ccs_modifier(u64 modifier)
> -{
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> -}
> -
> #endif /* __INTEL_DISPLAY_TYPES_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e8fe198b1b6a1..392f89e659eb6 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -125,6 +125,8 @@ const struct intel_modifier_desc {
> #define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> u8 type:3;
> u8 cc_planes:3;
> + u8 packed_ctrl_planes:4;
> + u8 planar_ctrl_planes:4;
> } ccs;
> } intel_modifiers[] = {
> {
> @@ -151,6 +153,7 @@ const struct intel_modifier_desc {
> .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC,
> + .ccs.packed_ctrl_planes = BIT(1),
>
> FORMAT_OVERRIDE(skl_ccs_formats),
> },
> @@ -159,6 +162,7 @@ const struct intel_modifier_desc {
> .display_versions = DISPLAY_VER_MASK(9, 11),
>
> .ccs.type = INTEL_CCS_RC,
> + .ccs.packed_ctrl_planes = BIT(1),
>
> FORMAT_OVERRIDE(skl_ccs_formats),
> },
> @@ -168,6 +172,7 @@ const struct intel_modifier_desc {
> .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC,
> + .ccs.packed_ctrl_planes = BIT(1),
>
> FORMAT_OVERRIDE(gen12_ccs_formats),
> },
> @@ -177,6 +182,7 @@ const struct intel_modifier_desc {
> .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_RC_CC,
> + .ccs.packed_ctrl_planes = BIT(1),
> .ccs.cc_planes = BIT(2),
>
> FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> @@ -187,6 +193,8 @@ const struct intel_modifier_desc {
> .tiling = I915_TILING_Y,
>
> .ccs.type = INTEL_CCS_MC,
> + .ccs.packed_ctrl_planes = BIT(1),
> + .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
>
> FORMAT_OVERRIDE(gen12_ccs_formats),
> },
> @@ -385,17 +393,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
> return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
> }
>
> -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> +static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
> + const struct drm_format_info *format)
> {
> - if (!is_ccs_modifier(fb->modifier))
> - return false;
> + if (format_is_yuv_semiplanar(md, format))
> + return md->ccs.planar_ctrl_planes;
> + else
> + return md->ccs.packed_ctrl_planes;
> +}
> +
> +/**
> + * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS control plane
> + * @fb: Framebuffer
> + * @plane: color plane index to check
> + *
> + * Returns:
> + * Returns %true if @fb's color plane at index @plane is a CCS control plane.
> + */
> +bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> +{
> + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
>
> - return plane >= fb->format->num_planes / 2;
> + return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
> }
>
> -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> +/**
> + * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer color plane is a GEN12 CCS control plane
> + * @fb: Framebuffer
> + * @plane: color plane index to check
> + *
> + * Returns:
> + * Returns %true if @fb's color plane at index @plane is a GEN12 CCS control plane.
> + */
> +static bool intel_fb_is_gen12_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> {
> - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> +
> + return md->display_versions & (DISPLAY_VER_MASK(12, 13)) &&
> + ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
> }
>
> /**
> @@ -418,7 +453,7 @@ int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
> return ilog2((int)md->ccs.cc_planes);
> }
>
> -bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
> +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane)
> {
> return intel_fb_rc_ccs_cc_plane(fb) == plane;
> }
> @@ -432,7 +467,7 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p
> bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
> {
> return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
> - is_gen12_ccs_plane(fb, color_plane) ||
> + intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane) ||
> is_gen12_ccs_cc_plane(fb, color_plane);
> }
>
> @@ -520,13 +555,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> - if (is_ccs_plane(fb, color_plane))
> + if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
> return 128;
> fallthrough;
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> - if (is_ccs_plane(fb, color_plane) ||
> + if (intel_fb_is_ccs_ctrl_plane(fb, color_plane) ||
> is_gen12_ccs_cc_plane(fb, color_plane))
> return 64;
> fallthrough;
> @@ -536,7 +571,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> else
> return 512;
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (is_ccs_plane(fb, color_plane))
> + if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
> return 128;
> fallthrough;
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -592,7 +627,7 @@ static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_pl
> {
> intel_tile_dims(fb, color_plane, tile_width, tile_height);
>
> - if (is_gen12_ccs_plane(fb, color_plane))
> + if (intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane))
> *tile_height = 1;
> }
>
> @@ -653,7 +688,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> return 512 * 4096;
>
> /* AUX_DIST needs only 4K alignment */
> - if (is_ccs_plane(fb, color_plane))
> + if (intel_fb_is_ccs_ctrl_plane(fb, color_plane))
> return 4096;
>
> if (is_semiplanar_uv_plane(fb, color_plane)) {
> @@ -712,7 +747,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> * TODO: Deduct the subsampling from the char block for all CCS
> * formats and planes.
> */
> - if (!is_gen12_ccs_plane(fb, color_plane)) {
> + if (!intel_fb_is_gen12_ccs_ctrl_plane(fb, color_plane)) {
> *hsub = fb->format->hsub;
> *vsub = fb->format->vsub;
>
> @@ -740,7 +775,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
> static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
> {
> struct drm_i915_private *i915 = to_i915(fb->base.dev);
> - int main_plane = is_ccs_plane(&fb->base, color_plane) ?
> + int main_plane = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ?
> skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
> unsigned int main_width = fb->base.width;
> unsigned int main_height = fb->base.height;
> @@ -753,7 +788,7 @@ static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_pl
> * stride in the allocated FB object may not be power-of-two
> * sized, in which case it is auto-padded to the POT size.
> */
> - if (IS_ALDERLAKE_P(i915) && is_ccs_plane(&fb->base, color_plane))
> + if (IS_ALDERLAKE_P(i915) && intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane))
> main_width = gen12_aligned_scanout_stride(fb, 0) /
> fb->base.format->cpp[0];
>
> @@ -992,7 +1027,7 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane
> int ccs_x, ccs_y;
> int main_x, main_y;
>
> - if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane))
> + if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
> return 0;
>
> /*
> @@ -1196,7 +1231,7 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
> unsigned int pitch_tiles)
> {
> if (intel_fb_needs_pot_stride_remap(fb)) {
> - unsigned int min_stride = is_ccs_plane(&fb->base, color_plane) ? 2 : 8;
> + unsigned int min_stride = intel_fb_is_ccs_ctrl_plane(&fb->base, color_plane) ? 2 : 8;
> /*
> * ADL_P, the only platform needing a POT stride has a minimum
> * of 8 main surface and 2 CCS AUX stride tiles.
> @@ -1812,7 +1847,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
> goto err;
> }
>
> - if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) {
> + if (intel_fb_is_gen12_ccs_ctrl_plane(fb, i)) {
> int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
>
> if (fb->pitches[i] != ccs_aux_stride) {
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> index 5affcc834e045..baa5b538b4be7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.h
> +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> @@ -22,10 +22,7 @@ struct intel_framebuffer;
> struct intel_plane;
> struct intel_plane_state;
>
> -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
> -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
> -bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
> -
> +bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane);
> int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);
>
> u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 4f0dbb00ea28c..95900b631aa7c 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1607,8 +1607,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> int hsub, vsub;
> int x, y;
>
> - if (!is_ccs_plane(fb, ccs_plane) ||
> - is_gen12_ccs_cc_plane(fb, ccs_plane))
> + if (!intel_fb_is_ccs_ctrl_plane(fb, ccs_plane))
> continue;
>
> intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
> --
> 2.27.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:14 ` Ville Syrjälä
@ 2021-10-13 20:40 ` Ville Syrjälä
2021-10-14 10:07 ` Imre Deak
1 sibling, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:40 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
> bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
> bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
Side note:
We have quite a few of these 'int plane' things still around. I'd
like to see them all renamed to 'color_plane' so that we don't get
confused between diffrent kinds of planes.
The rules that I've been going for everywhere:
- int color_plane == plane of a planar/compressed framebuffer
- struct intel_plane *plane == representation of the piece of
hardware that does the scanout
- enum plane plane_id == standalone version of plane->id
- enum i9xx_plane_id i9xx_plane == standalone version of plane->i9xx_plane
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 20:27 ` [Intel-gfx] [PATCH " Ville Syrjälä
@ 2021-10-13 20:45 ` Ville Syrjälä
2021-10-13 21:32 ` Imre Deak
0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 20:45 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > Future platforms change the location of CCS control planes in CCS
> > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
>
> Don't we use the term 'ccs_plane' everywhere else?
>
> > planes independently of the platform. This function can be used
> > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > since all the callers are only interested in control planes (and not CCS
> > color-clear planes).
Hmm. I guess you're changing the terminology across the board?
If it's used consistently then no objections from me.
> >
> > Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
> > used everywhere instead of is_gen12_ccs_plane(), based on the above
> > explanation.
> >
> > This change also unexports the is_gen12_ccs_modifier(),
> > is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
> > used in intel_fb.c
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 7 --
> > drivers/gpu/drm/i915/display/intel_fb.c | 73 ++++++++++++++-----
> > drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
> > .../drm/i915/display/skl_universal_plane.c | 3 +-
> > 4 files changed, 56 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index bb53b01f07aee..b4b6a31caf4e3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
> > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > }
> >
> > -static inline bool is_gen12_ccs_modifier(u64 modifier)
> > -{
> > - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > -}
> > -
> > #endif /* __INTEL_DISPLAY_TYPES_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index e8fe198b1b6a1..392f89e659eb6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -125,6 +125,8 @@ const struct intel_modifier_desc {
> > #define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > u8 type:3;
> > u8 cc_planes:3;
> > + u8 packed_ctrl_planes:4;
> > + u8 planar_ctrl_planes:4;
> > } ccs;
> > } intel_modifiers[] = {
> > {
> > @@ -151,6 +153,7 @@ const struct intel_modifier_desc {
> > .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> > + .ccs.packed_ctrl_planes = BIT(1),
> >
> > FORMAT_OVERRIDE(skl_ccs_formats),
> > },
> > @@ -159,6 +162,7 @@ const struct intel_modifier_desc {
> > .display_versions = DISPLAY_VER_MASK(9, 11),
> >
> > .ccs.type = INTEL_CCS_RC,
> > + .ccs.packed_ctrl_planes = BIT(1),
> >
> > FORMAT_OVERRIDE(skl_ccs_formats),
> > },
> > @@ -168,6 +172,7 @@ const struct intel_modifier_desc {
> > .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> > + .ccs.packed_ctrl_planes = BIT(1),
> >
> > FORMAT_OVERRIDE(gen12_ccs_formats),
> > },
> > @@ -177,6 +182,7 @@ const struct intel_modifier_desc {
> > .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC_CC,
> > + .ccs.packed_ctrl_planes = BIT(1),
> > .ccs.cc_planes = BIT(2),
> >
> > FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> > @@ -187,6 +193,8 @@ const struct intel_modifier_desc {
> > .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_MC,
> > + .ccs.packed_ctrl_planes = BIT(1),
> > + .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
> >
> > FORMAT_OVERRIDE(gen12_ccs_formats),
> > },
> > @@ -385,17 +393,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
> > return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
> > }
> >
> > -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > +static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
> > + const struct drm_format_info *format)
> > {
> > - if (!is_ccs_modifier(fb->modifier))
> > - return false;
> > + if (format_is_yuv_semiplanar(md, format))
> > + return md->ccs.planar_ctrl_planes;
> > + else
> > + return md->ccs.packed_ctrl_planes;
> > +}
> > +
> > +/**
> > + * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS control plane
> > + * @fb: Framebuffer
> > + * @plane: color plane index to check
> > + *
> > + * Returns:
> > + * Returns %true if @fb's color plane at index @plane is a CCS control plane.
> > + */
> > +bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> > +{
> > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> >
> > - return plane >= fb->format->num_planes / 2;
> > + return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
> > }
> >
> > -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > +/**
> > + * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer color plane is a GEN12 CCS control plane
> > + * @fb: Framebuffer
> > + * @plane: color plane index to check
> > + *
> > + * Returns:
> > + * Returns %true if @fb's color plane at index @plane is a GEN12 CCS control plane.
> > + */
> > +static bool intel_fb_is_gen12_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> > {
> > - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> > +
> > + return md->display_versions & (DISPLAY_VER_MASK(12, 13)) &&
Aha! No RPN here ;)
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-13 20:14 ` Ville Syrjälä
@ 2021-10-13 21:01 ` Imre Deak
2021-10-13 21:34 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-13 21:01 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:14:42PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
> >
> > v2:
> > - Keep the plane caps calculation in the plane code and pass an enum
> > with these caps to intel_fb_get_modifiers(). (Ville)
> > - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as
> > well.
> >
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +--
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h | 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 143 ++++++++++++++
> > drivers/gpu/drm/i915/display/intel_fb.h | 16 ++
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 181 +++++-------------
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 9 files changed, 245 insertions(+), 184 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index b1439ba78f67b..a939accff7ee2 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = {
> > DRM_FORMAT_XBGR16161616F,
> > };
> >
> > -static const u64 i9xx_format_modifiers[] = {
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_C8:
> > @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane,
> > static bool i965_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_C8:
> > @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> > struct intel_plane *plane;
> > const struct drm_plane_funcs *plane_funcs;
> > unsigned int supported_rotations;
> > + const u64 *modifiers;
> > const u32 *formats;
> > int num_formats;
> > int ret, zpos;
> > @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> > plane->disable_flip_done = ilk_primary_disable_flip_done;
> > }
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
> > +
> > if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> > 0, plane_funcs,
> > formats, num_formats,
> > - i9xx_format_modifiers,
> > + modifiers,
> > DRM_PLANE_TYPE_PRIMARY,
> > "primary %c", pipe_name(pipe));
> > else
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> > 0, plane_funcs,
> > formats, num_formats,
> > - i9xx_format_modifiers,
> > + modifiers,
> > DRM_PLANE_TYPE_PRIMARY,
> > "plane %c",
> > plane_name(plane->i9xx_plane));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index f6dcb5aa63f64..1f764c6d59583 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB8888,
> > };
> >
> > -static const u64 cursor_format_modifiers[] = {
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > - format == DRM_FORMAT_ARGB8888;
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > + return false;
> > +
> > + return format == DRM_FORMAT_ARGB8888;
> > }
> >
> > static int
> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > {
> > struct intel_plane *cursor;
> > int ret, zpos;
> > + u64 *modifiers;
> >
> > cursor = intel_plane_alloc();
> > if (IS_ERR(cursor))
> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > cursor->cursor.size = ~0;
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > 0, &intel_cursor_plane_funcs,
> > intel_cursor_formats,
> > ARRAY_SIZE(intel_cursor_formats),
> > - cursor_format_modifiers,
> > + modifiers,
> > DRM_PLANE_TYPE_CURSOR,
> > "cursor %c", pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645a..bb53b01f07aee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > enum plane_id id;
> > enum pipe pipe;
> > bool has_fbc;
> > - bool has_ccs;
> > bool need_async_flip_disable_wa;
> > u32 frontbuffer_bit;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index fa1f375e696bf..11a4c3e81cead 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,6 +13,149 @@
> >
> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> >
> > +const struct intel_modifier_desc {
> > + u64 id;
>
> s/id/modifier/ ?
Ok.
> > + u64 display_versions;
> > + u8 is_linear:1;
> > +
> > + struct {
> > +#define INTEL_CCS_RC BIT(0)
> > +#define INTEL_CCS_RC_CC BIT(1)
> > +#define INTEL_CCS_MC BIT(2)
> > +
> > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > + u8 type:3;
> > + } ccs;
> > +} intel_modifiers[] = {
> > + {
> > + .id = DRM_FORMAT_MOD_LINEAR,
> > + .display_versions = DISPLAY_VER_MASK_ALL,
> > + .is_linear = true,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_X_TILED,
> > + .display_versions = DISPLAY_VER_MASK_ALL,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED,
> > + .display_versions = DISPLAY_VER_MASK(9, 13),
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Yf_TILED,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > + .display_versions = DISPLAY_VER_MASK(9, 11),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_RC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_RC_CC,
> > + },
> > + {
> > + .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > + .display_versions = DISPLAY_VER_MASK(12, 13),
> > +
> > + .ccs.type = INTEL_CCS_MC,
> > + },
> > +};
> > +
> > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > +{
> > + return md->ccs.type & ccs_type;
> > +}
> > +
> > +static bool plane_has_modifier(struct drm_i915_private *i915,
> > + enum intel_plane_caps plane_caps,
> > + const struct intel_modifier_desc *md)
> > +{
> > + if (!(DISPLAY_VER_BIT(DISPLAY_VER(i915)) & md->display_versions))
> > + return false;
>
> I guess I'd typically have the bitmask vs. the bit we're checking
> the other way around. Feels a bit RPN :P
Yes, will fix it.
> > +
> > + if (!(plane_caps & PLANE_HAS_TILING) && !md->is_linear)
> > + return false;
>
> This has the plane_caps part on the left of && ...
>
> > +
> > + if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) &&
> > + !(plane_caps & PLANE_HAS_CCS_RC))
> > + return false;
> > +
> > + if (is_ccs_type_modifier(md, INTEL_CCS_MC) &&
> > + !(plane_caps & PLANE_HAS_CCS_MC))
> > + return false;
>
> ...these have it on the right.
>
> My poor brain would like things to be consistent ;a
Yep, makes sense, will make the conditions more uniform.
>
> > +
> > + return true;
> > +}
> > +
> > +/**
> > + * intel_fb_plane_get_modifiers: Get the modifiers supported by the given pipe and plane
> > + * @i915: i915 device instance
> > + * @plane_caps: capabilities for the plane the modifiers are queried for
> > + *
> > + * Returns:
> > + * Returns the list of modifiers as allowed by @plane_caps.
> > + * The caller must free the returned buffer.
> > + */
> > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> > + enum intel_plane_caps plane_caps)
> > +{
> > + u64 *list, *p;
> > + int count = 1; /* +1 for invalid modifier terminator */
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> > + count++;
> > + }
> > +
> > + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
> > + if (drm_WARN_ON(&i915->drm, !list))
> > + return NULL;
> > +
> > + p = list;
> > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
> > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
> > + *p++ = intel_modifiers[i].id;
> > + }
> > + *p++ = DRM_FORMAT_MOD_INVALID;
> > +
> > + return list;
> > +}
> > +
> > +/**
> > + * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
> > + * @plane: Plane to check the modifier support for
> > + * @modifier: The modifier to check the support for
> > + *
> > + * Returns:
> > + * %true if the @modifier is supported on @plane.
> > + */
> > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < plane->base.modifier_count; i++)
> > + if (plane->base.modifiers[i] == modifier)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > {
> > if (!is_ccs_modifier(fb->modifier))
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> > index 1cbdd84502bdd..5bff88ccb9372 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> > @@ -6,8 +6,12 @@
> > #ifndef __INTEL_FB_H__
> > #define __INTEL_FB_H__
> >
> > +#include <linux/bits.h>
> > #include <linux/types.h>
> >
> > +enum pipe;
> > +enum plane_id;
> > +
> > struct drm_device;
> > struct drm_file;
> > struct drm_framebuffer;
> > @@ -16,13 +20,25 @@ struct drm_i915_private;
> > struct drm_mode_fb_cmd2;
> > struct intel_fb_view;
> > struct intel_framebuffer;
> > +struct intel_plane;
> > struct intel_plane_state;
> >
> > +enum intel_plane_caps {
> > + PLANE_HAS_NO_CAPS = 0,
> > + PLANE_HAS_TILING = BIT(0),
> > + PLANE_HAS_CCS_RC = BIT(1),
> > + PLANE_HAS_CCS_MC = BIT(2),
> > +};
> > +
> > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
> > bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
> > bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
> > bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane);
> >
> > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> > + enum intel_plane_caps plane_caps);
> > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
> > +
> > bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
> >
> > int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
> > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> > index 08116f41da26a..2f4f47ab9da03 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> > @@ -45,6 +45,7 @@
> > #include "intel_atomic_plane.h"
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > +#include "intel_fb.h"
> > #include "intel_frontbuffer.h"
> > #include "intel_sprite.h"
> > #include "i9xx_plane.h"
> > @@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = {
> > DRM_FORMAT_VYUY,
> > };
> >
> > -static const u64 i9xx_plane_format_modifiers[] = {
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static const u32 snb_plane_formats[] = {
> > DRM_FORMAT_XRGB8888,
> > DRM_FORMAT_XBGR8888,
> > @@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = {
> > static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_XRGB8888:
> > @@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane,
> > static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_XRGB8888:
> > @@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane,
> > static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_C8:
> > @@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> > formats = vlv_plane_formats;
> > num_formats = ARRAY_SIZE(vlv_plane_formats);
> > }
> > - modifiers = i9xx_plane_format_modifiers;
> >
> > plane_funcs = &vlv_sprite_funcs;
> > } else if (DISPLAY_VER(dev_priv) >= 7) {
> > @@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> >
> > formats = snb_plane_formats;
> > num_formats = ARRAY_SIZE(snb_plane_formats);
> > - modifiers = i9xx_plane_format_modifiers;
> >
> > plane_funcs = &snb_sprite_funcs;
> > } else {
> > @@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> > plane->max_stride = g4x_sprite_max_stride;
> > plane->min_cdclk = g4x_sprite_min_cdclk;
> >
> > - modifiers = i9xx_plane_format_modifiers;
> > if (IS_SANDYBRIDGE(dev_priv)) {
> > formats = snb_plane_formats;
> > num_formats = ARRAY_SIZE(snb_plane_formats);
> > @@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
> > plane->id = PLANE_SPRITE0 + sprite;
> > plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id);
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> > 0, plane_funcs,
> > formats, num_formats, modifiers,
> > DRM_PLANE_TYPE_OVERLAY,
> > "sprite %c", sprite_name(pipe, sprite));
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> > index 37eabeff8197f..c2e94118566b6 100644
> > --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> > @@ -4,6 +4,7 @@
> > */
> > #include "intel_de.h"
> > #include "intel_display_types.h"
> > +#include "intel_fb.h"
> > #include "skl_scaler.h"
> > #include "skl_universal_plane.h"
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index a0e53a3b267aa..908eb87d9cf8f 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = {
> > DRM_FORMAT_XVYU16161616,
> > };
> >
> > -static const u64 skl_plane_format_modifiers_noccs[] = {
> > - I915_FORMAT_MOD_Yf_TILED,
> > - I915_FORMAT_MOD_Y_TILED,
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > -static const u64 skl_plane_format_modifiers_ccs[] = {
> > - I915_FORMAT_MOD_Yf_TILED_CCS,
> > - I915_FORMAT_MOD_Y_TILED_CCS,
> > - I915_FORMAT_MOD_Yf_TILED,
> > - I915_FORMAT_MOD_Y_TILED,
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > -static const u64 gen12_plane_format_modifiers_mc_ccs[] = {
> > - I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > - I915_FORMAT_MOD_Y_TILED,
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > -static const u64 gen12_plane_format_modifiers_rc_ccs[] = {
> > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > - I915_FORMAT_MOD_Y_TILED,
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > -static const u64 adlp_step_a_plane_format_modifiers[] = {
> > - I915_FORMAT_MOD_Y_TILED,
> > - I915_FORMAT_MOD_X_TILED,
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> > {
> > switch (format) {
> > @@ -1870,42 +1826,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
> > }
> > }
> >
> > -static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
> > - enum pipe pipe, enum plane_id plane_id)
> > -{
> > - if (plane_id == PLANE_CURSOR)
> > - return false;
> > -
> > - if (DISPLAY_VER(dev_priv) >= 11)
> > - return true;
> > -
> > - if (IS_GEMINILAKE(dev_priv))
> > - return pipe != PIPE_C;
> > -
> > - return pipe != PIPE_C &&
> > - (plane_id == PLANE_PRIMARY ||
> > - plane_id == PLANE_SPRITE0);
> > -}
> > -
> > static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > struct intel_plane *plane = to_intel_plane(_plane);
> >
> > - switch (modifier) {
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - case I915_FORMAT_MOD_Y_TILED:
> > - case I915_FORMAT_MOD_Yf_TILED:
> > - break;
> > - case I915_FORMAT_MOD_Y_TILED_CCS:
> > - case I915_FORMAT_MOD_Yf_TILED_CCS:
> > - if (!plane->has_ccs)
> > - return false;
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(plane, modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_XRGB8888:
> > @@ -1953,45 +1880,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
> > }
> > }
> >
> > -static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
> > - enum plane_id plane_id)
> > -{
> > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0))
> > - return false;
> > -
> > - /* Wa_22011186057 */
> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - return false;
> > -
> > - return plane_id < PLANE_SPRITE4;
> > -}
> > -
> > static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(_plane->dev);
> > struct intel_plane *plane = to_intel_plane(_plane);
> >
> > - switch (modifier) {
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > - if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
> > - return false;
> > - fallthrough;
> > - case DRM_FORMAT_MOD_LINEAR:
> > - case I915_FORMAT_MOD_X_TILED:
> > - case I915_FORMAT_MOD_Y_TILED:
> > - break;
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > - /* Wa_22011186057 */
> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - return false;
> > - break;
> > - default:
> > + if (!intel_fb_plane_supports_modifier(plane, modifier))
> > return false;
> > - }
> >
> > switch (format) {
> > case DRM_FORMAT_XRGB8888:
> > @@ -2039,18 +1934,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
> > }
> > }
> >
> > -static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
> > - enum plane_id plane_id)
> > -{
> > - /* Wa_22011186057 */
> > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> > - return adlp_step_a_plane_format_modifiers;
> > - else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
> > - return gen12_plane_format_modifiers_mc_ccs;
> > - else
> > - return gen12_plane_format_modifiers_rc_ccs;
> > -}
> > -
> > static const struct drm_plane_funcs skl_plane_funcs = {
> > .update_plane = drm_atomic_helper_update_plane,
> > .disable_plane = drm_atomic_helper_disable_plane,
> > @@ -2091,6 +1974,42 @@ skl_plane_disable_flip_done(struct intel_plane *plane)
> > spin_unlock_irq(&i915->irq_lock);
> > }
> >
> > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > + enum pipe pipe, enum plane_id plane_id)
> > +{
> > + if (plane_id == PLANE_CURSOR)
> > + return false;
> > +
>
> No cursors here anyway.
Right, it's a copy/paste, but realize now that the cursor plane is
registered separately. Will drop this.
>
> > + /* Wa_22011186057 */
> > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > + return false;
> > +
> > + if (DISPLAY_VER(i915) >= 11)
> > + return true;
> > +
> > + if (IS_GEMINILAKE(i915))
> > + return pipe != PIPE_C;
> > +
> > + return pipe != PIPE_C &&
> > + (plane_id == PLANE_PRIMARY ||
> > + plane_id == PLANE_SPRITE0);
> > +}
>
> A bit tempted to say we should chop this up into more
> platform specific variants. But that can be left for later I guess.
You mean clarifying that last check is for SKL/BXT? Would a code comment
be ok?
> > +
> > +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> > + enum plane_id plane_id)
> > +{
> > + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> > + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
> > + IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0))
> > + return false;
> > +
> > + /* Wa_22011186057 */
> > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > + return false;
> > +
> > + return plane_id < PLANE_SPRITE4;
> > +}
> > +
> > struct intel_plane *
> > skl_universal_plane_create(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id)
> > @@ -2098,6 +2017,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> > const struct drm_plane_funcs *plane_funcs;
> > struct intel_plane *plane;
> > enum drm_plane_type plane_type;
> > + enum intel_plane_caps plane_caps;
> > unsigned int supported_rotations;
> > unsigned int supported_csc;
> > const u64 *modifiers;
> > @@ -2159,29 +2079,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> > formats = skl_get_plane_formats(dev_priv, pipe,
> > plane_id, &num_formats);
> >
> > - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
> > - if (DISPLAY_VER(dev_priv) >= 12) {
> > - modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
> > + if (DISPLAY_VER(dev_priv) >= 12)
> > plane_funcs = &gen12_plane_funcs;
> > - } else {
> > - if (plane->has_ccs)
> > - modifiers = skl_plane_format_modifiers_ccs;
> > - else
> > - modifiers = skl_plane_format_modifiers_noccs;
> > + else
> > plane_funcs = &skl_plane_funcs;
> > - }
> >
> > if (plane_id == PLANE_PRIMARY)
> > plane_type = DRM_PLANE_TYPE_PRIMARY;
> > else
> > plane_type = DRM_PLANE_TYPE_OVERLAY;
> >
> > + plane_caps = PLANE_HAS_TILING;
> > + if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id))
> > + plane_caps |= PLANE_HAS_CCS_RC;
> > +
> > + if (gen12_plane_has_mc_ccs(dev_priv, plane_id))
> > + plane_caps |= PLANE_HAS_CCS_MC;
> > +
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
> > 0, plane_funcs,
> > formats, num_formats, modifiers,
> > plane_type,
> > "plane %d%c", plane_id + 1,
> > pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 12256218634f4..a92228c922a54 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> > #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> > #define IS_DISPLAY_VER(i915, from, until) \
> > (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> > +#define DISPLAY_VER_BIT(d) BIT_ULL(d)
> > +#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
> > +#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
> >
> > #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
> >
> > --
> > 2.27.0
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c
2021-10-13 20:17 ` Ville Syrjälä
@ 2021-10-13 21:06 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-13 21:06 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:17:04PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 03:19:09AM +0300, Imre Deak wrote:
> > Move the function retrieving the format override information for a given
> > format/modifier to intel_fb.c. We can store a pointer to the format list
> > in each modifier's descriptor instead of the corresponding switch/case
> > logic, avoiding the listing of the modifiers twice.
> >
> > v2: Handle invalid modifiers in intel_fb_get_format_info() passed from
> > userspace.
>
> Do we have any tests for that btw?
Yes, that's how CI caught it: igt/kms_addfb_basic/addfb25-bad-modifier
>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 132 +--------------
> > drivers/gpu/drm/i915/display/intel_fb.c | 163 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_fb.h | 3 +
> > 3 files changed, 167 insertions(+), 131 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4f0badb11bbba..90802d16fbf91 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1087,136 +1087,6 @@ void intel_add_fb_offsets(int *x, int *y,
> > *y += state->view.color_plane[color_plane].y;
> > }
> >
> > -/*
> > - * From the Sky Lake PRM:
> > - * "The Color Control Surface (CCS) contains the compression status of
> > - * the cache-line pairs. The compression state of the cache-line pair
> > - * is specified by 2 bits in the CCS. Each CCS cache-line represents
> > - * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> > - * cache-line-pairs. CCS is always Y tiled."
> > - *
> > - * Since cache line pairs refers to horizontally adjacent cache lines,
> > - * each cache line in the CCS corresponds to an area of 32x16 cache
> > - * lines on the main surface. Since each pixel is 4 bytes, this gives
> > - * us a ratio of one byte in the CCS for each 8x16 pixels in the
> > - * main surface.
> > - */
> > -static const struct drm_format_info skl_ccs_formats[] = {
> > - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > -};
> > -
> > -/*
> > - * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> > - * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> > - * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> > - * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
> > - * the main surface.
> > - */
> > -static const struct drm_format_info gen12_ccs_formats[] = {
> > - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > - { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_VYUY, .num_planes = 2,
> > - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 2, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
> > - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > - .hsub = 1, .vsub = 1, .is_yuv = true },
> > - { .format = DRM_FORMAT_NV12, .num_planes = 4,
> > - .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
> > - .hsub = 2, .vsub = 2, .is_yuv = true },
> > - { .format = DRM_FORMAT_P010, .num_planes = 4,
> > - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > - .hsub = 2, .vsub = 2, .is_yuv = true },
> > - { .format = DRM_FORMAT_P012, .num_planes = 4,
> > - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > - .hsub = 2, .vsub = 2, .is_yuv = true },
> > - { .format = DRM_FORMAT_P016, .num_planes = 4,
> > - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > - .hsub = 2, .vsub = 2, .is_yuv = true },
> > -};
> > -
> > -/*
> > - * Same as gen12_ccs_formats[] above, but with additional surface used
> > - * to pass Clear Color information in plane 2 with 64 bits of data.
> > - */
> > -static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > - .hsub = 1, .vsub = 1, },
> > - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > - .hsub = 1, .vsub = 1, .has_alpha = true },
> > -};
> > -
> > -static const struct drm_format_info *
> > -lookup_format_info(const struct drm_format_info formats[],
> > - int num_formats, u32 format)
> > -{
> > - int i;
> > -
> > - for (i = 0; i < num_formats; i++) {
> > - if (formats[i].format == format)
> > - return &formats[i];
> > - }
> > -
> > - return NULL;
> > -}
> > -
> > -static const struct drm_format_info *
> > -intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> > -{
> > - switch (cmd->modifier[0]) {
> > - case I915_FORMAT_MOD_Y_TILED_CCS:
> > - case I915_FORMAT_MOD_Yf_TILED_CCS:
> > - return lookup_format_info(skl_ccs_formats,
> > - ARRAY_SIZE(skl_ccs_formats),
> > - cmd->pixel_format);
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > - return lookup_format_info(gen12_ccs_formats,
> > - ARRAY_SIZE(gen12_ccs_formats),
> > - cmd->pixel_format);
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > - return lookup_format_info(gen12_ccs_cc_formats,
> > - ARRAY_SIZE(gen12_ccs_cc_formats),
> > - cmd->pixel_format);
> > - default:
> > - return NULL;
> > - }
> > -}
> > -
> > u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> > u32 pixel_format, u64 modifier)
> > {
> > @@ -11270,7 +11140,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
> >
> > static const struct drm_mode_config_funcs intel_mode_funcs = {
> > .fb_create = intel_user_framebuffer_create,
> > - .get_format_info = intel_get_format_info,
> > + .get_format_info = intel_fb_get_format_info,
> > .output_poll_changed = intel_fbdev_output_poll_changed,
> > .mode_valid = intel_mode_valid,
> > .atomic_check = intel_atomic_check,
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 11a4c3e81cead..920de857ffa28 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,9 +13,108 @@
> >
> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> >
> > +/*
> > + * From the Sky Lake PRM:
> > + * "The Color Control Surface (CCS) contains the compression status of
> > + * the cache-line pairs. The compression state of the cache-line pair
> > + * is specified by 2 bits in the CCS. Each CCS cache-line represents
> > + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
> > + * cache-line-pairs. CCS is always Y tiled."
> > + *
> > + * Since cache line pairs refers to horizontally adjacent cache lines,
> > + * each cache line in the CCS corresponds to an area of 32x16 cache
> > + * lines on the main surface. Since each pixel is 4 bytes, this gives
> > + * us a ratio of one byte in the CCS for each 8x16 pixels in the
> > + * main surface.
> > + */
> > +static const struct drm_format_info skl_ccs_formats[] = {
> > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
> > +};
> > +
> > +/*
> > + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
> > + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
> > + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
> > + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
> > + * the main surface.
> > + */
> > +static const struct drm_format_info gen12_ccs_formats[] = {
> > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > + { .format = DRM_FORMAT_YUYV, .num_planes = 2,
> > + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 2, .vsub = 1, .is_yuv = true },
> > + { .format = DRM_FORMAT_YVYU, .num_planes = 2,
> > + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 2, .vsub = 1, .is_yuv = true },
> > + { .format = DRM_FORMAT_UYVY, .num_planes = 2,
> > + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 2, .vsub = 1, .is_yuv = true },
> > + { .format = DRM_FORMAT_VYUY, .num_planes = 2,
> > + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 2, .vsub = 1, .is_yuv = true },
> > + { .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
> > + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > + .hsub = 1, .vsub = 1, .is_yuv = true },
> > + { .format = DRM_FORMAT_NV12, .num_planes = 4,
> > + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
> > + .hsub = 2, .vsub = 2, .is_yuv = true },
> > + { .format = DRM_FORMAT_P010, .num_planes = 4,
> > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > + .hsub = 2, .vsub = 2, .is_yuv = true },
> > + { .format = DRM_FORMAT_P012, .num_planes = 4,
> > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > + .hsub = 2, .vsub = 2, .is_yuv = true },
> > + { .format = DRM_FORMAT_P016, .num_planes = 4,
> > + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
> > + .hsub = 2, .vsub = 2, .is_yuv = true },
> > +};
> > +
> > +/*
> > + * Same as gen12_ccs_formats[] above, but with additional surface used
> > + * to pass Clear Color information in plane 2 with 64 bits of data.
> > + */
> > +static const struct drm_format_info gen12_ccs_cc_formats[] = {
> > + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
> > + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
> > + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > + .hsub = 1, .vsub = 1, },
> > + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
> > + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
> > + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
> > + .hsub = 1, .vsub = 1, .has_alpha = true },
> > +};
> > +
> > +#define FORMAT_OVERRIDE(format_list) \
> > + .formats = format_list, \
> > + .format_count = ARRAY_SIZE(format_list)
> > +
> > const struct intel_modifier_desc {
> > u64 id;
> > u64 display_versions;
> > + const struct drm_format_info *formats;
> > + int format_count;
> > u8 is_linear:1;
> >
> > struct {
> > @@ -49,33 +148,97 @@ const struct intel_modifier_desc {
> > .display_versions = DISPLAY_VER_MASK(9, 11),
> >
> > .ccs.type = INTEL_CCS_RC,
> > +
> > + FORMAT_OVERRIDE(skl_ccs_formats),
> > },
> > {
> > .id = I915_FORMAT_MOD_Yf_TILED_CCS,
> > .display_versions = DISPLAY_VER_MASK(9, 11),
> >
> > .ccs.type = INTEL_CCS_RC,
> > +
> > + FORMAT_OVERRIDE(skl_ccs_formats),
> > },
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> >
> > .ccs.type = INTEL_CCS_RC,
> > +
> > + FORMAT_OVERRIDE(gen12_ccs_formats),
> > },
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> >
> > .ccs.type = INTEL_CCS_RC_CC,
> > +
> > + FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> > },
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> >
> > .ccs.type = INTEL_CCS_MC,
> > +
> > + FORMAT_OVERRIDE(gen12_ccs_formats),
> > },
> > };
> >
> > +static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
> > + if (intel_modifiers[i].id == modifier)
> > + return &intel_modifiers[i];
> > +
> > + return NULL;
> > +}
> > +
> > +static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
> > +{
> > + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
> > +
> > + if (WARN_ON(!md))
> > + return &intel_modifiers[0];
> > +
> > + return md;
> > +}
> > +
> > +static const struct drm_format_info *
> > +lookup_format_info(const struct drm_format_info formats[],
> > + int num_formats, u32 format)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < num_formats; i++) {
> > + if (formats[i].format == format)
> > + return &formats[i];
> > + }
> > +
> > + return NULL;
> > +}
> > +
> > +/**
> > + * intel_fb_get_format_info: Get a modifier specific format information
> > + * @cmd: FB add command structure
> > + *
> > + * Returns:
> > + * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
> > + * or %NULL if the modifier doesn't override the format.
> > + */
> > +const struct drm_format_info *
> > +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
> > +{
> > + const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
> > +
> > + if (!md || !md->formats)
> > + return NULL;
> > +
> > + return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
> > +}
> > +
> > static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type)
> > {
> > return md->ccs.type & ccs_type;
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
> > index 5bff88ccb9372..a87c58a3219cd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.h
> > @@ -39,6 +39,9 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
> > enum intel_plane_caps plane_caps);
> > bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier);
> >
> > +const struct drm_format_info *
> > +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd);
> > +
> > bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane);
> >
> > int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane);
> > --
> > 2.27.0
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor
2021-10-13 20:18 ` [Intel-gfx] [PATCH " Ville Syrjälä
@ 2021-10-13 21:08 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-13 21:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:18:27PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 07, 2021 at 11:35:09PM +0300, Imre Deak wrote:
> > Add a tiling atttribute to the modifier descriptor, which let's us
> > get the tiling without listing the modifiers twice.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_fb.c | 20 ++++++++------------
> > 1 file changed, 8 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 2543232580885..ef3cd375c9942 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -115,6 +115,7 @@ const struct intel_modifier_desc {
> > u64 display_versions;
> > const struct drm_format_info *formats;
> > int format_count;
> > + u8 tiling;
> >
> > struct {
> > #define INTEL_CCS_RC BIT(0)
> > @@ -132,10 +133,12 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_X_TILED,
> > .display_versions = DISPLAY_VER_MASK_ALL,
> > + .tiling = I915_TILING_X,
> > },
> > {
> > .id = I915_FORMAT_MOD_Y_TILED,
> > .display_versions = DISPLAY_VER_MASK(9, 13),
> > + .tiling = I915_TILING_Y,
> > },
> > {
> > .id = I915_FORMAT_MOD_Yf_TILED,
> > @@ -144,6 +147,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_CCS,
> > .display_versions = DISPLAY_VER_MASK(9, 11),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> >
> > @@ -160,6 +164,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC,
> >
> > @@ -168,6 +173,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_RC_CC,
> >
> > @@ -176,6 +182,7 @@ const struct intel_modifier_desc {
> > {
> > .id = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
> > .display_versions = DISPLAY_VER_MASK(12, 13),
> > + .tiling = I915_TILING_Y,
> >
> > .ccs.type = INTEL_CCS_MC,
> >
> > @@ -556,18 +563,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb,
> >
> > static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
> > {
> > - switch (fb_modifier) {
> > - case I915_FORMAT_MOD_X_TILED:
> > - return I915_TILING_X;
> > - case I915_FORMAT_MOD_Y_TILED:
> > - case I915_FORMAT_MOD_Y_TILED_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> > - return I915_TILING_Y;
> > - default:
> > - return I915_TILING_NONE;
>
> Had to double check that I915_TILING_NONE is really 0. It is.
Yea, I guess better to explicitly init it.
> > - }
> > + return lookup_modifier(fb_modifier)->tiling;
> > }
> >
> > unsigned int intel_cursor_alignment(const struct drm_i915_private *i915)
> > --
> > 2.27.0
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 20:45 ` Ville Syrjälä
@ 2021-10-13 21:32 ` Imre Deak
2021-10-13 21:54 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-13 21:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > Future platforms change the location of CCS control planes in CCS
> > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> >
> > Don't we use the term 'ccs_plane' everywhere else?
> >
> > > planes independently of the platform. This function can be used
> > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > since all the callers are only interested in control planes (and not CCS
> > > color-clear planes).
>
> Hmm. I guess you're changing the terminology across the board?
> If it's used consistently then no objections from me.
ccs_plane has been used as a generic term for both the "control" and the
cc plane, or at least I thought of it as such. I'm not sure if control
is a good name, but couldn't think of a better one. In any case I
thought calling the control plane ccs_plane is too generic, and would
make things clearer to use a more explicit term.
Function params and variables still use the ccs_plane name, though all
or most just handle ccs control planes.
main_to_ccs_plane() and skl_ccs_to_main_plane() should be renamed to
intel_fb_main_to_ccs_ctrl_plane() and intel_fb_ccs_ctrl_to_main_plane()
and change the latter one to assert that a control plane was passed.
IGT would also need the corresponding renames.
If you agree with the rational I can follow up with the above renames.
Otherwise we could just continue calling the control plane ccs_plane and
the cc plane ccs_cc_plane.
> > > Add the corresponding intel_fb_is_gen12_ccs_ctrl_plane(), which can be
> > > used everywhere instead of is_gen12_ccs_plane(), based on the above
> > > explanation.
> > >
> > > This change also unexports the is_gen12_ccs_modifier(),
> > > is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only
> > > used in intel_fb.c
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 7 --
> > > drivers/gpu/drm/i915/display/intel_fb.c | 73 ++++++++++++++-----
> > > drivers/gpu/drm/i915/display/intel_fb.h | 5 +-
> > > .../drm/i915/display/skl_universal_plane.c | 3 +-
> > > 4 files changed, 56 insertions(+), 32 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index bb53b01f07aee..b4b6a31caf4e3 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -2050,11 +2050,4 @@ static inline bool is_ccs_modifier(u64 modifier)
> > > modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> > > }
> > >
> > > -static inline bool is_gen12_ccs_modifier(u64 modifier)
> > > -{
> > > - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> > > - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> > > - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> > > -}
> > > -
> > > #endif /* __INTEL_DISPLAY_TYPES_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index e8fe198b1b6a1..392f89e659eb6 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -125,6 +125,8 @@ const struct intel_modifier_desc {
> > > #define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > > u8 type:3;
> > > u8 cc_planes:3;
> > > + u8 packed_ctrl_planes:4;
> > > + u8 planar_ctrl_planes:4;
> > > } ccs;
> > > } intel_modifiers[] = {
> > > {
> > > @@ -151,6 +153,7 @@ const struct intel_modifier_desc {
> > > .tiling = I915_TILING_Y,
> > >
> > > .ccs.type = INTEL_CCS_RC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > >
> > > FORMAT_OVERRIDE(skl_ccs_formats),
> > > },
> > > @@ -159,6 +162,7 @@ const struct intel_modifier_desc {
> > > .display_versions = DISPLAY_VER_MASK(9, 11),
> > >
> > > .ccs.type = INTEL_CCS_RC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > >
> > > FORMAT_OVERRIDE(skl_ccs_formats),
> > > },
> > > @@ -168,6 +172,7 @@ const struct intel_modifier_desc {
> > > .tiling = I915_TILING_Y,
> > >
> > > .ccs.type = INTEL_CCS_RC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > >
> > > FORMAT_OVERRIDE(gen12_ccs_formats),
> > > },
> > > @@ -177,6 +182,7 @@ const struct intel_modifier_desc {
> > > .tiling = I915_TILING_Y,
> > >
> > > .ccs.type = INTEL_CCS_RC_CC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > > .ccs.cc_planes = BIT(2),
> > >
> > > FORMAT_OVERRIDE(gen12_ccs_cc_formats),
> > > @@ -187,6 +193,8 @@ const struct intel_modifier_desc {
> > > .tiling = I915_TILING_Y,
> > >
> > > .ccs.type = INTEL_CCS_MC,
> > > + .ccs.packed_ctrl_planes = BIT(1),
> > > + .ccs.planar_ctrl_planes = BIT(2) | BIT(3),
> > >
> > > FORMAT_OVERRIDE(gen12_ccs_formats),
> > > },
> > > @@ -385,17 +393,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
> > > return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
> > > }
> > >
> > > -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > > +static u8 ccs_ctrl_plane_mask(const struct intel_modifier_desc *md,
> > > + const struct drm_format_info *format)
> > > {
> > > - if (!is_ccs_modifier(fb->modifier))
> > > - return false;
> > > + if (format_is_yuv_semiplanar(md, format))
> > > + return md->ccs.planar_ctrl_planes;
> > > + else
> > > + return md->ccs.packed_ctrl_planes;
> > > +}
> > > +
> > > +/**
> > > + * intel_fb_is_ccs_ctrl_plane: Check if a framebuffer color plane is a CCS control plane
> > > + * @fb: Framebuffer
> > > + * @plane: color plane index to check
> > > + *
> > > + * Returns:
> > > + * Returns %true if @fb's color plane at index @plane is a CCS control plane.
> > > + */
> > > +bool intel_fb_is_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> > > +{
> > > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> > >
> > > - return plane >= fb->format->num_planes / 2;
> > > + return ccs_ctrl_plane_mask(md, fb->format) & BIT(plane);
> > > }
> > >
> > > -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > > +/**
> > > + * intel_fb_is_gen12_ccs_ctrl_plane: Check if a framebuffer color plane is a GEN12 CCS control plane
> > > + * @fb: Framebuffer
> > > + * @plane: color plane index to check
> > > + *
> > > + * Returns:
> > > + * Returns %true if @fb's color plane at index @plane is a GEN12 CCS control plane.
> > > + */
> > > +static bool intel_fb_is_gen12_ccs_ctrl_plane(const struct drm_framebuffer *fb, int plane)
> > > {
> > > - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
> > > + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> > > +
> > > + return md->display_versions & (DISPLAY_VER_MASK(12, 13)) &&
>
> Aha! No RPN here ;)
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-13 21:01 ` Imre Deak
@ 2021-10-13 21:34 ` Ville Syrjälä
0 siblings, 0 replies; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 21:34 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 12:01:41AM +0300, Imre Deak wrote:
> On Wed, Oct 13, 2021 at 11:14:42PM +0300, Ville Syrjälä wrote:
> > On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> > > + /* Wa_22011186057 */
> > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> > > + return false;
> > > +
> > > + if (DISPLAY_VER(i915) >= 11)
> > > + return true;
> > > +
> > > + if (IS_GEMINILAKE(i915))
> > > + return pipe != PIPE_C;
> > > +
> > > + return pipe != PIPE_C &&
> > > + (plane_id == PLANE_PRIMARY ||
> > > + plane_id == PLANE_SPRITE0);
> > > +}
> >
> > A bit tempted to say we should chop this up into more
> > platform specific variants. But that can be left for later I guess.
>
> You mean clarifying that last check is for SKL/BXT? Would a code comment
> be ok?
I don't really enjoy comments when the code can express what we
mean more clearly. So I'm thinking just a clean skl/glk/icl split
could perhaps be the thing. Pretty sure we have that exact if
ladder in the init function already at least once so could
shove this stuff in there as well.
But it's not really important for the moment.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 21:32 ` Imre Deak
@ 2021-10-13 21:54 ` Ville Syrjälä
2021-10-13 22:28 ` Imre Deak
0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 21:54 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote:
> On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > > Future platforms change the location of CCS control planes in CCS
> > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> > >
> > > Don't we use the term 'ccs_plane' everywhere else?
> > >
> > > > planes independently of the platform. This function can be used
> > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > > since all the callers are only interested in control planes (and not CCS
> > > > color-clear planes).
> >
> > Hmm. I guess you're changing the terminology across the board?
> > If it's used consistently then no objections from me.
>
> ccs_plane has been used as a generic term for both the "control" and the
> cc plane, or at least I thought of it as such.
The official definition I think is:
CCS == color control surface
So in terms of modifier naming I suppose I tend to think
of it like this:
modifier name has CCS -> color control surface is present
modifier name has CC -> clear color is present
But if we want to make the distinction somehow stronger I was
thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up
being more confusing since AUX_DIST is also used for planar scanout
on skl/etc.
Or another way to make it more clear would be to drop the "ccs" part
from the is_ccs_cc_plane() or whatever. But is_cc_plane() is perhaps
also pretty confusing. So could expand it to full on is_clear_color_plane()?
Shrug. Plenty of different color paint for this one available I think.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 21:54 ` Ville Syrjälä
@ 2021-10-13 22:28 ` Imre Deak
2021-10-13 22:38 ` Ville Syrjälä
0 siblings, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-13 22:28 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 12:54:58AM +0300, Ville Syrjälä wrote:
> On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote:
> > On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> > > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > > > Future platforms change the location of CCS control planes in CCS
> > > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> > > >
> > > > Don't we use the term 'ccs_plane' everywhere else?
> > > >
> > > > > planes independently of the platform. This function can be used
> > > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > > > since all the callers are only interested in control planes (and not CCS
> > > > > color-clear planes).
> > >
> > > Hmm. I guess you're changing the terminology across the board?
> > > If it's used consistently then no objections from me.
> >
> > ccs_plane has been used as a generic term for both the "control" and the
> > cc plane, or at least I thought of it as such.
>
> The official definition I think is:
> CCS == color control surface
>
> So in terms of modifier naming I suppose I tend to think
> of it like this:
> modifier name has CCS -> color control surface is present
> modifier name has CC -> clear color is present
>
> But if we want to make the distinction somehow stronger I was
> thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up
> being more confusing since AUX_DIST is also used for planar scanout
> on skl/etc.
>
> Or another way to make it more clear would be to drop the "ccs" part
> from the is_ccs_cc_plane() or whatever. But is_cc_plane() is perhaps
> also pretty confusing. So could expand it to full on is_clear_color_plane()?
Imo it's better to preserve the connection to ccs in the name, maybe
regarding the cc as a subplane of the ccs plane.
> Shrug. Plenty of different color paint for this one available I think.
Ok with all that, I think the best would be to use the ccs_plane /
ccs_cc_plane names to mean the control plane and clear color plane.
Will change the patch.
--Imre
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 22:28 ` Imre Deak
@ 2021-10-13 22:38 ` Ville Syrjälä
2021-10-14 10:10 ` Imre Deak
0 siblings, 1 reply; 53+ messages in thread
From: Ville Syrjälä @ 2021-10-13 22:38 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 01:28:24AM +0300, Imre Deak wrote:
> On Thu, Oct 14, 2021 at 12:54:58AM +0300, Ville Syrjälä wrote:
> > On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote:
> > > On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> > > > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > > > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > > > > Future platforms change the location of CCS control planes in CCS
> > > > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> > > > >
> > > > > Don't we use the term 'ccs_plane' everywhere else?
> > > > >
> > > > > > planes independently of the platform. This function can be used
> > > > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > > > > since all the callers are only interested in control planes (and not CCS
> > > > > > color-clear planes).
> > > >
> > > > Hmm. I guess you're changing the terminology across the board?
> > > > If it's used consistently then no objections from me.
> > >
> > > ccs_plane has been used as a generic term for both the "control" and the
> > > cc plane, or at least I thought of it as such.
> >
> > The official definition I think is:
> > CCS == color control surface
> >
> > So in terms of modifier naming I suppose I tend to think
> > of it like this:
> > modifier name has CCS -> color control surface is present
> > modifier name has CC -> clear color is present
> >
> > But if we want to make the distinction somehow stronger I was
> > thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up
> > being more confusing since AUX_DIST is also used for planar scanout
> > on skl/etc.
I guess the fact that it would also say "ccs" in additon to "aux"
would make it ok. So ccs_aux goes into AUX_DIST, ccs_cc goes into CC_VAL.
But anyway, as long we go with something consitent everywhere I'll be
happy.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH v2 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-13 20:40 ` Ville Syrjälä
@ 2021-10-14 10:07 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-14 10:07 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Oct 13, 2021 at 11:40:11PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 08, 2021 at 03:19:08AM +0300, Imre Deak wrote:
> > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane);
> > bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane);
> > bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane);
>
> Side note:
> We have quite a few of these 'int plane' things still around. I'd
> like to see them all renamed to 'color_plane' so that we don't get
> confused between diffrent kinds of planes.
>
> The rules that I've been going for everywhere:
> - int color_plane == plane of a planar/compressed framebuffer
> - struct intel_plane *plane == representation of the piece of
> hardware that does the scanout
> - enum plane plane_id == standalone version of plane->id
> - enum i9xx_plane_id i9xx_plane == standalone version of plane->i9xx_plane
Ok, makes sense, I'll s/plane/color_plane/ in functions I added in this
patchset and will follow up to convert the remaining ones.
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for CCS control planes
2021-10-13 22:38 ` Ville Syrjälä
@ 2021-10-14 10:10 ` Imre Deak
0 siblings, 0 replies; 53+ messages in thread
From: Imre Deak @ 2021-10-14 10:10 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 01:38:14AM +0300, Ville Syrjälä wrote:
> On Thu, Oct 14, 2021 at 01:28:24AM +0300, Imre Deak wrote:
> > On Thu, Oct 14, 2021 at 12:54:58AM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 14, 2021 at 12:32:55AM +0300, Imre Deak wrote:
> > > > On Wed, Oct 13, 2021 at 11:45:33PM +0300, Ville Syrjälä wrote:
> > > > > On Wed, Oct 13, 2021 at 11:27:02PM +0300, Ville Syrjälä wrote:
> > > > > > On Thu, Oct 07, 2021 at 11:35:15PM +0300, Imre Deak wrote:
> > > > > > > Future platforms change the location of CCS control planes in CCS
> > > > > > > framebuffers, so add intel_fb_is_rc_ccs_ctrl_plane() to query for these
> > > > > >
> > > > > > Don't we use the term 'ccs_plane' everywhere else?
> > > > > >
> > > > > > > planes independently of the platform. This function can be used
> > > > > > > everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()),
> > > > > > > since all the callers are only interested in control planes (and not CCS
> > > > > > > color-clear planes).
> > > > >
> > > > > Hmm. I guess you're changing the terminology across the board?
> > > > > If it's used consistently then no objections from me.
> > > >
> > > > ccs_plane has been used as a generic term for both the "control" and the
> > > > cc plane, or at least I thought of it as such.
> > >
> > > The official definition I think is:
> > > CCS == color control surface
> > >
> > > So in terms of modifier naming I suppose I tend to think
> > > of it like this:
> > > modifier name has CCS -> color control surface is present
> > > modifier name has CC -> clear color is present
> > >
> > > But if we want to make the distinction somehow stronger I was
> > > thinking maybe ccs_aux vs. ccs_cc. But dunno if that just ends up
> > > being more confusing since AUX_DIST is also used for planar scanout
> > > on skl/etc.
>
> I guess the fact that it would also say "ccs" in additon to "aux"
> would make it ok. So ccs_aux goes into AUX_DIST, ccs_cc goes into CC_VAL.
Ok, ccs_aux works I guess, and it's actually used at a few places
already. So yes, not too consistent atm, will use ccs_aux in this
patchset and rename the remaining instances in a follow-up patch.
> But anyway, as long we go with something consitent everywhere I'll be
> happy.
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
2021-10-07 21:10 ` Ville Syrjälä
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
@ 2021-10-14 14:07 ` Jani Nikula
2021-10-14 14:16 ` Jani Nikula
2021-10-14 15:03 ` Imre Deak
2 siblings, 2 replies; 53+ messages in thread
From: Jani Nikula @ 2021-10-14 14:07 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Thu, 07 Oct 2021, Imre Deak <imre.deak@intel.com> wrote:
> Add a table describing all the framebuffer modifiers used by i915 at one
> place. This has the benefit of deduplicating the listing of supported
> modifiers for each platform and checking the support of these modifiers
> on a given plane. This also simplifies in a similar way getting some
> attribute for a modifier, for instance checking if the modifier is a
> CCS modifier type.
Just some high level comments inline.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> .../drm/i915/display/intel_display_types.h | 1 -
> drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> 8 files changed, 218 insertions(+), 164 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index f6dcb5aa63f64..bcd44ff30ce5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> DRM_FORMAT_ARGB8888,
> };
>
> -static const u64 cursor_format_modifiers[] = {
> - DRM_FORMAT_MOD_LINEAR,
> - DRM_FORMAT_MOD_INVALID
> -};
> -
> static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> u32 format, u64 modifier)
> {
> - return modifier == DRM_FORMAT_MOD_LINEAR &&
> - format == DRM_FORMAT_ARGB8888;
> + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> + return false;
> +
> + return format == DRM_FORMAT_ARGB8888;
> }
>
> static int
> @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> {
> struct intel_plane *cursor;
> int ret, zpos;
> + u64 *modifiers;
>
> cursor = intel_plane_alloc();
> if (IS_ERR(cursor))
> @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> cursor->cursor.size = ~0;
>
> + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> +
> ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> 0, &intel_cursor_plane_funcs,
> intel_cursor_formats,
> ARRAY_SIZE(intel_cursor_formats),
> - cursor_format_modifiers,
> + modifiers,
> DRM_PLANE_TYPE_CURSOR,
> "cursor %c", pipe_name(pipe));
> +
> + kfree(modifiers);
> +
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 21ce8bccc645a..bb53b01f07aee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1336,7 +1336,6 @@ struct intel_plane {
> enum plane_id id;
> enum pipe pipe;
> bool has_fbc;
> - bool has_ccs;
> bool need_async_flip_disable_wa;
> u32 frontbuffer_bit;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index fa1f375e696bf..aefae988b620b 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -13,6 +13,184 @@
>
> #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
>
> +const struct intel_modifier_desc {
static?
Maybe split the struct declaration and the array definition for
clarity. *shrug*
> + u64 id;
> + u64 display_versions;
> +
> + struct {
> +#define INTEL_CCS_RC BIT(0)
> +#define INTEL_CCS_RC_CC BIT(1)
> +#define INTEL_CCS_MC BIT(2)
> +
> +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> + u8 type:3;
> + } ccs;
> +} intel_modifiers[] = {
> + {
> + .id = DRM_FORMAT_MOD_LINEAR,
> + .display_versions = DISPLAY_VER_MASK_ALL,
What is this going to look like when display version mask isn't fine
grained enough to cover all the platforms? Do we have cases like that
already?
[snip]
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12256218634f4..a92228c922a54 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> +#define DISPLAY_VER_BIT(d) BIT_ULL(d)
> +#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
> +#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
Do we want to promote this usage all over the place? Maybe keep them
internal to intel_fb.c?
Or just add both from and until members in intel_modifier_desc, and use
the regular IS_DISPLAY_VER() in intel_fb.c as well. It's not worse
considering the mask you have is u64. You could have two u8's
instead. You could consider 0 for either to mean "no limit", and skip
the initialization instead of duplicating .display_versions =
DISPLAY_VER_MASK_ALL.
I think I'd prefer that. Or do you see masks with gaps in them?
BR,
Jani.
>
> #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-14 14:07 ` [Intel-gfx] [PATCH " Jani Nikula
@ 2021-10-14 14:16 ` Jani Nikula
2021-10-14 15:03 ` Imre Deak
1 sibling, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2021-10-14 14:16 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Thu, 14 Oct 2021, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 07 Oct 2021, Imre Deak <imre.deak@intel.com> wrote:
>> +} intel_modifiers[] = {
>> + {
>> + .id = DRM_FORMAT_MOD_LINEAR,
>> + .display_versions = DISPLAY_VER_MASK_ALL,
>
> What is this going to look like when display version mask isn't fine
> grained enough to cover all the platforms? Do we have cases like that
> already?
Day-dreaming, would be nice if we could turn our IS_PLATFORM() macros to
functions, and pass them as function pointers in places like this. Or
have lambda functions here.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-14 14:07 ` [Intel-gfx] [PATCH " Jani Nikula
2021-10-14 14:16 ` Jani Nikula
@ 2021-10-14 15:03 ` Imre Deak
2021-10-14 15:48 ` Jani Nikula
1 sibling, 1 reply; 53+ messages in thread
From: Imre Deak @ 2021-10-14 15:03 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Oct 14, 2021 at 05:07:16PM +0300, Jani Nikula wrote:
> On Thu, 07 Oct 2021, Imre Deak <imre.deak@intel.com> wrote:
> > Add a table describing all the framebuffer modifiers used by i915 at one
> > place. This has the benefit of deduplicating the listing of supported
> > modifiers for each platform and checking the support of these modifiers
> > on a given plane. This also simplifies in a similar way getting some
> > attribute for a modifier, for instance checking if the modifier is a
> > CCS modifier type.
>
> Just some high level comments inline.
>
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
> > .../drm/i915/display/intel_display_types.h | 1 -
> > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
> > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
> > drivers/gpu/drm/i915/i915_drv.h | 3 +
> > 8 files changed, 218 insertions(+), 164 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index f6dcb5aa63f64..bcd44ff30ce5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
> > DRM_FORMAT_ARGB8888,
> > };
> >
> > -static const u64 cursor_format_modifiers[] = {
> > - DRM_FORMAT_MOD_LINEAR,
> > - DRM_FORMAT_MOD_INVALID
> > -};
> > -
> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
> > {
> > struct drm_i915_private *dev_priv =
> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
> > u32 format, u64 modifier)
> > {
> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
> > - format == DRM_FORMAT_ARGB8888;
> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
> > + return false;
> > +
> > + return format == DRM_FORMAT_ARGB8888;
> > }
> >
> > static int
> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > {
> > struct intel_plane *cursor;
> > int ret, zpos;
> > + u64 *modifiers;
> >
> > cursor = intel_plane_alloc();
> > if (IS_ERR(cursor))
> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
> > cursor->cursor.size = ~0;
> >
> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
> > +
> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
> > 0, &intel_cursor_plane_funcs,
> > intel_cursor_formats,
> > ARRAY_SIZE(intel_cursor_formats),
> > - cursor_format_modifiers,
> > + modifiers,
> > DRM_PLANE_TYPE_CURSOR,
> > "cursor %c", pipe_name(pipe));
> > +
> > + kfree(modifiers);
> > +
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645a..bb53b01f07aee 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1336,7 +1336,6 @@ struct intel_plane {
> > enum plane_id id;
> > enum pipe pipe;
> > bool has_fbc;
> > - bool has_ccs;
> > bool need_async_flip_disable_wa;
> > u32 frontbuffer_bit;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> > index fa1f375e696bf..aefae988b620b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -13,6 +13,184 @@
> >
> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
> >
> > +const struct intel_modifier_desc {
>
> static?
Yes, will fix this.
> Maybe split the struct declaration and the array definition for
> clarity. *shrug*
Ok.
> > + u64 id;
> > + u64 display_versions;
> > +
> > + struct {
> > +#define INTEL_CCS_RC BIT(0)
> > +#define INTEL_CCS_RC_CC BIT(1)
> > +#define INTEL_CCS_MC BIT(2)
> > +
> > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
> > + u8 type:3;
> > + } ccs;
> > +} intel_modifiers[] = {
> > + {
> > + .id = DRM_FORMAT_MOD_LINEAR,
> > + .display_versions = DISPLAY_VER_MASK_ALL,
>
> What is this going to look like when display version mask isn't fine
> grained enough to cover all the platforms? Do we have cases like that
> already?
Display 13 platforms will have different modifiers enabled, but they can
be distinguished with a modifier attribute.
> [snip]
>
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 12256218634f4..a92228c922a54 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
> > #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
> > #define IS_DISPLAY_VER(i915, from, until) \
> > (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
> > +#define DISPLAY_VER_BIT(d) BIT_ULL(d)
> > +#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
> > +#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
>
> Do we want to promote this usage all over the place? Maybe keep them
> internal to intel_fb.c?
>
> Or just add both from and until members in intel_modifier_desc, and use
> the regular IS_DISPLAY_VER() in intel_fb.c as well. It's not worse
> considering the mask you have is u64. You could have two u8's
> instead.
>
> You could consider 0 for either to mean "no limit", and skip
> the initialization instead of duplicating .display_versions =
> DISPLAY_VER_MASK_ALL.
>
> I think I'd prefer that. Or do you see masks with gaps in them?
No, just continuous ranges atm.
Ok, I can change these to two u8s instead, though I would prefer the
simpler way of checking a bitmask. But yes, it requires a u64 (or u32
which would be enough for now).
> BR,
> Jani.
>
>
> >
> > #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers
2021-10-14 15:03 ` Imre Deak
@ 2021-10-14 15:48 ` Jani Nikula
0 siblings, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2021-10-14 15:48 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, 14 Oct 2021, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Oct 14, 2021 at 05:07:16PM +0300, Jani Nikula wrote:
>> On Thu, 07 Oct 2021, Imre Deak <imre.deak@intel.com> wrote:
>> > Add a table describing all the framebuffer modifiers used by i915 at one
>> > place. This has the benefit of deduplicating the listing of supported
>> > modifiers for each platform and checking the support of these modifiers
>> > on a given plane. This also simplifies in a similar way getting some
>> > attribute for a modifier, for instance checking if the modifier is a
>> > CCS modifier type.
>>
>> Just some high level comments inline.
>>
>> >
>> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
>> > .../drm/i915/display/intel_display_types.h | 1 -
>> > drivers/gpu/drm/i915/display/intel_fb.c | 178 ++++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_fb.h | 8 +
>> > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +---
>> > drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
>> > .../drm/i915/display/skl_universal_plane.c | 137 +-------------
>> > drivers/gpu/drm/i915/i915_drv.h | 3 +
>> > 8 files changed, 218 insertions(+), 164 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
>> > index f6dcb5aa63f64..bcd44ff30ce5b 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
>> > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = {
>> > DRM_FORMAT_ARGB8888,
>> > };
>> >
>> > -static const u64 cursor_format_modifiers[] = {
>> > - DRM_FORMAT_MOD_LINEAR,
>> > - DRM_FORMAT_MOD_INVALID
>> > -};
>> > -
>> > static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
>> > {
>> > struct drm_i915_private *dev_priv =
>> > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
>> > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
>> > u32 format, u64 modifier)
>> > {
>> > - return modifier == DRM_FORMAT_MOD_LINEAR &&
>> > - format == DRM_FORMAT_ARGB8888;
>> > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
>> > + return false;
>> > +
>> > + return format == DRM_FORMAT_ARGB8888;
>> > }
>> >
>> > static int
>> > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>> > {
>> > struct intel_plane *cursor;
>> > int ret, zpos;
>> > + u64 *modifiers;
>> >
>> > cursor = intel_plane_alloc();
>> > if (IS_ERR(cursor))
>> > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
>> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
>> > cursor->cursor.size = ~0;
>> >
>> > + modifiers = intel_fb_plane_get_modifiers(dev_priv, pipe, cursor->id);
>> > +
>> > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
>> > 0, &intel_cursor_plane_funcs,
>> > intel_cursor_formats,
>> > ARRAY_SIZE(intel_cursor_formats),
>> > - cursor_format_modifiers,
>> > + modifiers,
>> > DRM_PLANE_TYPE_CURSOR,
>> > "cursor %c", pipe_name(pipe));
>> > +
>> > + kfree(modifiers);
>> > +
>> > if (ret)
>> > goto fail;
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> > index 21ce8bccc645a..bb53b01f07aee 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> > @@ -1336,7 +1336,6 @@ struct intel_plane {
>> > enum plane_id id;
>> > enum pipe pipe;
>> > bool has_fbc;
>> > - bool has_ccs;
>> > bool need_async_flip_disable_wa;
>> > u32 frontbuffer_bit;
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
>> > index fa1f375e696bf..aefae988b620b 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
>> > @@ -13,6 +13,184 @@
>> >
>> > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
>> >
>> > +const struct intel_modifier_desc {
>>
>> static?
>
> Yes, will fix this.
>
>> Maybe split the struct declaration and the array definition for
>> clarity. *shrug*
>
> Ok.
>
>> > + u64 id;
>> > + u64 display_versions;
>> > +
>> > + struct {
>> > +#define INTEL_CCS_RC BIT(0)
>> > +#define INTEL_CCS_RC_CC BIT(1)
>> > +#define INTEL_CCS_MC BIT(2)
>> > +
>> > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC)
>> > + u8 type:3;
>> > + } ccs;
>> > +} intel_modifiers[] = {
>> > + {
>> > + .id = DRM_FORMAT_MOD_LINEAR,
>> > + .display_versions = DISPLAY_VER_MASK_ALL,
>>
>> What is this going to look like when display version mask isn't fine
>> grained enough to cover all the platforms? Do we have cases like that
>> already?
>
> Display 13 platforms will have different modifiers enabled, but they can
> be distinguished with a modifier attribute.
>
>> [snip]
>>
>> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> > index 12256218634f4..a92228c922a54 100644
>> > --- a/drivers/gpu/drm/i915/i915_drv.h
>> > +++ b/drivers/gpu/drm/i915/i915_drv.h
>> > @@ -1342,6 +1342,9 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
>> > #define DISPLAY_VER(i915) (INTEL_INFO(i915)->display.ver)
>> > #define IS_DISPLAY_VER(i915, from, until) \
>> > (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>> > +#define DISPLAY_VER_BIT(d) BIT_ULL(d)
>> > +#define DISPLAY_VER_MASK(f, u) GENMASK_ULL(u, f)
>> > +#define DISPLAY_VER_MASK_ALL DISPLAY_VER_MASK(0, BITS_PER_LONG_LONG - 1)
>>
>> Do we want to promote this usage all over the place? Maybe keep them
>> internal to intel_fb.c?
>>
>> Or just add both from and until members in intel_modifier_desc, and use
>> the regular IS_DISPLAY_VER() in intel_fb.c as well. It's not worse
>> considering the mask you have is u64. You could have two u8's
>> instead.
>>
>> You could consider 0 for either to mean "no limit", and skip
>> the initialization instead of duplicating .display_versions =
>> DISPLAY_VER_MASK_ALL.
>>
>> I think I'd prefer that. Or do you see masks with gaps in them?
>
> No, just continuous ranges atm.
>
> Ok, I can change these to two u8s instead, though I would prefer the
> simpler way of checking a bitmask. But yes, it requires a u64 (or u32
> which would be enough for now).
Simplicity is in the eye of the beholder. ;)
if (!(DISPLAY_VER_BIT(DISPLAY_VER(i915)) & md->display_versions))
return false;
vs.
if (!IS_DISPLAY_VER(i915, md->display_ver_from, md->display_ver_until))
return false;
But okay, to omit the initializations you also need some more magic
here.
BR,
Jani.
>
>> BR,
>> Jani.
>>
>>
>> >
>> > #define INTEL_REVID(dev_priv) (to_pci_dev((dev_priv)->drm.dev)->revision)
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 53+ messages in thread
end of thread, other threads:[~2021-10-14 15:48 UTC | newest]
Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-07 20:35 [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
2021-10-07 21:10 ` Ville Syrjälä
2021-10-07 21:26 ` Imre Deak
2021-10-07 21:32 ` Ville Syrjälä
2021-10-07 22:00 ` Imre Deak
2021-10-08 9:41 ` Ville Syrjälä
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:14 ` Ville Syrjälä
2021-10-13 21:01 ` Imre Deak
2021-10-13 21:34 ` Ville Syrjälä
2021-10-13 20:40 ` Ville Syrjälä
2021-10-14 10:07 ` Imre Deak
2021-10-14 14:07 ` [Intel-gfx] [PATCH " Jani Nikula
2021-10-14 14:16 ` Jani Nikula
2021-10-14 15:03 ` Imre Deak
2021-10-14 15:48 ` Jani Nikula
2021-10-07 20:35 ` [Intel-gfx] [PATCH 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:17 ` Ville Syrjälä
2021-10-13 21:06 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:18 ` [Intel-gfx] [PATCH " Ville Syrjälä
2021-10-13 21:08 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 08/11] drm/i915: Handle CCS CC planes separately from CCS control planes Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 09/11] drm/i915: Add a platform independent way to check for " Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-13 20:27 ` [Intel-gfx] [PATCH " Ville Syrjälä
2021-10-13 20:45 ` Ville Syrjälä
2021-10-13 21:32 ` Imre Deak
2021-10-13 21:54 ` Ville Syrjälä
2021-10-13 22:28 ` Imre Deak
2021-10-13 22:38 ` Ville Syrjälä
2021-10-14 10:10 ` Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 20:35 ` [Intel-gfx] [PATCH 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak
2021-10-08 0:19 ` [Intel-gfx] [PATCH v2 " Imre Deak
2021-10-07 21:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers Patchwork
2021-10-07 21:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-07 21:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-08 0:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev9) Patchwork
2021-10-08 0:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-08 1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-08 2:15 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-13 19:41 ` [Intel-gfx] [PATCH 00/11] drm/i915: Simplify handling of modifiers Juha-Pekka Heikkila
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