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From: "tip-bot2 for Kan Liang" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Kan Liang <kan.liang@linux.intel.com>,
	"Peter Zijlstra (Intel)" <peterz@infradead.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: perf/urgent] perf/x86/msr: Add Sapphire Rapids CPU support
Date: Fri, 15 Oct 2021 09:32:00 -0000	[thread overview]
Message-ID: <163429032051.25758.2605197618414983019.tip-bot2@tip-bot2> (raw)
In-Reply-To: <1633551137-192083-1-git-send-email-kan.liang@linux.intel.com>

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     71920ea97d6d1d800ee8b51951dc3fda3f5dc698
Gitweb:        https://git.kernel.org/tip/71920ea97d6d1d800ee8b51951dc3fda3f5dc698
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Wed, 06 Oct 2021 13:12:17 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 15 Oct 2021 11:25:26 +02:00

perf/x86/msr: Add Sapphire Rapids CPU support

SMI_COUNT MSR is supported on Sapphire Rapids CPU.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1633551137-192083-1-git-send-email-kan.liang@linux.intel.com
---
 arch/x86/events/msr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index c853b28..96c775a 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -68,6 +68,7 @@ static bool test_intel(int idx, void *data)
 	case INTEL_FAM6_BROADWELL_D:
 	case INTEL_FAM6_BROADWELL_G:
 	case INTEL_FAM6_BROADWELL_X:
+	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 
 	case INTEL_FAM6_ATOM_SILVERMONT:
 	case INTEL_FAM6_ATOM_SILVERMONT_D:

      reply	other threads:[~2021-10-15  9:32 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-06 20:12 [PATCH] perf/x86/msr: Add Sapphire Rapids CPU support kan.liang
2021-10-15  9:32 ` tip-bot2 for Kan Liang [this message]

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