From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Imre Deak" <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
Date: Mon, 18 Oct 2021 18:01:55 -0000 [thread overview]
Message-ID: <163458011515.27089.13103387203788649803@emeril.freedesktop.org> (raw)
In-Reply-To: <20211018094154.1407705-1-imre.deak@intel.com>
== Series Details ==
Series: drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2)
URL : https://patchwork.freedesktop.org/series/95948/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f1a6421dfe5 drm/i915/dp: Skip the HW readout of DPCD on disabled encoders
4de2ca096081 drm/i915/dp: Ensure sink rate values are always valid
-:42: WARNING:TYPO_SPELLING: 'initialzing' may be misspelled - perhaps 'initializing'?
#42:
v2: Clear the default sink rates, before initialzing these for eDP.
^^^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 29 lines checked
ef437e0c551b drm/i915/dp: Ensure max link params are always valid
66b542816538 drm/i915/dp: Ensure sink/link max lane count values are always valid
f2bd5e3e941b drm/i915/dp: Sanitize sink rate DPCD register values
-:15: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#15:
buggy monitor). So fixup the invalid DPCD sink rate values already and print
total: 0 errors, 1 warnings, 0 checks, 33 lines checked
d94f0647dd78 drm/i915/dp: Sanitize link common rate array lookups
-:45: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#45: FILE: drivers/gpu/drm/i915/display/intel_dp.c:622:
+ intel_dp_common_rate(intel_dp, index - 1),
total: 0 errors, 1 warnings, 0 checks, 77 lines checked
next prev parent reply other threads:[~2021-10-18 18:01 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-18 9:41 [Intel-gfx] [PATCH 0/6] drm/i915/dp: Fix link parameter use in lack of a valid DPCD Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 1/6] drm/i915/dp: Skip the HW readout of DPCD on disabled encoders Imre Deak
2021-10-18 9:41 ` Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 2/6] drm/i915/dp: Ensure sink rate values are always valid Imre Deak
2021-10-18 9:41 ` Imre Deak
2021-10-18 14:34 ` [PATCH v2 " Imre Deak
2021-10-18 14:34 ` [Intel-gfx] " Imre Deak
2021-10-19 7:27 ` [Intel-gfx] [PATCH " Jani Nikula
2021-10-19 7:33 ` Imre Deak
2021-10-19 7:37 ` Jani Nikula
2021-10-19 7:39 ` Imre Deak
2021-10-19 18:37 ` Imre Deak
2021-10-19 19:17 ` Jani Nikula
2021-10-18 9:41 ` [Intel-gfx] [PATCH 3/6] drm/i915/dp: Ensure max link params " Imre Deak
2021-10-18 9:41 ` Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values " Imre Deak
2021-10-18 15:04 ` Ville Syrjälä
2021-10-18 15:13 ` Imre Deak
2021-10-18 15:27 ` Ville Syrjälä
2021-10-18 9:41 ` [Intel-gfx] [PATCH 5/6] drm/i915/dp: Sanitize sink rate DPCD register values Imre Deak
2021-10-18 9:41 ` [Intel-gfx] [PATCH 6/6] drm/i915/dp: Sanitize link common rate array lookups Imre Deak
2021-10-19 19:23 ` Jani Nikula
2021-10-20 9:06 ` Imre Deak
2021-10-20 9:53 ` Jani Nikula
2021-10-20 10:09 ` Ville Syrjälä
2021-10-18 12:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Fix link parameter use in lack of a valid DPCD Patchwork
2021-10-18 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-18 13:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-10-18 18:01 ` Patchwork [this message]
2021-10-18 18:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dp: Fix link parameter use in lack of a valid DPCD (rev2) Patchwork
2021-10-18 18:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-19 0:52 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-19 12:54 ` Imre Deak
2021-10-19 15:33 ` Vudum, Lakshminarayana
2021-10-19 16:32 ` Imre Deak
2021-10-19 14:45 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2021-10-20 15:40 ` Imre Deak
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