* [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
@ 2021-10-27 9:53 Vandita Kulkarni
2021-10-27 14:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Vandita Kulkarni @ 2021-10-27 9:53 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, manasi.d.navare, Vandita Kulkarni
DP 1.4 spec limits max compression bpp to
uncompressed bpp -1, which is supported from
XELPD onwards.
Instead of uncompressed bpp, max dsc input bpp
was being used to limit the max compression bpp.
Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression BPPs")
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9d8132dd4cc5..1f7e666ae490 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1322,7 +1322,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
- int pipe_bpp;
+ int pipe_bpp, max_dsc_pipe_bpp;
int ret;
pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
@@ -1331,7 +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
- pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
+ pipe_bpp = pipe_config->pipe_bpp;
+ max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
/* Min Input BPC for ICL+ is 8 */
if (pipe_bpp < 8 * 3) {
@@ -1345,7 +1346,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* Optimize this later for the minimum possible link rate/lane count
* with DSC enabled for the requested mode.
*/
- pipe_config->pipe_bpp = pipe_bpp;
+ pipe_config->pipe_bpp = max_dsc_pipe_bpp;
pipe_config->port_clock = limits->max_rate;
pipe_config->lane_count = limits->max_lane_count;
--
2.32.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-27 9:53 [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp Vandita Kulkarni
@ 2021-10-27 14:37 ` Patchwork
2021-10-27 18:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-27 19:26 ` [Intel-gfx] [PATCH] " Navare, Manasi
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-10-27 14:37 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1503 bytes --]
== Series Details ==
Series: drm/i915/dsc: Fix the usage of uncompressed bpp
URL : https://patchwork.freedesktop.org/series/96337/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10796 -> Patchwork_21459
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/index.html
Participating hosts (39 -> 34)
------------------------------
Missing (5): bat-dg1-6 bat-dg1-5 fi-bsw-cyan bat-adlp-4 fi-pnv-d510
Known issues
------------
Here are the changes found in Patchwork_21459 that come from known issues:
### IGT changes ###
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
Build changes
-------------
* Linux: CI_DRM_10796 -> Patchwork_21459
CI-20190529: 20190529
CI_DRM_10796: c2698ab428a9398c02ef1ee3a03f51608cf97a86 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6262: d1c793b26e31cc6ae3f9fa3239805a9bbcc749fb @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21459: 1ac112762b3a9fecce295348f3c37ce1bc6ea36a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
1ac112762b3a drm/i915/dsc: Fix the usage of uncompressed bpp
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/index.html
[-- Attachment #2: Type: text/html, Size: 2012 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-27 9:53 [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp Vandita Kulkarni
2021-10-27 14:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
@ 2021-10-27 18:02 ` Patchwork
2021-10-27 19:26 ` [Intel-gfx] [PATCH] " Navare, Manasi
2 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2021-10-27 18:02 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30270 bytes --]
== Series Details ==
Series: drm/i915/dsc: Fix the usage of uncompressed bpp
URL : https://patchwork.freedesktop.org/series/96337/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10796_full -> Patchwork_21459_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21459_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21459_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21459_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
- shard-kbl: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl3/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl1/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
#### Warnings ####
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-glk: [FAIL][3] ([i915#1888]) -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
Known issues
------------
Here are the changes found in Patchwork_21459_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@many-contexts:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#2410])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb7/igt@gem_ctx_persistence@many-contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][7] -> [FAIL][8] ([i915#2842])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk7/igt@gem_exec_fair@basic-none@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk7/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][14] -> [SKIP][15] ([fdo#109271])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-tglb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@gem_huc_copy@huc-copy.html
* igt@gem_pxp@verify-pxp-stale-ctx-execution:
- shard-tglb: NOTRUN -> [SKIP][18] ([i915#4270]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@gem_pxp@verify-pxp-stale-ctx-execution.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#1373] / [i915#456])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb8/igt@gem_softpin@noreloc-s3.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb7/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rpm@gem-execbuf-stress-pc8:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109506] / [i915#2411])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
* igt@i915_query@query-topology-known-pci-ids:
- shard-tglb: NOTRUN -> [SKIP][22] ([fdo#109303])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@i915_query@query-topology-known-pci-ids.html
* igt@i915_query@query-topology-unsupported:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109302])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@i915_query@query-topology-unsupported.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl1/igt@i915_suspend@sysfs-reader.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@i915_suspend@sysfs-reader.html
* igt@kms_async_flips@async-flip-with-page-flip-events:
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#4323])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl6/igt@kms_async_flips@async-flip-with-page-flip-events.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl2/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111614]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][29] ([i915#3743])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111615]) +4 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271]) +67 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#3886]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs:
- shard-snb: NOTRUN -> [SKIP][34] ([fdo#109271]) +39 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-snb7/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_ccs.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +3 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl7/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][38] ([i915#3689] / [i915#3886]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#3689]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_chamelium@dp-crc-multiple:
- shard-apl: NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +4 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_chamelium@dp-crc-multiple.html
- shard-tglb: NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +4 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_chamelium@dp-crc-multiple.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +6 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl7/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +2 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-snb7/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][47] ([i915#1319])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@kms_content_protection@lic.html
* igt@kms_content_protection@type1:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111828])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3319])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-random:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_cursor_crc@pipe-b-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][51] ([i915#180])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3359]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-max-size-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-tglb: [PASS][53] -> [INCOMPLETE][54] ([i915#456])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-glk: NOTRUN -> [SKIP][55] ([fdo#109271]) +31 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-tglb: NOTRUN -> [SKIP][56] ([i915#4103]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl7/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled:
- shard-glk: [PASS][58] -> [DMESG-WARN][59] ([i915#118]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk1/igt@kms_draw_crc@draw-method-rgb565-pwrite-xtiled.html
* igt@kms_dsc@basic-dsc-enable@edp-1-pipe-a:
- shard-tglb: [PASS][60] -> [FAIL][61] ([i915#1385]) +3 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb2/igt@kms_dsc@basic-dsc-enable@edp-1-pipe-a.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb7/igt@kms_dsc@basic-dsc-enable@edp-1-pipe-a.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][62] -> [INCOMPLETE][63] ([i915#2411] / [i915#456])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb2/igt@kms_fbcon_fbt@fbc-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109274])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1:
- shard-apl: [PASS][65] -> [FAIL][66] ([i915#79])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [PASS][67] -> [DMESG-WARN][68] ([i915#180])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-apl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-edp1:
- shard-skl: [PASS][69] -> [INCOMPLETE][70] ([i915#198])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl2/igt@kms_flip@flip-vs-suspend@c-edp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl10/igt@kms_flip@flip-vs-suspend@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271]) +51 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move:
- shard-tglb: NOTRUN -> [SKIP][73] ([fdo#111825]) +11 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271]) +105 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-tglb: [PASS][75] -> [INCOMPLETE][76] ([i915#4184] / [i915#456])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][79] ([i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
- shard-skl: NOTRUN -> [FAIL][80] ([i915#265])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][81] -> [FAIL][82] ([fdo#108145] / [i915#265])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-tglb: NOTRUN -> [SKIP][84] ([i915#3536])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_plane_lowres@pipe-c-tiling-yf:
- shard-iclb: NOTRUN -> [SKIP][85] ([i915#3536])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_plane_lowres@pipe-c-tiling-yf.html
* igt@kms_plane_lowres@pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][86] ([fdo#112054]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_plane_lowres@pipe-d-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
- shard-tglb: NOTRUN -> [SKIP][88] ([i915#2920])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#658])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][92] ([i915#132] / [i915#3467]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [PASS][93] -> [SKIP][94] ([fdo#109441])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb3/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr@psr2_primary_render:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109441])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_psr@psr2_primary_render.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-d:
- shard-iclb: NOTRUN -> [SKIP][96] ([fdo#109278])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@kms_universal_plane@universal-plane-gen9-features-pipe-d.html
* igt@kms_writeback@writeback-fb-id:
- shard-glk: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2437])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-b-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#2530])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
* igt@prime_nv_test@i915_import_gtt_mmap:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109291])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb6/igt@prime_nv_test@i915_import_gtt_mmap.html
* igt@sysfs_clients@fair-0:
- shard-glk: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2994])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk6/igt@sysfs_clients@fair-0.html
* igt@sysfs_clients@pidname:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#2994])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@sysfs_clients@pidname.html
* igt@sysfs_clients@recycle:
- shard-kbl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2994])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl7/igt@sysfs_clients@recycle.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [PASS][103] -> [FAIL][104] ([i915#1731]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl6/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl2/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-kbl: [DMESG-WARN][105] ([i915#180]) -> [PASS][106] +6 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_shared@q-smoketest-all:
- shard-glk: [DMESG-WARN][107] ([i915#118]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk6/igt@gem_ctx_shared@q-smoketest-all.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk1/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-glk: [FAIL][109] ([i915#2842]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk1/igt@gem_exec_fair@basic-none-vip@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][111] ([i915#2842]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-iclb: [FAIL][113] ([i915#2842]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-iclb6/igt@gem_exec_fair@basic-pace@vecs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb4/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [INCOMPLETE][115] ([i915#3921]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-snb6/igt@i915_selftest@live@hangcheck.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@debugfs-reader:
- shard-tglb: [INCOMPLETE][117] ([i915#456]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb7/igt@i915_suspend@debugfs-reader.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb3/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][119] ([i915#72]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][121] ([i915#2346]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-iclb4/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][123] ([i915#79]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@modeset-vs-vblank-race-interruptible@b-edp1:
- shard-tglb: [INCOMPLETE][125] -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-tglb8/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-edp1.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-tglb2/igt@kms_flip@modeset-vs-vblank-race-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-edp1:
- shard-skl: [FAIL][127] ([i915#2122]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl9/igt@kms_flip@plain-flip-fb-recreate@a-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][129] ([i915#1188]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][131] ([i915#180]) -> [PASS][132] +2 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][133] ([fdo#108145] / [i915#265]) -> [PASS][134] +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][135] ([fdo#109441]) -> [PASS][136] +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10796/shard-iclb4/igt@kms_ps
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21459/index.html
[-- Attachment #2: Type: text/html, Size: 33564 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-27 9:53 [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp Vandita Kulkarni
2021-10-27 14:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-27 18:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-10-27 19:26 ` Navare, Manasi
2021-10-28 4:37 ` Kulkarni, Vandita
2 siblings, 1 reply; 10+ messages in thread
From: Navare, Manasi @ 2021-10-27 19:26 UTC (permalink / raw)
To: Vandita Kulkarni; +Cc: intel-gfx, jani.nikula
On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> DP 1.4 spec limits max compression bpp to
> uncompressed bpp -1, which is supported from
> XELPD onwards.
> Instead of uncompressed bpp, max dsc input bpp
> was being used to limit the max compression bpp.
So the input Pipe BPP which is the uncompressed bpp is decided by the input bpc
and when this was initially written, we had designed it to respect the max_req_bpc by the user.
So that is what we use to decide the input bpc and hence the pipe_bpp
This input pipe_bpp decides the compressed bpp that we calculate based on all the supported output bpps
which are supported all the way upto uncompressed_output_bpp - 1.
So I dont see the need to change the logic here. Moreover I dont see any change in the dsc_compute_bpp function
So I dont understand the purpose of introducing the new max_dsc_pipe_bpp variable here
Manasi
>
> Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression BPPs")
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9d8132dd4cc5..1f7e666ae490 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1322,7 +1322,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
> const struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> - int pipe_bpp;
> + int pipe_bpp, max_dsc_pipe_bpp;
> int ret;
>
> pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> @@ -1331,7 +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> return -EINVAL;
>
> - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
> + pipe_bpp = pipe_config->pipe_bpp;
> + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc);
>
> /* Min Input BPC for ICL+ is 8 */
> if (pipe_bpp < 8 * 3) {
> @@ -1345,7 +1346,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> * Optimize this later for the minimum possible link rate/lane count
> * with DSC enabled for the requested mode.
> */
> - pipe_config->pipe_bpp = pipe_bpp;
> + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> pipe_config->port_clock = limits->max_rate;
> pipe_config->lane_count = limits->max_lane_count;
>
> --
> 2.32.0
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-27 19:26 ` [Intel-gfx] [PATCH] " Navare, Manasi
@ 2021-10-28 4:37 ` Kulkarni, Vandita
2021-10-29 23:12 ` Navare, Manasi
0 siblings, 1 reply; 10+ messages in thread
From: Kulkarni, Vandita @ 2021-10-28 4:37 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: intel-gfx, Nikula, Jani
> -----Original Message-----
> From: Navare, Manasi D <manasi.d.navare@intel.com>
> Sent: Thursday, October 28, 2021 12:57 AM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
>
> On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > DP 1.4 spec limits max compression bpp to uncompressed bpp -1, which
> > is supported from XELPD onwards.
> > Instead of uncompressed bpp, max dsc input bpp was being used to limit
> > the max compression bpp.
>
> So the input Pipe BPP which is the uncompressed bpp is decided by the input
> bpc and when this was initially written, we had designed it to respect the
> max_req_bpc by the user.
> So that is what we use to decide the input bpc and hence the pipe_bpp This
> input pipe_bpp decides the compressed bpp that we calculate based on all
> the supported output bpps which are supported all the way upto
> uncompressed_output_bpp - 1.
>
> So I dont see the need to change the logic here. Moreover I dont see any
> change in the dsc_compute_bpp function So I dont understand the purpose
> of introducing the new max_dsc_pipe_bpp variable here
Thanks for the comments, I had few more opens around this along with this patch.
AFAIU about max_requested_bpc it is to limit the max_bpc
"drm: Add connector property to limit max bpc"
And the driver is supposed to program the default bpc as per the connector limitation.
Which is 12 as per the current driver implementation.
I had few queries around this design:
So it means that max_dsc_input_bpp would be set to 36 if supported by the sink and the platform.
And now we make this as our pipe_bpp,
1. Does this mean that we are assuming 12bpc as i/p always?
2. What happens to those with formats 8bpc, 10 bpc?
We do not consider the actual pipe_bpp while computing the compression_bpp,
We reverse calculate it from the link_rate, and small joiner bpp limits.
In cases of forcing dsc, we might have a situation where the link can actually support the current bpp, or even more.
But we are forcing the dsc enable.
In such cases we might end up with a compression bpp which is higher than the actual i/p bpp.
Now, even if we take a min of higher compression bpp against max_requested_bpc *3 -1, we still have
Compression bpp > actual pipe_bpp
As per the spec when they say uncompressed bpp, they actually mean 3 * bpc
If we go ahead with this approach of using max_requested_bpc , which is 12 always we cannot
adhere to the spec.
Thanks,
Vandita
> Manasi
>
> >
> > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression BPPs")
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 9d8132dd4cc5..1f7e666ae490 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1322,7 +1322,7 @@ static int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> > struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> > const struct drm_display_mode *adjusted_mode =
> > &pipe_config->hw.adjusted_mode;
> > - int pipe_bpp;
> > + int pipe_bpp, max_dsc_pipe_bpp;
> > int ret;
> >
> > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -
> 1331,7
> > +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > return -EINVAL;
> >
> > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> >max_requested_bpc);
> > + pipe_bpp = pipe_config->pipe_bpp;
> > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > +conn_state->max_requested_bpc);
> >
> > /* Min Input BPC for ICL+ is 8 */
> > if (pipe_bpp < 8 * 3) {
> > @@ -1345,7 +1346,7 @@ static int intel_dp_dsc_compute_config(struct
> intel_dp *intel_dp,
> > * Optimize this later for the minimum possible link rate/lane count
> > * with DSC enabled for the requested mode.
> > */
> > - pipe_config->pipe_bpp = pipe_bpp;
> > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > pipe_config->port_clock = limits->max_rate;
> > pipe_config->lane_count = limits->max_lane_count;
> >
> > --
> > 2.32.0
> >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-28 4:37 ` Kulkarni, Vandita
@ 2021-10-29 23:12 ` Navare, Manasi
2021-11-01 16:45 ` Kulkarni, Vandita
0 siblings, 1 reply; 10+ messages in thread
From: Navare, Manasi @ 2021-10-29 23:12 UTC (permalink / raw)
To: Kulkarni, Vandita; +Cc: intel-gfx, Nikula, Jani
On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote:
> > -----Original Message-----
> > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > Sent: Thursday, October 28, 2021 12:57 AM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> >
> > On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > > DP 1.4 spec limits max compression bpp to uncompressed bpp -1, which
> > > is supported from XELPD onwards.
> > > Instead of uncompressed bpp, max dsc input bpp was being used to limit
> > > the max compression bpp.
> >
> > So the input Pipe BPP which is the uncompressed bpp is decided by the input
> > bpc and when this was initially written, we had designed it to respect the
> > max_req_bpc by the user.
> > So that is what we use to decide the input bpc and hence the pipe_bpp This
> > input pipe_bpp decides the compressed bpp that we calculate based on all
> > the supported output bpps which are supported all the way upto
> > uncompressed_output_bpp - 1.
> >
> > So I dont see the need to change the logic here. Moreover I dont see any
> > change in the dsc_compute_bpp function So I dont understand the purpose
> > of introducing the new max_dsc_pipe_bpp variable here
>
> Thanks for the comments, I had few more opens around this along with this patch.
>
> AFAIU about max_requested_bpc it is to limit the max_bpc
> "drm: Add connector property to limit max bpc"
> And the driver is supposed to program the default bpc as per the connector limitation.
> Which is 12 as per the current driver implementation.
>
> I had few queries around this design:
> So it means that max_dsc_input_bpp would be set to 36 if supported by the sink and the platform.
> And now we make this as our pipe_bpp,
> 1. Does this mean that we are assuming 12bpc as i/p always?
> 2. What happens to those with formats 8bpc, 10 bpc?
>
Yes so this driver policy was decided based on some feedback that I had got from the community as well as internal feedback from Ville
that the decision of input_bpc should be based on max_bpc requested by the user through the connector property and max_bpc supported by the platform.
Here we take the min of the two so that we dont violate either of the max constrains.
This was primarily suggested by Ville since he said that we should always respect what user has set as the upper limit in the bpc because
this could be for example driven by the fact that OEM's panel has a limitation or issues with higher bpcs or a display requirement for certain use case.
Hence while we want to support as high bpc as supported by the platform and sink to have better display quality, it should not exceed the max limit
set by the user through the property.
8 and 10bpc will be supported but we want to start with supporting the max we can, going down from there if needed.
So for compression, we chose the maximum input bpc and determine the compressed bpp for that.
> We do not consider the actual pipe_bpp while computing the compression_bpp,
> We reverse calculate it from the link_rate, and small joiner bpp limits.
> In cases of forcing dsc, we might have a situation where the link can actually support the current bpp, or even more.
> But we are forcing the dsc enable.
> In such cases we might end up with a compression bpp which is higher than the actual i/p bpp.
Well the only time we force the dsc_enable is for IGT DSC tests and thats okay for compression bpp to be higher
since there we are just validation the functionality and its not for actual user/use case.
In the actual use case we will only enable DSC when the available max link rate/lane count does not support the
minimum bpp of 18 (min bpc of 6 * 3)
So then in that case we say that lets keep the pipe_bpp or input bpp as max_supported_input_bpc * 3
>
> Now, even if we take a min of higher compression bpp against max_requested_bpc *3 -1, we still have
> Compression bpp > actual pipe_bpp
>
> As per the spec when they say uncompressed bpp, they actually mean 3 * bpc
> If we go ahead with this approach of using max_requested_bpc , which is 12 always we cannot
> adhere to the spec.
So the Bspec says that if the input BPP is (8 * 3) = 24, then based on the engine's compression ratio capability it can support output compressed BPP of: 8 - 23 in the increments of 1 BPP
And the maximum that we can pick between 8 - 23 will depend on the min(max bits_per_pixel that the max link rate, lane count can handle, max bits per pixel by small joiner RAM calc).
So we are good here in terms of how we calculate our compressed bpp. However what you should once double check is for XeLPD (>=13) platforms, you just pick min (bits_per_pixel, pipe_bpp - 1)
But I remember seeing that the spec still says target bpp has to be 8 to 27 even when supported input bpc are 8/10/12 (please check if it actually goes all the way from 8 to 35)
Manasi
>
> Thanks,
> Vandita
>
> > Manasi
> >
> > >
> > > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression BPPs")
> > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 9d8132dd4cc5..1f7e666ae490 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1322,7 +1322,7 @@ static int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > >base.base.dev);
> > > const struct drm_display_mode *adjusted_mode =
> > > &pipe_config->hw.adjusted_mode;
> > > - int pipe_bpp;
> > > + int pipe_bpp, max_dsc_pipe_bpp;
> > > int ret;
> > >
> > > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -
> > 1331,7
> > > +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> > *intel_dp,
> > > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > > return -EINVAL;
> > >
> > > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> > >max_requested_bpc);
> > > + pipe_bpp = pipe_config->pipe_bpp;
> > > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > > +conn_state->max_requested_bpc);
> > >
> > > /* Min Input BPC for ICL+ is 8 */
> > > if (pipe_bpp < 8 * 3) {
> > > @@ -1345,7 +1346,7 @@ static int intel_dp_dsc_compute_config(struct
> > intel_dp *intel_dp,
> > > * Optimize this later for the minimum possible link rate/lane count
> > > * with DSC enabled for the requested mode.
> > > */
> > > - pipe_config->pipe_bpp = pipe_bpp;
> > > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > > pipe_config->port_clock = limits->max_rate;
> > > pipe_config->lane_count = limits->max_lane_count;
> > >
> > > --
> > > 2.32.0
> > >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-10-29 23:12 ` Navare, Manasi
@ 2021-11-01 16:45 ` Kulkarni, Vandita
2021-11-02 4:40 ` Navare, Manasi
0 siblings, 1 reply; 10+ messages in thread
From: Kulkarni, Vandita @ 2021-11-01 16:45 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Navare, Manasi D <manasi.d.navare@intel.com>
> Sent: Saturday, October 30, 2021 4:43 AM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
>
> On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote:
> > > -----Original Message-----
> > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > Sent: Thursday, October 28, 2021 12:57 AM
> > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > <jani.nikula@intel.com>
> > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> > >
> > > On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > > > DP 1.4 spec limits max compression bpp to uncompressed bpp -1,
> > > > which is supported from XELPD onwards.
> > > > Instead of uncompressed bpp, max dsc input bpp was being used to
> > > > limit the max compression bpp.
> > >
> > > So the input Pipe BPP which is the uncompressed bpp is decided by
> > > the input bpc and when this was initially written, we had designed
> > > it to respect the max_req_bpc by the user.
> > > So that is what we use to decide the input bpc and hence the
> > > pipe_bpp This input pipe_bpp decides the compressed bpp that we
> > > calculate based on all the supported output bpps which are supported
> > > all the way upto uncompressed_output_bpp - 1.
> > >
> > > So I dont see the need to change the logic here. Moreover I dont see
> > > any change in the dsc_compute_bpp function So I dont understand the
> > > purpose of introducing the new max_dsc_pipe_bpp variable here
> >
> > Thanks for the comments, I had few more opens around this along with
> this patch.
> >
> > AFAIU about max_requested_bpc it is to limit the max_bpc
> > "drm: Add connector property to limit max bpc"
> > And the driver is supposed to program the default bpc as per the connector
> limitation.
> > Which is 12 as per the current driver implementation.
> >
> > I had few queries around this design:
> > So it means that max_dsc_input_bpp would be set to 36 if supported by the
> sink and the platform.
> > And now we make this as our pipe_bpp,
> > 1. Does this mean that we are assuming 12bpc as i/p always?
> > 2. What happens to those with formats 8bpc, 10 bpc?
> >
>
> Yes so this driver policy was decided based on some feedback that I had got
> from the community as well as internal feedback from Ville that the decision
> of input_bpc should be based on max_bpc requested by the user through the
> connector property and max_bpc supported by the platform.
> Here we take the min of the two so that we dont violate either of the max
> constrains.
> This was primarily suggested by Ville since he said that we should always
> respect what user has set as the upper limit in the bpc because this could be
> for example driven by the fact that OEM's panel has a limitation or issues
> with higher bpcs or a display requirement for certain use case.
> Hence while we want to support as high bpc as supported by the platform
> and sink to have better display quality, it should not exceed the max limit set
> by the user through the property.
>
> 8 and 10bpc will be supported but we want to start with supporting the max
> we can, going down from there if needed.
> So for compression, we chose the maximum input bpc and determine the
> compressed bpp for that.
>
>
> > We do not consider the actual pipe_bpp while computing the
> > compression_bpp, We reverse calculate it from the link_rate, and small
> joiner bpp limits.
> > In cases of forcing dsc, we might have a situation where the link can
> actually support the current bpp, or even more.
> > But we are forcing the dsc enable.
> > In such cases we might end up with a compression bpp which is higher than
> the actual i/p bpp.
>
> Well the only time we force the dsc_enable is for IGT DSC tests and thats
> okay for compression bpp to be higher since there we are just validation the
> functionality and its not for actual user/use case.
We are having these test cases as part of CI. We hit FIFO underrun in such cases and that's treated as a fail.
>
> In the actual use case we will only enable DSC when the available max link
> rate/lane count does not support the minimum bpp of 18 (min bpc of 6 * 3)
> So then in that case we say that lets keep the pipe_bpp or input bpp as
> max_supported_input_bpc * 3
> >
> > Now, even if we take a min of higher compression bpp against
> > max_requested_bpc *3 -1, we still have Compression bpp > actual
> > pipe_bpp
> >
> > As per the spec when they say uncompressed bpp, they actually mean 3 *
> > bpc If we go ahead with this approach of using max_requested_bpc ,
> > which is 12 always we cannot adhere to the spec.
>
> So the Bspec says that if the input BPP is (8 * 3) = 24, then based on the
> engine's compression ratio capability it can support output compressed BPP
> of: 8 - 23 in the increments of 1 BPP And the maximum that we can pick
> between 8 - 23 will depend on the min(max bits_per_pixel that the max link
> rate, lane count can handle, max bits per pixel by small joiner RAM calc).
In case of force dsc, as part of the IGT tests, the link can actually support more than
24bpp, since we are forcing have seen a case where it could support 28bpp.
So min of (28,(36-1)) would be 28 and not as per the spec.
Hence in either of the places, kernel or igt we need to honour the limits
Of bpc*3 as per the DP 1.4 spec.
If you look at the IGT we have cases of 8bpc, 10 bpc
We need to address this either in the driver by getting the actual uncompressed bpp limits
Or in the user space by changing the max_requested_bpc for 8bpc and 10bpc cases.
This patch is tested and resolves the FIFO underruns, in force dsc cases.
The problem is only when we are forcing DSC and the link rate can actually support higher bpp.
And we have multiple igts trying to use 8bpc and 10bpc.
Thanks
Vandita
>
> So we are good here in terms of how we calculate our compressed bpp.
> However what you should once double check is for XeLPD (>=13) platforms,
> you just pick min (bits_per_pixel, pipe_bpp - 1) But I remember seeing that
> the spec still says target bpp has to be 8 to 27 even when supported input bpc
> are 8/10/12 (please check if it actually goes all the way from 8 to 35)
>
> Manasi
>
> >
> > Thanks,
> > Vandita
> >
> > > Manasi
> > >
> > > >
> > > > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression
> > > > BPPs")
> > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 9d8132dd4cc5..1f7e666ae490 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1322,7 +1322,7 @@ static int
> > > > intel_dp_dsc_compute_config(struct
> > > intel_dp *intel_dp,
> > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > >base.base.dev);
> > > > const struct drm_display_mode *adjusted_mode =
> > > > &pipe_config->hw.adjusted_mode;
> > > > - int pipe_bpp;
> > > > + int pipe_bpp, max_dsc_pipe_bpp;
> > > > int ret;
> > > >
> > > > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -
> > > 1331,7
> > > > +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> > > *intel_dp,
> > > > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > > > return -EINVAL;
> > > >
> > > > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> > > >max_requested_bpc);
> > > > + pipe_bpp = pipe_config->pipe_bpp;
> > > > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > > > +conn_state->max_requested_bpc);
> > > >
> > > > /* Min Input BPC for ICL+ is 8 */
> > > > if (pipe_bpp < 8 * 3) {
> > > > @@ -1345,7 +1346,7 @@ static int
> > > > intel_dp_dsc_compute_config(struct
> > > intel_dp *intel_dp,
> > > > * Optimize this later for the minimum possible link rate/lane count
> > > > * with DSC enabled for the requested mode.
> > > > */
> > > > - pipe_config->pipe_bpp = pipe_bpp;
> > > > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > > > pipe_config->port_clock = limits->max_rate;
> > > > pipe_config->lane_count = limits->max_lane_count;
> > > >
> > > > --
> > > > 2.32.0
> > > >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-11-02 4:40 ` Navare, Manasi
@ 2021-11-02 4:35 ` Kulkarni, Vandita
2021-11-02 15:09 ` Navare, Manasi
0 siblings, 1 reply; 10+ messages in thread
From: Kulkarni, Vandita @ 2021-11-02 4:35 UTC (permalink / raw)
To: Navare, Manasi D; +Cc: Nikula, Jani, intel-gfx
> -----Original Message-----
> From: Navare, Manasi D <manasi.d.navare@intel.com>
> Sent: Tuesday, November 2, 2021 10:11 AM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
>
> On Mon, Nov 01, 2021 at 09:45:23AM -0700, Kulkarni, Vandita wrote:
> > > -----Original Message-----
> > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > Sent: Saturday, October 30, 2021 4:43 AM
> > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > <jani.nikula@intel.com>
> > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> > >
> > > On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote:
> > > > > -----Original Message-----
> > > > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > > > Sent: Thursday, October 28, 2021 12:57 AM
> > > > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > > > <jani.nikula@intel.com>
> > > > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed
> > > > > bpp
> > > > >
> > > > > On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > > > > > DP 1.4 spec limits max compression bpp to uncompressed bpp -1,
> > > > > > which is supported from XELPD onwards.
> > > > > > Instead of uncompressed bpp, max dsc input bpp was being used
> > > > > > to limit the max compression bpp.
> > > > >
> > > > > So the input Pipe BPP which is the uncompressed bpp is decided
> > > > > by the input bpc and when this was initially written, we had
> > > > > designed it to respect the max_req_bpc by the user.
> > > > > So that is what we use to decide the input bpc and hence the
> > > > > pipe_bpp This input pipe_bpp decides the compressed bpp that we
> > > > > calculate based on all the supported output bpps which are
> > > > > supported all the way upto uncompressed_output_bpp - 1.
> > > > >
> > > > > So I dont see the need to change the logic here. Moreover I dont
> > > > > see any change in the dsc_compute_bpp function So I dont
> > > > > understand the purpose of introducing the new max_dsc_pipe_bpp
> > > > > variable here
> > > >
> > > > Thanks for the comments, I had few more opens around this along
> > > > with
> > > this patch.
> > > >
> > > > AFAIU about max_requested_bpc it is to limit the max_bpc
> > > > "drm: Add connector property to limit max bpc"
> > > > And the driver is supposed to program the default bpc as per the
> > > > connector
> > > limitation.
> > > > Which is 12 as per the current driver implementation.
> > > >
> > > > I had few queries around this design:
> > > > So it means that max_dsc_input_bpp would be set to 36 if supported
> > > > by the
> > > sink and the platform.
> > > > And now we make this as our pipe_bpp, 1. Does this mean that we
> > > > are assuming 12bpc as i/p always?
> > > > 2. What happens to those with formats 8bpc, 10 bpc?
> > > >
> > >
> > > Yes so this driver policy was decided based on some feedback that I
> > > had got from the community as well as internal feedback from Ville
> > > that the decision of input_bpc should be based on max_bpc requested
> > > by the user through the connector property and max_bpc supported by
> the platform.
> > > Here we take the min of the two so that we dont violate either of
> > > the max constrains.
> > > This was primarily suggested by Ville since he said that we should
> > > always respect what user has set as the upper limit in the bpc
> > > because this could be for example driven by the fact that OEM's
> > > panel has a limitation or issues with higher bpcs or a display requirement
> for certain use case.
> > > Hence while we want to support as high bpc as supported by the
> > > platform and sink to have better display quality, it should not
> > > exceed the max limit set by the user through the property.
> > >
> > > 8 and 10bpc will be supported but we want to start with supporting
> > > the max we can, going down from there if needed.
> > > So for compression, we chose the maximum input bpc and determine the
> > > compressed bpp for that.
> > >
> > >
> > > > We do not consider the actual pipe_bpp while computing the
> > > > compression_bpp, We reverse calculate it from the link_rate, and
> > > > small
> > > joiner bpp limits.
> > > > In cases of forcing dsc, we might have a situation where the link
> > > > can
> > > actually support the current bpp, or even more.
> > > > But we are forcing the dsc enable.
> > > > In such cases we might end up with a compression bpp which is
> > > > higher than
> > > the actual i/p bpp.
> > >
> > > Well the only time we force the dsc_enable is for IGT DSC tests and
> > > thats okay for compression bpp to be higher since there we are just
> > > validation the functionality and its not for actual user/use case.
> >
> > We are having these test cases as part of CI. We hit FIFO underrun in such
> cases and that's treated as a fail.
>
> >
> > >
> > > In the actual use case we will only enable DSC when the available
> > > max link rate/lane count does not support the minimum bpp of 18 (min
> > > bpc of 6 * 3) So then in that case we say that lets keep the
> > > pipe_bpp or input bpp as max_supported_input_bpc * 3
> > > >
> > > > Now, even if we take a min of higher compression bpp against
> > > > max_requested_bpc *3 -1, we still have Compression bpp > actual
> > > > pipe_bpp
> > > >
> > > > As per the spec when they say uncompressed bpp, they actually mean
> > > > 3 * bpc If we go ahead with this approach of using
> > > > max_requested_bpc , which is 12 always we cannot adhere to the spec.
> > >
> > > So the Bspec says that if the input BPP is (8 * 3) = 24, then based
> > > on the engine's compression ratio capability it can support output
> > > compressed BPP
> > > of: 8 - 23 in the increments of 1 BPP And the maximum that we can
> > > pick between 8 - 23 will depend on the min(max bits_per_pixel that
> > > the max link rate, lane count can handle, max bits per pixel by small joiner
> RAM calc).
> >
> > In case of force dsc, as part of the IGT tests, the link can actually
> > support more than 24bpp, since we are forcing have seen a case where it
> could support 28bpp.
> >
>
> From IGT we are forcing DSC for all supported input BPCs right, so for bpc =
> 8, so input bpp = 24. So IMO in the kernel code, when we calculate pipe_bpp
> when force_dsc is set in that case we should use the bpc requested from IGT
> as inpput bpc and not care for max_connector_bpc So then input bpp = 24
> and the limits of compressed bpp would be 8 - 23
Right, had thought of this
Adding a check on force_dsc_en before doing this
pipe_config->pipe_bpp = max_dsc_pipe_bpp;
but since you said that the design was to respect the max_requested_bpc from the user
should we use max_requested_bpc property in the igt to say that set the max to 8bpc
since this test simulates a situation of testing 8bpc panel?
Similarly for 10bpc?
Thanks
Vandita
>
> Ideally now the link rate and lane count should be lowered to use the least
> required to support that compressed bpp Then we wont see any underruns.
>
> Manasi
>
> > So min of (28,(36-1)) would be 28 and not as per the spec.
> >
> > Hence in either of the places, kernel or igt we need to honour the
> > limits Of bpc*3 as per the DP 1.4 spec.
> >
> > If you look at the IGT we have cases of 8bpc, 10 bpc We need to
> > address this either in the driver by getting the actual uncompressed
> > bpp limits Or in the user space by changing the max_requested_bpc for
> 8bpc and 10bpc cases.
> >
> > This patch is tested and resolves the FIFO underruns, in force dsc cases.
> > The problem is only when we are forcing DSC and the link rate can actually
> support higher bpp.
> > And we have multiple igts trying to use 8bpc and 10bpc.
> >
> > Thanks
> > Vandita
> >
> > >
> > > So we are good here in terms of how we calculate our compressed bpp.
> > > However what you should once double check is for XeLPD (>=13)
> > > platforms, you just pick min (bits_per_pixel, pipe_bpp - 1) But I
> > > remember seeing that the spec still says target bpp has to be 8 to
> > > 27 even when supported input bpc are 8/10/12 (please check if it
> > > actually goes all the way from 8 to 35)
> > >
> > > Manasi
> > >
> > > >
> > > > Thanks,
> > > > Vandita
> > > >
> > > > > Manasi
> > > > >
> > > > > >
> > > > > > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4
> > > > > > compression
> > > > > > BPPs")
> > > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > > > > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > index 9d8132dd4cc5..1f7e666ae490 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > @@ -1322,7 +1322,7 @@ static int
> > > > > > intel_dp_dsc_compute_config(struct
> > > > > intel_dp *intel_dp,
> > > > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > >base.base.dev);
> > > > > > const struct drm_display_mode *adjusted_mode =
> > > > > > &pipe_config->hw.adjusted_mode;
> > > > > > - int pipe_bpp;
> > > > > > + int pipe_bpp, max_dsc_pipe_bpp;
> > > > > > int ret;
> > > > > >
> > > > > > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> @@ -
> > > > > 1331,7
> > > > > > +1331,8 @@ static int intel_dp_dsc_compute_config(struct
> > > > > > +intel_dp
> > > > > *intel_dp,
> > > > > > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > > > > > return -EINVAL;
> > > > > >
> > > > > > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> > > > > >max_requested_bpc);
> > > > > > + pipe_bpp = pipe_config->pipe_bpp;
> > > > > > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > > > > > +conn_state->max_requested_bpc);
> > > > > >
> > > > > > /* Min Input BPC for ICL+ is 8 */
> > > > > > if (pipe_bpp < 8 * 3) {
> > > > > > @@ -1345,7 +1346,7 @@ static int
> > > > > > intel_dp_dsc_compute_config(struct
> > > > > intel_dp *intel_dp,
> > > > > > * Optimize this later for the minimum possible link rate/lane
> count
> > > > > > * with DSC enabled for the requested mode.
> > > > > > */
> > > > > > - pipe_config->pipe_bpp = pipe_bpp;
> > > > > > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > > > > > pipe_config->port_clock = limits->max_rate;
> > > > > > pipe_config->lane_count = limits->max_lane_count;
> > > > > >
> > > > > > --
> > > > > > 2.32.0
> > > > > >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-11-01 16:45 ` Kulkarni, Vandita
@ 2021-11-02 4:40 ` Navare, Manasi
2021-11-02 4:35 ` Kulkarni, Vandita
0 siblings, 1 reply; 10+ messages in thread
From: Navare, Manasi @ 2021-11-02 4:40 UTC (permalink / raw)
To: Kulkarni, Vandita; +Cc: Nikula, Jani, intel-gfx
On Mon, Nov 01, 2021 at 09:45:23AM -0700, Kulkarni, Vandita wrote:
> > -----Original Message-----
> > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > Sent: Saturday, October 30, 2021 4:43 AM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> >
> > On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote:
> > > > -----Original Message-----
> > > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > > Sent: Thursday, October 28, 2021 12:57 AM
> > > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > > <jani.nikula@intel.com>
> > > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> > > >
> > > > On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > > > > DP 1.4 spec limits max compression bpp to uncompressed bpp -1,
> > > > > which is supported from XELPD onwards.
> > > > > Instead of uncompressed bpp, max dsc input bpp was being used to
> > > > > limit the max compression bpp.
> > > >
> > > > So the input Pipe BPP which is the uncompressed bpp is decided by
> > > > the input bpc and when this was initially written, we had designed
> > > > it to respect the max_req_bpc by the user.
> > > > So that is what we use to decide the input bpc and hence the
> > > > pipe_bpp This input pipe_bpp decides the compressed bpp that we
> > > > calculate based on all the supported output bpps which are supported
> > > > all the way upto uncompressed_output_bpp - 1.
> > > >
> > > > So I dont see the need to change the logic here. Moreover I dont see
> > > > any change in the dsc_compute_bpp function So I dont understand the
> > > > purpose of introducing the new max_dsc_pipe_bpp variable here
> > >
> > > Thanks for the comments, I had few more opens around this along with
> > this patch.
> > >
> > > AFAIU about max_requested_bpc it is to limit the max_bpc
> > > "drm: Add connector property to limit max bpc"
> > > And the driver is supposed to program the default bpc as per the connector
> > limitation.
> > > Which is 12 as per the current driver implementation.
> > >
> > > I had few queries around this design:
> > > So it means that max_dsc_input_bpp would be set to 36 if supported by the
> > sink and the platform.
> > > And now we make this as our pipe_bpp,
> > > 1. Does this mean that we are assuming 12bpc as i/p always?
> > > 2. What happens to those with formats 8bpc, 10 bpc?
> > >
> >
> > Yes so this driver policy was decided based on some feedback that I had got
> > from the community as well as internal feedback from Ville that the decision
> > of input_bpc should be based on max_bpc requested by the user through the
> > connector property and max_bpc supported by the platform.
> > Here we take the min of the two so that we dont violate either of the max
> > constrains.
> > This was primarily suggested by Ville since he said that we should always
> > respect what user has set as the upper limit in the bpc because this could be
> > for example driven by the fact that OEM's panel has a limitation or issues
> > with higher bpcs or a display requirement for certain use case.
> > Hence while we want to support as high bpc as supported by the platform
> > and sink to have better display quality, it should not exceed the max limit set
> > by the user through the property.
> >
> > 8 and 10bpc will be supported but we want to start with supporting the max
> > we can, going down from there if needed.
> > So for compression, we chose the maximum input bpc and determine the
> > compressed bpp for that.
> >
> >
> > > We do not consider the actual pipe_bpp while computing the
> > > compression_bpp, We reverse calculate it from the link_rate, and small
> > joiner bpp limits.
> > > In cases of forcing dsc, we might have a situation where the link can
> > actually support the current bpp, or even more.
> > > But we are forcing the dsc enable.
> > > In such cases we might end up with a compression bpp which is higher than
> > the actual i/p bpp.
> >
> > Well the only time we force the dsc_enable is for IGT DSC tests and thats
> > okay for compression bpp to be higher since there we are just validation the
> > functionality and its not for actual user/use case.
>
> We are having these test cases as part of CI. We hit FIFO underrun in such cases and that's treated as a fail.
>
> >
> > In the actual use case we will only enable DSC when the available max link
> > rate/lane count does not support the minimum bpp of 18 (min bpc of 6 * 3)
> > So then in that case we say that lets keep the pipe_bpp or input bpp as
> > max_supported_input_bpc * 3
> > >
> > > Now, even if we take a min of higher compression bpp against
> > > max_requested_bpc *3 -1, we still have Compression bpp > actual
> > > pipe_bpp
> > >
> > > As per the spec when they say uncompressed bpp, they actually mean 3 *
> > > bpc If we go ahead with this approach of using max_requested_bpc ,
> > > which is 12 always we cannot adhere to the spec.
> >
> > So the Bspec says that if the input BPP is (8 * 3) = 24, then based on the
> > engine's compression ratio capability it can support output compressed BPP
> > of: 8 - 23 in the increments of 1 BPP And the maximum that we can pick
> > between 8 - 23 will depend on the min(max bits_per_pixel that the max link
> > rate, lane count can handle, max bits per pixel by small joiner RAM calc).
>
> In case of force dsc, as part of the IGT tests, the link can actually support more than
> 24bpp, since we are forcing have seen a case where it could support 28bpp.
>
From IGT we are forcing DSC for all supported input BPCs right, so for bpc = 8,
so input bpp = 24. So IMO in the kernel code, when we calculate pipe_bpp when force_dsc is set in that case we should use the bpc requested
from IGT as inpput bpc and not care for max_connector_bpc
So then input bpp = 24 and the limits of compressed bpp would be 8 - 23
Ideally now the link rate and lane count should be lowered to use the least required to support that compressed bpp
Then we wont see any underruns.
Manasi
> So min of (28,(36-1)) would be 28 and not as per the spec.
>
> Hence in either of the places, kernel or igt we need to honour the limits
> Of bpc*3 as per the DP 1.4 spec.
>
> If you look at the IGT we have cases of 8bpc, 10 bpc
> We need to address this either in the driver by getting the actual uncompressed bpp limits
> Or in the user space by changing the max_requested_bpc for 8bpc and 10bpc cases.
>
> This patch is tested and resolves the FIFO underruns, in force dsc cases.
> The problem is only when we are forcing DSC and the link rate can actually support higher bpp.
> And we have multiple igts trying to use 8bpc and 10bpc.
>
> Thanks
> Vandita
>
> >
> > So we are good here in terms of how we calculate our compressed bpp.
> > However what you should once double check is for XeLPD (>=13) platforms,
> > you just pick min (bits_per_pixel, pipe_bpp - 1) But I remember seeing that
> > the spec still says target bpp has to be 8 to 27 even when supported input bpc
> > are 8/10/12 (please check if it actually goes all the way from 8 to 35)
> >
> > Manasi
> >
> > >
> > > Thanks,
> > > Vandita
> > >
> > > > Manasi
> > > >
> > > > >
> > > > > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4 compression
> > > > > BPPs")
> > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > > > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index 9d8132dd4cc5..1f7e666ae490 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -1322,7 +1322,7 @@ static int
> > > > > intel_dp_dsc_compute_config(struct
> > > > intel_dp *intel_dp,
> > > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > >base.base.dev);
> > > > > const struct drm_display_mode *adjusted_mode =
> > > > > &pipe_config->hw.adjusted_mode;
> > > > > - int pipe_bpp;
> > > > > + int pipe_bpp, max_dsc_pipe_bpp;
> > > > > int ret;
> > > > >
> > > > > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && @@ -
> > > > 1331,7
> > > > > +1331,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> > > > *intel_dp,
> > > > > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > > > > return -EINVAL;
> > > > >
> > > > > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> > > > >max_requested_bpc);
> > > > > + pipe_bpp = pipe_config->pipe_bpp;
> > > > > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > > > > +conn_state->max_requested_bpc);
> > > > >
> > > > > /* Min Input BPC for ICL+ is 8 */
> > > > > if (pipe_bpp < 8 * 3) {
> > > > > @@ -1345,7 +1346,7 @@ static int
> > > > > intel_dp_dsc_compute_config(struct
> > > > intel_dp *intel_dp,
> > > > > * Optimize this later for the minimum possible link rate/lane count
> > > > > * with DSC enabled for the requested mode.
> > > > > */
> > > > > - pipe_config->pipe_bpp = pipe_bpp;
> > > > > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > > > > pipe_config->port_clock = limits->max_rate;
> > > > > pipe_config->lane_count = limits->max_lane_count;
> > > > >
> > > > > --
> > > > > 2.32.0
> > > > >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
2021-11-02 4:35 ` Kulkarni, Vandita
@ 2021-11-02 15:09 ` Navare, Manasi
0 siblings, 0 replies; 10+ messages in thread
From: Navare, Manasi @ 2021-11-02 15:09 UTC (permalink / raw)
To: Kulkarni, Vandita; +Cc: Nikula, Jani, intel-gfx
On Mon, Nov 01, 2021 at 09:35:32PM -0700, Kulkarni, Vandita wrote:
> > -----Original Message-----
> > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > Sent: Tuesday, November 2, 2021 10:11 AM
> > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> >
> > On Mon, Nov 01, 2021 at 09:45:23AM -0700, Kulkarni, Vandita wrote:
> > > > -----Original Message-----
> > > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > > Sent: Saturday, October 30, 2021 4:43 AM
> > > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > > <jani.nikula@intel.com>
> > > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp
> > > >
> > > > On Wed, Oct 27, 2021 at 09:37:10PM -0700, Kulkarni, Vandita wrote:
> > > > > > -----Original Message-----
> > > > > > From: Navare, Manasi D <manasi.d.navare@intel.com>
> > > > > > Sent: Thursday, October 28, 2021 12:57 AM
> > > > > > To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> > > > > > Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani
> > > > > > <jani.nikula@intel.com>
> > > > > > Subject: Re: [PATCH] drm/i915/dsc: Fix the usage of uncompressed
> > > > > > bpp
> > > > > >
> > > > > > On Wed, Oct 27, 2021 at 03:23:16PM +0530, Vandita Kulkarni wrote:
> > > > > > > DP 1.4 spec limits max compression bpp to uncompressed bpp -1,
> > > > > > > which is supported from XELPD onwards.
> > > > > > > Instead of uncompressed bpp, max dsc input bpp was being used
> > > > > > > to limit the max compression bpp.
> > > > > >
> > > > > > So the input Pipe BPP which is the uncompressed bpp is decided
> > > > > > by the input bpc and when this was initially written, we had
> > > > > > designed it to respect the max_req_bpc by the user.
> > > > > > So that is what we use to decide the input bpc and hence the
> > > > > > pipe_bpp This input pipe_bpp decides the compressed bpp that we
> > > > > > calculate based on all the supported output bpps which are
> > > > > > supported all the way upto uncompressed_output_bpp - 1.
> > > > > >
> > > > > > So I dont see the need to change the logic here. Moreover I dont
> > > > > > see any change in the dsc_compute_bpp function So I dont
> > > > > > understand the purpose of introducing the new max_dsc_pipe_bpp
> > > > > > variable here
> > > > >
> > > > > Thanks for the comments, I had few more opens around this along
> > > > > with
> > > > this patch.
> > > > >
> > > > > AFAIU about max_requested_bpc it is to limit the max_bpc
> > > > > "drm: Add connector property to limit max bpc"
> > > > > And the driver is supposed to program the default bpc as per the
> > > > > connector
> > > > limitation.
> > > > > Which is 12 as per the current driver implementation.
> > > > >
> > > > > I had few queries around this design:
> > > > > So it means that max_dsc_input_bpp would be set to 36 if supported
> > > > > by the
> > > > sink and the platform.
> > > > > And now we make this as our pipe_bpp, 1. Does this mean that we
> > > > > are assuming 12bpc as i/p always?
> > > > > 2. What happens to those with formats 8bpc, 10 bpc?
> > > > >
> > > >
> > > > Yes so this driver policy was decided based on some feedback that I
> > > > had got from the community as well as internal feedback from Ville
> > > > that the decision of input_bpc should be based on max_bpc requested
> > > > by the user through the connector property and max_bpc supported by
> > the platform.
> > > > Here we take the min of the two so that we dont violate either of
> > > > the max constrains.
> > > > This was primarily suggested by Ville since he said that we should
> > > > always respect what user has set as the upper limit in the bpc
> > > > because this could be for example driven by the fact that OEM's
> > > > panel has a limitation or issues with higher bpcs or a display requirement
> > for certain use case.
> > > > Hence while we want to support as high bpc as supported by the
> > > > platform and sink to have better display quality, it should not
> > > > exceed the max limit set by the user through the property.
> > > >
> > > > 8 and 10bpc will be supported but we want to start with supporting
> > > > the max we can, going down from there if needed.
> > > > So for compression, we chose the maximum input bpc and determine the
> > > > compressed bpp for that.
> > > >
> > > >
> > > > > We do not consider the actual pipe_bpp while computing the
> > > > > compression_bpp, We reverse calculate it from the link_rate, and
> > > > > small
> > > > joiner bpp limits.
> > > > > In cases of forcing dsc, we might have a situation where the link
> > > > > can
> > > > actually support the current bpp, or even more.
> > > > > But we are forcing the dsc enable.
> > > > > In such cases we might end up with a compression bpp which is
> > > > > higher than
> > > > the actual i/p bpp.
> > > >
> > > > Well the only time we force the dsc_enable is for IGT DSC tests and
> > > > thats okay for compression bpp to be higher since there we are just
> > > > validation the functionality and its not for actual user/use case.
> > >
> > > We are having these test cases as part of CI. We hit FIFO underrun in such
> > cases and that's treated as a fail.
> >
> > >
> > > >
> > > > In the actual use case we will only enable DSC when the available
> > > > max link rate/lane count does not support the minimum bpp of 18 (min
> > > > bpc of 6 * 3) So then in that case we say that lets keep the
> > > > pipe_bpp or input bpp as max_supported_input_bpc * 3
> > > > >
> > > > > Now, even if we take a min of higher compression bpp against
> > > > > max_requested_bpc *3 -1, we still have Compression bpp > actual
> > > > > pipe_bpp
> > > > >
> > > > > As per the spec when they say uncompressed bpp, they actually mean
> > > > > 3 * bpc If we go ahead with this approach of using
> > > > > max_requested_bpc , which is 12 always we cannot adhere to the spec.
> > > >
> > > > So the Bspec says that if the input BPP is (8 * 3) = 24, then based
> > > > on the engine's compression ratio capability it can support output
> > > > compressed BPP
> > > > of: 8 - 23 in the increments of 1 BPP And the maximum that we can
> > > > pick between 8 - 23 will depend on the min(max bits_per_pixel that
> > > > the max link rate, lane count can handle, max bits per pixel by small joiner
> > RAM calc).
> > >
> > > In case of force dsc, as part of the IGT tests, the link can actually
> > > support more than 24bpp, since we are forcing have seen a case where it
> > could support 28bpp.
> > >
> >
> > From IGT we are forcing DSC for all supported input BPCs right, so for bpc =
> > 8, so input bpp = 24. So IMO in the kernel code, when we calculate pipe_bpp
> > when force_dsc is set in that case we should use the bpc requested from IGT
> > as inpput bpc and not care for max_connector_bpc So then input bpp = 24
> > and the limits of compressed bpp would be 8 - 23
> Right, had thought of this
> Adding a check on force_dsc_en before doing this
> pipe_config->pipe_bpp = max_dsc_pipe_bpp;
>
> but since you said that the design was to respect the max_requested_bpc from the user
> should we use max_requested_bpc property in the igt to say that set the max to 8bpc
> since this test simulates a situation of testing 8bpc panel?
> Similarly for 10bpc?
>
> Thanks
> Vandita
Yes that would be a better way than adding a special force_dsc_en case
in the kernel.
We can set the max_requested_bpc to 8, 10, 12 then the pipe_bpp will get
set to 8/10/12 respectively as per the current logic and the compressed bpp
will get capped at pipe_bpp -1
So I think here since we would still use max link rate/ max lane count
we will still have much higher available link BW but we will just be
validating the functionality of 24 bpp to 23 bpp compression.
This sounds like a good approach.
Manasi
>
> >
> > Ideally now the link rate and lane count should be lowered to use the least
> > required to support that compressed bpp Then we wont see any underruns.
> >
> > Manasi
> >
> > > So min of (28,(36-1)) would be 28 and not as per the spec.
> > >
> > > Hence in either of the places, kernel or igt we need to honour the
> > > limits Of bpc*3 as per the DP 1.4 spec.
> > >
> > > If you look at the IGT we have cases of 8bpc, 10 bpc We need to
> > > address this either in the driver by getting the actual uncompressed
> > > bpp limits Or in the user space by changing the max_requested_bpc for
> > 8bpc and 10bpc cases.
> > >
> > > This patch is tested and resolves the FIFO underruns, in force dsc cases.
> > > The problem is only when we are forcing DSC and the link rate can actually
> > support higher bpp.
> > > And we have multiple igts trying to use 8bpc and 10bpc.
> > >
> > > Thanks
> > > Vandita
> > >
> > > >
> > > > So we are good here in terms of how we calculate our compressed bpp.
> > > > However what you should once double check is for XeLPD (>=13)
> > > > platforms, you just pick min (bits_per_pixel, pipe_bpp - 1) But I
> > > > remember seeing that the spec still says target bpp has to be 8 to
> > > > 27 even when supported input bpc are 8/10/12 (please check if it
> > > > actually goes all the way from 8 to 35)
> > > >
> > > > Manasi
> > > >
> > > > >
> > > > > Thanks,
> > > > > Vandita
> > > > >
> > > > > > Manasi
> > > > > >
> > > > > > >
> > > > > > > Fixes: 831d5aa96c97 ("drm/i915/xelpd: Support DP1.4
> > > > > > > compression
> > > > > > > BPPs")
> > > > > > > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++---
> > > > > > > 1 file changed, 4 insertions(+), 3 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > index 9d8132dd4cc5..1f7e666ae490 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > @@ -1322,7 +1322,7 @@ static int
> > > > > > > intel_dp_dsc_compute_config(struct
> > > > > > intel_dp *intel_dp,
> > > > > > > struct drm_i915_private *dev_priv = to_i915(dig_port-
> > > > > > >base.base.dev);
> > > > > > > const struct drm_display_mode *adjusted_mode =
> > > > > > > &pipe_config->hw.adjusted_mode;
> > > > > > > - int pipe_bpp;
> > > > > > > + int pipe_bpp, max_dsc_pipe_bpp;
> > > > > > > int ret;
> > > > > > >
> > > > > > > pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
> > @@ -
> > > > > > 1331,7
> > > > > > > +1331,8 @@ static int intel_dp_dsc_compute_config(struct
> > > > > > > +intel_dp
> > > > > > *intel_dp,
> > > > > > > if (!intel_dp_supports_dsc(intel_dp, pipe_config))
> > > > > > > return -EINVAL;
> > > > > > >
> > > > > > > - pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state-
> > > > > > >max_requested_bpc);
> > > > > > > + pipe_bpp = pipe_config->pipe_bpp;
> > > > > > > + max_dsc_pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp,
> > > > > > > +conn_state->max_requested_bpc);
> > > > > > >
> > > > > > > /* Min Input BPC for ICL+ is 8 */
> > > > > > > if (pipe_bpp < 8 * 3) {
> > > > > > > @@ -1345,7 +1346,7 @@ static int
> > > > > > > intel_dp_dsc_compute_config(struct
> > > > > > intel_dp *intel_dp,
> > > > > > > * Optimize this later for the minimum possible link rate/lane
> > count
> > > > > > > * with DSC enabled for the requested mode.
> > > > > > > */
> > > > > > > - pipe_config->pipe_bpp = pipe_bpp;
> > > > > > > + pipe_config->pipe_bpp = max_dsc_pipe_bpp;
> > > > > > > pipe_config->port_clock = limits->max_rate;
> > > > > > > pipe_config->lane_count = limits->max_lane_count;
> > > > > > >
> > > > > > > --
> > > > > > > 2.32.0
> > > > > > >
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-11-02 14:57 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-27 9:53 [Intel-gfx] [PATCH] drm/i915/dsc: Fix the usage of uncompressed bpp Vandita Kulkarni
2021-10-27 14:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-27 18:02 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-27 19:26 ` [Intel-gfx] [PATCH] " Navare, Manasi
2021-10-28 4:37 ` Kulkarni, Vandita
2021-10-29 23:12 ` Navare, Manasi
2021-11-01 16:45 ` Kulkarni, Vandita
2021-11-02 4:40 ` Navare, Manasi
2021-11-02 4:35 ` Kulkarni, Vandita
2021-11-02 15:09 ` Navare, Manasi
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