* [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver
@ 2021-10-28 13:23 Akhil R
2021-10-28 13:23 ` [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
` (4 more replies)
0 siblings, 5 replies; 21+ messages in thread
From: Akhil R @ 2021-10-28 13:23 UTC (permalink / raw)
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Akhil R
Add support for NVIDIA Tegra general purpose DMA driver for
Tegra186 and Tegra194 platform.
Changes in patch v11:
* Removed unused label. Added description in doc
* Fixed dt_binding_check warnings.
v10 - https://lkml.org/lkml/2021/10/25/854
Akhil R (4):
dt-bindings: dmaengine: Add doc for tegra gpcdma
dmaengine: tegra: Add tegra gpcdma driver
arm64: defconfig: tegra: Enable GPCDMA
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1279 ++++++++++++++++++++
9 files changed, 1504 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
create mode 100644 drivers/dma/tegra186-gpc-dma.c
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
@ 2021-10-28 13:23 ` Akhil R
2021-11-02 13:20 ` Rob Herring
2021-10-28 13:23 ` [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
` (3 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Akhil R @ 2021-10-28 13:23 UTC (permalink / raw)
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Akhil R
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 +++++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
new file mode 100644
index 0000000..bc97efc
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
+
+description: |
+ The Tegra General Purpose Central (GPC) DMA controller is used for faster
+ data transfers between memory to memory, memory to device and device to
+ memory.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Rajesh Gumasta <rgumasta@nvidia.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+ - items:
+ - const: nvidia,tegra186-gpcdma
+ - const: nvidia,tegra194-gpcdma
+
+ "#dma-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: |
+ Should contain all of the per-channel DMA interrupts in
+ ascending order with respect to the DMA channel index.
+ minItems: 1
+ maxItems: 32
+
+ resets:
+ description: |
+ Should contain the reset phandle for gpcdma.
+ maxItems: 1
+
+ reset-names:
+ const: gpcdma
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x0>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+...
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-10-28 13:23 ` [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
@ 2021-10-28 13:23 ` Akhil R
2021-10-29 2:00 ` kernel test robot
2021-10-29 14:27 ` kernel test robot
2021-10-28 13:23 ` [PATCH v11 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
` (2 subsequent siblings)
4 siblings, 2 replies; 21+ messages in thread
From: Akhil R @ 2021-10-28 13:23 UTC (permalink / raw)
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Akhil R, Pavan Kunapuli
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1279 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 1292 insertions(+)
create mode 100644 drivers/dma/tegra186-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 80c2c03..35095ae 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -629,6 +629,18 @@ config TXX9_DMAC
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config TEGRA186_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TEGRA20_APB_DMA
tristate "NVIDIA Tegra20 APB DMA support"
depends on ARCH_TEGRA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 616d926..2f1b87f 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
obj-$(CONFIG_SPRD_DMA) += sprd-dma.o
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
new file mode 100644
index 0000000..efb1553
--- /dev/null
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -0,0 +1,1279 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for NVIDIA Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/minmax.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/reset.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+
+#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
+
+#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
+
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
+#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
+#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT 23
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_MIN 1
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_MAX 16
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR 0xF
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR 0xE
+#define TEGRA_DMA_PERIPH_ID_ERR 0xD
+#define TEGRA_DMA_STREAM_ID_ERR 0xC
+#define TEGRA_DMA_MC_SLAVE_ERR 0xB
+#define TEGRA_DMA_MMIO_SLAVE_ERR 0xA
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ unsigned int nr_channels;
+ unsigned int channel_reg_size;
+ unsigned int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+};
+
+struct tegra_dma_channel;
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned int stream_id;
+ unsigned long chan_base_offset;
+ struct tegra_dma_channel_regs ch_regs;
+ raw_spinlock_t lock;
+ bool busy;
+ struct tegra_dma *tdma;
+ int slave_id;
+ enum dma_transfer_direction sid_dir;
+ struct dma_slave_config dma_sconfig;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ unsigned long sid_m2d_reserved;
+ unsigned long sid_d2m_reserved;
+ unsigned long sid_m2m_reserved;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ if (!is_slave_direction(direction))
+ return 0;
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_DEV_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ }
+
+ tdc->sid_dir = direction;
+
+ return 0;
+}
+
+static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ switch (tdc->sid_dir) {
+ case DMA_MEM_TO_DEV:
+ clear_bit(sid, &tdma->sid_m2d_reserved);
+ break;
+ case DMA_DEV_TO_MEM:
+ clear_bit(sid, &tdma->sid_d2m_reserved);
+ break;
+ }
+
+ tdc->sid_dir = DMA_TRANS_NONE;
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ kfree(container_of(vd, struct tegra_dma_desc, vd));
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ tdc->config_init = true;
+
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret)
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_channel_regs *ch_regs = &tdc->ch_regs;
+ struct virt_dma_desc *vdesc;
+
+ if (tdc->busy)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ list_del(&vdesc->node);
+
+ tdc->dma_desc->tdc = tdc;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+
+ tdc->busy = true;
+}
+
+static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ dma_desc = tdc->dma_desc;
+ dma_desc->bytes_transferred += dma_desc->bytes_requested;
+
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ u32 status;
+
+ raw_spin_lock(&tdc->lock);
+
+ /* Check channel error status register */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+ if (status) {
+ tegra_dma_chan_decode_error(tdc, status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+
+ tegra_dma_xfer_complete(tdc);
+ tegra_dma_start(tdc);
+
+ ret = IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return ret;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tegra_dma_start(tdc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
+{
+ int ret;
+ unsigned long status;
+
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+ if (ret) {
+ dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+
+ return ret;
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->dma_desc) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause)
+ err = tegra_dma_pause(tdc);
+ else
+ err = tegra_dma_stop_client(tdc);
+
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tegra_dma_xfer_complete(tdc);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ }
+
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ tegra_dma_stop(tdc);
+
+ tdc->dma_desc->bytes_transferred +=
+ tdc->dma_desc->bytes_requested - (wcount * 4);
+
+skip_dma_stop:
+ tegra_dma_sid_free(tdc);
+ kfree(tdc->dma_desc);
+ vchan_free_chan_resources(&tdc->vc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct virt_dma_desc *vd;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ vd = vchan_find_desc(&tdc->vc, cookie);
+ if (vd) {
+ dma_desc = vd_to_tegra_dma_desc(vd);
+ residual = dma_desc->bytes_requested;
+ dma_set_residue(txstate, residual);
+ } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) {
+ dma_desc = tdc->dma_desc;
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ } else {
+ dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ default:
+ dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");
+ return -EINVAL;
+ }
+}
+
+static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size, enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ unsigned int burst_mmio_width, burst_byte;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ * If burst_size is not specified from client, then use
+ * len to calculate the optimum burst size
+ */
+ burst_byte = burst_size ? burst_size * slave_bw : len;
+ burst_mmio_width = burst_byte / 4;
+
+ clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
+ TEGRA_GPCDMA_MMIOSEQ_BURST_MAX);
+
+ return (fls(burst_mmio_width) - 1) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
+ }
+
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
+ size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ if ((len & 3) || (dest & 3) || len > max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ return NULL;
+ }
+
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ dma_desc->bytes_requested += len;
+ tdc->ch_regs.src_ptr = 0;
+ tdc->ch_regs.dst_ptr = dest;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ tdc->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = 0;
+ tdc->ch_regs.mc_seq = mc_seq;
+
+ tdc->dma_desc = dma_desc;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ if ((len & 3) || (src & 3) || (dest & 3) || len > max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ return NULL;
+ }
+
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ dma_desc->bytes_requested += len;
+ tdc->ch_regs.src_ptr = src;
+ tdc->ch_regs.dst_ptr = dest;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
+ tdc->ch_regs.high_addr_ptr |=
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ /* Word count reg takes value as (N +1) words */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = 0;
+ tdc->ch_regs.mc_seq = mc_seq;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = tegra_dma_sid_reserve(tdc, direction);
+ if (ret)
+ return NULL;
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping on both MC and MMIO side */
+
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ tdc->ch_regs.src_ptr = mem;
+ tdc->ch_regs.dst_ptr = apb_ptr;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
+ } else if (direction == DMA_DEV_TO_MEM) {
+ tdc->ch_regs.src_ptr = apb_ptr;
+ tdc->ch_regs.dst_ptr = mem;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = mmio_seq;
+ tdc->ch_regs.mc_seq = mc_seq;
+ tdc->dma_desc = dma_desc;
+ }
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_chan_synchronize(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ vchan_synchronize(&tdc->vc);
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ tegra_dma_terminate_all(dc);
+
+ tegra_dma_chan_synchronize(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->config_init = false;
+ tdc->slave_id = -1;
+ tdc->sid_dir = DMA_TRANS_NONE;
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ struct iommu_fwspec *iommu_spec;
+ unsigned int stream_id, i;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ int ret;
+
+ cdata = of_device_get_match_data(&pdev->dev);
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
+ "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ iommu_spec = dev_iommu_fwspec_get(&pdev->dev);
+ if (!iommu_spec) {
+ dev_err(&pdev->dev, "Missing iommu stream-id\n");
+ return -EINVAL;
+ }
+ stream_id = iommu_spec->ids[0] & 0xffff;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!res) {
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ return -EINVAL;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret,
+ "request_irq failed for channel %d\n", i);
+ return ret;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA driver registration failed\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA OF registration failed\n");
+
+ dma_async_device_unregister(&tdma->dma_dev);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+
+ return 0;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned long flags;
+ unsigned int i;
+ bool busy;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ busy = tdc->busy;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+
+ if (busy) {
+ dev_err(tdma->dev, "channel %u busy\n", i);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned int i;
+
+ reset_control_reset(tdma->rst);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tegra_dma_program_sid(tdc, i, tdc->stream_id);
+ }
+
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <pkunapuli@nvidia.com>");
+MODULE_AUTHOR("Rajesh Gumasta <rgumasta@nvidia.com>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v11 3/4] arm64: defconfig: tegra: Enable GPCDMA
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-10-28 13:23 ` [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-10-28 13:23 ` [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-10-28 13:23 ` Akhil R
2021-10-28 13:23 ` [PATCH v11 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
4 siblings, 0 replies; 21+ messages in thread
From: Akhil R @ 2021-10-28 13:23 UTC (permalink / raw)
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Akhil R
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 156d96a..6616148 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -928,6 +928,7 @@ CONFIG_MV_XOR=y
CONFIG_MV_XOR_V2=y
CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
+CONFIG_TEGRA186_GPC_DMA=m
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
CONFIG_QCOM_BAM_DMA=y
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v11 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
` (2 preceding siblings ...)
2021-10-28 13:23 ` [PATCH v11 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
@ 2021-10-28 13:23 ` Akhil R
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
4 siblings, 0 replies; 21+ messages in thread
From: Akhil R @ 2021-10-28 13:23 UTC (permalink / raw)
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Akhil R
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index fcd71bf..f5ef04d3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,10 @@
};
};
+ dma-controller@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index e94f8ad..355d53c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,50 @@
snps,rxpbl = <8>;
};
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index c4058ee..5bc74af 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -49,6 +49,10 @@
};
};
+ dma-controller@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c8250a3..94094f3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -72,6 +72,50 @@
snps,rxpbl = <8>;
};
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-10-28 13:23 ` [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-10-29 2:00 ` kernel test robot
2021-10-29 14:27 ` kernel test robot
1 sibling, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-10-29 2:00 UTC (permalink / raw)
To: Akhil R
Cc: kbuild-all, dan.j.williams, devicetree, dmaengine, jonathanh,
kyarlagadda, ldewangan, linux-kernel, linux-tegra, p.zabel,
rgumasta
[-- Attachment #1: Type: text/plain, Size: 9404 bytes --]
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on vkoul-dmaengine/next arm64/for-next/core v5.15-rc7 next-20211028]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/020f86b695432467db8b697540871173f6d751c8
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
git checkout 020f86b695432467db8b697540871173f6d751c8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_reserve':
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
299 | switch (direction) {
| ^~~~~~
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
324 | switch (tdc->sid_dir) {
| ^~~~~~
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
In file included from drivers/dma/tegra186-gpc-dma.c:8:
drivers/dma/tegra186-gpc-dma.c: In function 'get_burst_size':
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
In file included from include/linux/minmax.h:5,
from drivers/dma/tegra186-gpc-dma.c:8:
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/const.h:12:55: note: in definition of macro '__is_constexpr'
12 | (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
| ^
include/linux/minmax.h:26:39: note: in expansion of macro '__no_side_effects'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
In file included from drivers/dma/tegra186-gpc-dma.c:8:
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:28:27: note: in definition of macro '__cmp'
28 | #define __cmp(x, y, op) ((x) op (y) ? (x) : (y))
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
vim +/DMA_MEM_TO_MEM +299 drivers/dma/tegra186-gpc-dma.c
289
290 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
291 enum dma_transfer_direction direction)
292 {
293 struct tegra_dma *tdma = tdc->tdma;
294 unsigned int sid = tdc->slave_id;
295
296 if (!is_slave_direction(direction))
297 return 0;
298
> 299 switch (direction) {
300 case DMA_MEM_TO_DEV:
301 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
302 dev_err(tdma->dev, "slave id already in use\n");
303 return -EINVAL;
304 }
305 break;
306 case DMA_DEV_TO_MEM:
307 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
308 dev_err(tdma->dev, "slave id already in use\n");
309 return -EINVAL;
310 }
311 break;
312 }
313
314 tdc->sid_dir = direction;
315
316 return 0;
317 }
318
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 56240 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver
@ 2021-10-29 2:00 ` kernel test robot
0 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-10-29 2:00 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 9579 bytes --]
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on vkoul-dmaengine/next arm64/for-next/core v5.15-rc7 next-20211028]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/020f86b695432467db8b697540871173f6d751c8
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
git checkout 020f86b695432467db8b697540871173f6d751c8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_reserve':
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
299 | switch (direction) {
| ^~~~~~
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
>> drivers/dma/tegra186-gpc-dma.c:299:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
324 | switch (tdc->sid_dir) {
| ^~~~~~
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c:324:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
In file included from drivers/dma/tegra186-gpc-dma.c:8:
drivers/dma/tegra186-gpc-dma.c: In function 'get_burst_size':
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
In file included from include/linux/minmax.h:5,
from drivers/dma/tegra186-gpc-dma.c:8:
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/const.h:12:55: note: in definition of macro '__is_constexpr'
12 | (sizeof(int) == sizeof(*(8 ? ((void *)((long)(x) * 0l)) : (int *)8)))
| ^
include/linux/minmax.h:26:39: note: in expansion of macro '__no_side_effects'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
In file included from drivers/dma/tegra186-gpc-dma.c:8:
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:28:27: note: in definition of macro '__cmp'
28 | #define __cmp(x, y, op) ((x) op (y) ? (x) : (y))
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
vim +/DMA_MEM_TO_MEM +299 drivers/dma/tegra186-gpc-dma.c
289
290 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
291 enum dma_transfer_direction direction)
292 {
293 struct tegra_dma *tdma = tdc->tdma;
294 unsigned int sid = tdc->slave_id;
295
296 if (!is_slave_direction(direction))
297 return 0;
298
> 299 switch (direction) {
300 case DMA_MEM_TO_DEV:
301 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
302 dev_err(tdma->dev, "slave id already in use\n");
303 return -EINVAL;
304 }
305 break;
306 case DMA_DEV_TO_MEM:
307 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
308 dev_err(tdma->dev, "slave id already in use\n");
309 return -EINVAL;
310 }
311 break;
312 }
313
314 tdc->sid_dir = direction;
315
316 return 0;
317 }
318
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 56240 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-10-28 13:23 ` [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-10-29 14:27 ` kernel test robot
2021-10-29 14:27 ` kernel test robot
1 sibling, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-10-29 14:27 UTC (permalink / raw)
To: Akhil R
Cc: kbuild-all, dan.j.williams, devicetree, dmaengine, jonathanh,
kyarlagadda, ldewangan, linux-kernel, linux-tegra, p.zabel,
rgumasta
[-- Attachment #1: Type: text/plain, Size: 14157 bytes --]
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on vkoul-dmaengine/next arm64/for-next/core v5.15-rc7 next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: openrisc-randconfig-r031-20211029 (attached as .config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/020f86b695432467db8b697540871173f6d751c8
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
git checkout 020f86b695432467db8b697540871173f6d751c8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:28:40: note: in definition of macro '__cmp'
28 | #define __cmp(x, y, op) ((x) op (y) ? (x) : (y))
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:31:24: note: in definition of macro '__cmp_once'
31 | typeof(x) unique_x = (x); \
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:31:39: note: in definition of macro '__cmp_once'
31 | typeof(x) unique_x = (x); \
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:785:74: warning: right shift count >= width of type [-Wshift-count-overflow]
785 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:852:65: warning: right shift count >= width of type [-Wshift-count-overflow]
852 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:854:66: warning: right shift count >= width of type [-Wshift-count-overflow]
854 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:960:81: warning: right shift count >= width of type [-Wshift-count-overflow]
960 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:965:81: warning: right shift count >= width of type [-Wshift-count-overflow]
965 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
| ^~
cc1: some warnings being treated as errors
vim +785 drivers/dma/tegra186-gpc-dma.c
676
677 static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
678 u32 burst_size, enum dma_slave_buswidth slave_bw,
679 int len)
680 {
681 unsigned int burst_mmio_width, burst_byte;
682
683 /*
684 * burst_size from client is in terms of the bus_width.
685 * convert that into words.
686 * If burst_size is not specified from client, then use
687 * len to calculate the optimum burst size
688 */
689 burst_byte = burst_size ? burst_size * slave_bw : len;
690 burst_mmio_width = burst_byte / 4;
691
> 692 clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
693 TEGRA_GPCDMA_MMIOSEQ_BURST_MAX);
694
695 return (fls(burst_mmio_width) - 1) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT;
696 }
697
698 static int get_transfer_param(struct tegra_dma_channel *tdc,
699 enum dma_transfer_direction direction,
700 unsigned long *apb_addr,
701 unsigned long *mmio_seq,
702 unsigned long *csr,
703 unsigned int *burst_size,
704 enum dma_slave_buswidth *slave_bw)
705 {
706 switch (direction) {
707 case DMA_MEM_TO_DEV:
708 *apb_addr = tdc->dma_sconfig.dst_addr;
709 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
710 *burst_size = tdc->dma_sconfig.dst_maxburst;
711 *slave_bw = tdc->dma_sconfig.dst_addr_width;
712 *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
713 return 0;
714 case DMA_DEV_TO_MEM:
715 *apb_addr = tdc->dma_sconfig.src_addr;
716 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
717 *burst_size = tdc->dma_sconfig.src_maxburst;
718 *slave_bw = tdc->dma_sconfig.src_addr_width;
719 *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
720 return 0;
721 case DMA_MEM_TO_MEM:
722 *burst_size = tdc->dma_sconfig.src_addr_width;
723 *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
724 return 0;
725 default:
726 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
727 }
728
729 return -EINVAL;
730 }
731
732 static struct dma_async_tx_descriptor *
733 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
734 size_t len, unsigned long flags)
735 {
736 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
737 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
738 struct tegra_dma_desc *dma_desc;
739 unsigned long csr, mc_seq;
740
741 if ((len & 3) || (dest & 3) || len > max_dma_count) {
742 dev_err(tdc2dev(tdc),
743 "DMA length/memory address is not supported\n");
744 return NULL;
745 }
746
747 /* Set dma mode to fixed pattern */
748 csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
749 /* Enable once or continuous mode */
750 csr |= TEGRA_GPCDMA_CSR_ONCE;
751 /* Enable IRQ mask */
752 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
753 /* Enable the dma interrupt */
754 if (flags & DMA_PREP_INTERRUPT)
755 csr |= TEGRA_GPCDMA_CSR_IE_EOC;
756 /* Configure default priority weight for the channel */
757 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
758
759 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
760 /* retain stream-id and clean rest */
761 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
762
763 /* Set the address wrapping */
764 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
765 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
766 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
767 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
768
769 /* Program outstanding MC requests */
770 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
771 /* Set burst size */
772 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
773
774 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
775 if (!dma_desc)
776 return NULL;
777
778 dma_desc->bytes_requested = 0;
779 dma_desc->bytes_transferred = 0;
780
781 dma_desc->bytes_requested += len;
782 tdc->ch_regs.src_ptr = 0;
783 tdc->ch_regs.dst_ptr = dest;
784 tdc->ch_regs.high_addr_ptr =
> 785 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
786 tdc->ch_regs.fixed_pattern = value;
787 /* Word count reg takes value as (N +1) words */
788 tdc->ch_regs.wcount = ((len - 4) >> 2);
789 tdc->ch_regs.csr = csr;
790 tdc->ch_regs.mmio_seq = 0;
791 tdc->ch_regs.mc_seq = mc_seq;
792
793 tdc->dma_desc = dma_desc;
794
795 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
796 }
797
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33190 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver
@ 2021-10-29 14:27 ` kernel test robot
0 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-10-29 14:27 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 14436 bytes --]
Hi Akhil,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on vkoul-dmaengine/next arm64/for-next/core v5.15-rc7 next-20211029]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: openrisc-randconfig-r031-20211029 (attached as .config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/020f86b695432467db8b697540871173f6d751c8
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/Add-NVIDIA-Tegra-GPC-DMA-driver/20211028-212920
git checkout 020f86b695432467db8b697540871173f6d751c8
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:28:40: note: in definition of macro '__cmp'
28 | #define __cmp(x, y, op) ((x) op (y) ? (x) : (y))
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:31:24: note: in definition of macro '__cmp_once'
31 | typeof(x) unique_x = (x); \
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
include/linux/minmax.h:20:35: warning: comparison of distinct pointer types lacks a cast
20 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1)))
| ^~
include/linux/minmax.h:31:39: note: in definition of macro '__cmp_once'
31 | typeof(x) unique_x = (x); \
| ^
include/linux/minmax.h:45:25: note: in expansion of macro '__careful_cmp'
45 | #define min(x, y) __careful_cmp(x, y, <)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:28: note: in expansion of macro 'min'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
include/linux/minmax.h:26:18: note: in expansion of macro '__typecheck'
26 | (__typecheck(x, y) && __no_side_effects(x, y))
| ^~~~~~~~~~~
include/linux/minmax.h:36:31: note: in expansion of macro '__safe_cmp'
36 | __builtin_choose_expr(__safe_cmp(x, y), \
| ^~~~~~~~~~
include/linux/minmax.h:52:25: note: in expansion of macro '__careful_cmp'
52 | #define max(x, y) __careful_cmp(x, y, >)
| ^~~~~~~~~~~~~
include/linux/minmax.h:89:45: note: in expansion of macro 'max'
89 | #define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi)
| ^~~
drivers/dma/tegra186-gpc-dma.c:692:9: note: in expansion of macro 'clamp'
692 | clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
| ^~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:785:74: warning: right shift count >= width of type [-Wshift-count-overflow]
785 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:852:65: warning: right shift count >= width of type [-Wshift-count-overflow]
852 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:854:66: warning: right shift count >= width of type [-Wshift-count-overflow]
854 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:960:81: warning: right shift count >= width of type [-Wshift-count-overflow]
960 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:965:81: warning: right shift count >= width of type [-Wshift-count-overflow]
965 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
| ^~
cc1: some warnings being treated as errors
vim +785 drivers/dma/tegra186-gpc-dma.c
676
677 static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
678 u32 burst_size, enum dma_slave_buswidth slave_bw,
679 int len)
680 {
681 unsigned int burst_mmio_width, burst_byte;
682
683 /*
684 * burst_size from client is in terms of the bus_width.
685 * convert that into words.
686 * If burst_size is not specified from client, then use
687 * len to calculate the optimum burst size
688 */
689 burst_byte = burst_size ? burst_size * slave_bw : len;
690 burst_mmio_width = burst_byte / 4;
691
> 692 clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
693 TEGRA_GPCDMA_MMIOSEQ_BURST_MAX);
694
695 return (fls(burst_mmio_width) - 1) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT;
696 }
697
698 static int get_transfer_param(struct tegra_dma_channel *tdc,
699 enum dma_transfer_direction direction,
700 unsigned long *apb_addr,
701 unsigned long *mmio_seq,
702 unsigned long *csr,
703 unsigned int *burst_size,
704 enum dma_slave_buswidth *slave_bw)
705 {
706 switch (direction) {
707 case DMA_MEM_TO_DEV:
708 *apb_addr = tdc->dma_sconfig.dst_addr;
709 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
710 *burst_size = tdc->dma_sconfig.dst_maxburst;
711 *slave_bw = tdc->dma_sconfig.dst_addr_width;
712 *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
713 return 0;
714 case DMA_DEV_TO_MEM:
715 *apb_addr = tdc->dma_sconfig.src_addr;
716 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
717 *burst_size = tdc->dma_sconfig.src_maxburst;
718 *slave_bw = tdc->dma_sconfig.src_addr_width;
719 *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
720 return 0;
721 case DMA_MEM_TO_MEM:
722 *burst_size = tdc->dma_sconfig.src_addr_width;
723 *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
724 return 0;
725 default:
726 dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
727 }
728
729 return -EINVAL;
730 }
731
732 static struct dma_async_tx_descriptor *
733 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
734 size_t len, unsigned long flags)
735 {
736 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
737 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
738 struct tegra_dma_desc *dma_desc;
739 unsigned long csr, mc_seq;
740
741 if ((len & 3) || (dest & 3) || len > max_dma_count) {
742 dev_err(tdc2dev(tdc),
743 "DMA length/memory address is not supported\n");
744 return NULL;
745 }
746
747 /* Set dma mode to fixed pattern */
748 csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
749 /* Enable once or continuous mode */
750 csr |= TEGRA_GPCDMA_CSR_ONCE;
751 /* Enable IRQ mask */
752 csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
753 /* Enable the dma interrupt */
754 if (flags & DMA_PREP_INTERRUPT)
755 csr |= TEGRA_GPCDMA_CSR_IE_EOC;
756 /* Configure default priority weight for the channel */
757 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
758
759 mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
760 /* retain stream-id and clean rest */
761 mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
762
763 /* Set the address wrapping */
764 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
765 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
766 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
767 TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
768
769 /* Program outstanding MC requests */
770 mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
771 /* Set burst size */
772 mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
773
774 dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
775 if (!dma_desc)
776 return NULL;
777
778 dma_desc->bytes_requested = 0;
779 dma_desc->bytes_transferred = 0;
780
781 dma_desc->bytes_requested += len;
782 tdc->ch_regs.src_ptr = 0;
783 tdc->ch_regs.dst_ptr = dest;
784 tdc->ch_regs.high_addr_ptr =
> 785 FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
786 tdc->ch_regs.fixed_pattern = value;
787 /* Word count reg takes value as (N +1) words */
788 tdc->ch_regs.wcount = ((len - 4) >> 2);
789 tdc->ch_regs.csr = csr;
790 tdc->ch_regs.mmio_seq = 0;
791 tdc->ch_regs.mc_seq = mc_seq;
792
793 tdc->dma_desc = dma_desc;
794
795 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
796 }
797
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 33190 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma
2021-10-28 13:23 ` [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
@ 2021-11-02 13:20 ` Rob Herring
2021-11-03 10:34 ` Akhil R
0 siblings, 1 reply; 21+ messages in thread
From: Rob Herring @ 2021-11-02 13:20 UTC (permalink / raw)
To: Akhil R
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta,
thierry.reding, vkoul
On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote:
> Add DT binding document for Nvidia Tegra GPCDMA controller.
>
> Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> ---
> .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115 +++++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> new file mode 100644
> index 0000000..bc97efc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
> +
> +description: |
> + The Tegra General Purpose Central (GPC) DMA controller is used for faster
> + data transfers between memory to memory, memory to device and device to
> + memory.
> +
> +maintainers:
> + - Jon Hunter <jonathanh@nvidia.com>
> + - Rajesh Gumasta <rgumasta@nvidia.com>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + oneOf:
> + - enum:
> + - nvidia,tegra186-gpcdma
> + - nvidia,tegra194-gpcdma
> + - items:
> + - const: nvidia,tegra186-gpcdma
> + - const: nvidia,tegra194-gpcdma
One of these is wrong. Either 186 has a fallback to 194 or it doesn't.
> +
> + "#dma-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + description: |
Don't need '|' if there's no formatting.
> + Should contain all of the per-channel DMA interrupts in
> + ascending order with respect to the DMA channel index.
> + minItems: 1
> + maxItems: 32
> +
> + resets:
> + description: |
> + Should contain the reset phandle for gpcdma.
Not really a useful description. Drop.
> + maxItems: 1
> +
> + reset-names:
> + const: gpcdma
> +
> + iommus:
> + maxItems: 1
> +
> + dma-coherent: true
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - resets
> + - reset-names
> + - "#dma-cells"
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/tegra186-mc.h>
> + #include <dt-bindings/reset/tegra186-reset.h>
> +
> + dma-controller@2600000 {
> + compatible = "nvidia,tegra186-gpcdma";
> + reg = <0x2600000 0x0>;
> + resets = <&bpmp TEGRA186_RESET_GPCDMA>;
> + reset-names = "gpcdma";
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
> + dma-coherent;
> + };
> +...
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma
2021-11-02 13:20 ` Rob Herring
@ 2021-11-03 10:34 ` Akhil R
2021-11-18 23:35 ` Rob Herring
0 siblings, 1 reply; 21+ messages in thread
From: Akhil R @ 2021-11-03 10:34 UTC (permalink / raw)
To: Rob Herring
Cc: dan.j.williams, devicetree, dmaengine, Jonathan Hunter,
Krishna Yarlagadda, Laxman Dewangan, linux-kernel, linux-tegra,
p.zabel, Rajesh Gumasta, thierry.reding, vkoul
> On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote:
> > Add DT binding document for Nvidia Tegra GPCDMA controller.
> >
> > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
> > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > ---
> > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115
> +++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> > b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> > new file mode 100644
> > index 0000000..bc97efc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.ya
> > +++ ml
> > @@ -0,0 +1,115 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
> > +
> > +description: |
> > + The Tegra General Purpose Central (GPC) DMA controller is used for
> > +faster
> > + data transfers between memory to memory, memory to device and
> > +device to
> > + memory.
> > +
> > +maintainers:
> > + - Jon Hunter <jonathanh@nvidia.com>
> > + - Rajesh Gumasta <rgumasta@nvidia.com>
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - enum:
> > + - nvidia,tegra186-gpcdma
> > + - nvidia,tegra194-gpcdma
> > + - items:
> > + - const: nvidia,tegra186-gpcdma
> > + - const: nvidia,tegra194-gpcdma
>
> One of these is wrong. Either 186 has a fallback to 194 or it doesn't.
Not sure if I understood this correctly. Tegra186 and 194 have different chip data
inside driver based on the compatible. I guess, it then needs to be one of these.
Or is the mistake something related to formatting?
Agreed with other comments.
--
nvpublic
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
` (3 preceding siblings ...)
2021-10-28 13:23 ` [PATCH v11 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
@ 2021-11-09 14:35 ` Akhil R
2021-11-09 14:35 ` [PATCH v12 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
` (3 more replies)
4 siblings, 4 replies; 21+ messages in thread
From: Akhil R @ 2021-11-09 14:35 UTC (permalink / raw)
To: akhilrajeev
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul
Add support for NVIDIA Tegra general purpose DMA driver for
Tegra186 and Tegra194 platform.
Changes in patch v11:
* corrections in dt-binding doc
* fixes for warnings reported-by: kernel test robot <lkp@intel.com>
v11 - https://lkml.org/lkml/2021/10/28/454
Akhil R (4):
dt-bindings: dmaengine: Add doc for tegra gpcdma
dmaengine: tegra: Add tegra gpcdma driver
arm64: defconfig: tegra: Enable GPCDMA
arm64: tegra: Add GPCDMA node for tegra186 and tegra194
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 113 ++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 +
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 +
arch/arm64/configs/defconfig | 1 +
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1281 ++++++++++++++++++++
9 files changed, 1504 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
create mode 100644 drivers/dma/tegra186-gpc-dma.c
--
2.7.4
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v12 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
@ 2021-11-09 14:35 ` Akhil R
2021-11-09 14:35 ` [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
` (2 subsequent siblings)
3 siblings, 0 replies; 21+ messages in thread
From: Akhil R @ 2021-11-09 14:35 UTC (permalink / raw)
To: akhilrajeev
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul
Add DT binding document for Nvidia Tegra GPCDMA controller.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
.../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 113 +++++++++++++++++++++
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
new file mode 100644
index 0000000..f2d63d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
+
+description:
+ The Tegra General Purpose Central (GPC) DMA controller is used for faster
+ data transfers between memory to memory, memory to device and device to
+ memory.
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Rajesh Gumasta <rgumasta@nvidia.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nvidia,tegra186-gpcdma
+ - nvidia,tegra194-gpcdma
+ - items:
+ - const: nvidia,tegra186-gpcdma
+ - const: nvidia,tegra194-gpcdma
+
+ "#dma-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Should contain all of the per-channel DMA interrupts in
+ ascending order with respect to the DMA channel index.
+ minItems: 1
+ maxItems: 32
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: gpcdma
+
+ iommus:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - resets
+ - reset-names
+ - "#dma-cells"
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/memory/tegra186-mc.h>
+ #include <dt-bindings/reset/tegra186-reset.h>
+
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x0>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ };
+...
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-11-09 14:35 ` [PATCH v12 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
@ 2021-11-09 14:35 ` Akhil R
2021-11-12 19:10 ` kernel test robot
2021-11-17 17:39 ` kernel test robot
2021-11-09 14:35 ` [PATCH v12 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-11-09 14:35 ` [PATCH v12 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
3 siblings, 2 replies; 21+ messages in thread
From: Akhil R @ 2021-11-09 14:35 UTC (permalink / raw)
To: akhilrajeev
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul, Pavan Kunapuli
Adding GPC DMA controller driver for Tegra186 and Tegra194. The driver
supports dma transfers between memory to memory, IO peripheral to memory
and memory to IO peripheral.
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/tegra186-gpc-dma.c | 1281 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 1294 insertions(+)
create mode 100644 drivers/dma/tegra186-gpc-dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 80c2c03..35095ae 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -629,6 +629,18 @@ config TXX9_DMAC
Support the TXx9 SoC internal DMA controller. This can be
integrated in chips such as the Toshiba TX4927/38/39.
+config TEGRA186_GPC_DMA
+ tristate "NVIDIA Tegra GPC DMA support"
+ depends on ARCH_TEGRA_186_SOC || ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select DMA_ENGINE
+ help
+ Support for the NVIDIA Tegra186 and Tegra194 GPC DMA controller
+ driver. The DMA controller has multiple DMA channels which can
+ be configured for different peripherals like UART, SPI, etc
+ which are on APB bus.
+ This DMA controller transfers data from memory to peripheral FIFO
+ or vice versa. It also supports memory to memory data transfer.
+
config TEGRA20_APB_DMA
tristate "NVIDIA Tegra20 APB DMA support"
depends on ARCH_TEGRA || COMPILE_TEST
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 616d926..2f1b87f 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -72,6 +72,7 @@ obj-$(CONFIG_STM32_MDMA) += stm32-mdma.o
obj-$(CONFIG_SPRD_DMA) += sprd-dma.o
obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
+obj-$(CONFIG_TEGRA186_GPC_DMA) += tegra186-gpc-dma.o
obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
obj-$(CONFIG_TEGRA210_ADMA) += tegra210-adma.o
obj-$(CONFIG_TIMB_DMA) += timb_dma.o
diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c
new file mode 100644
index 0000000..12388d0
--- /dev/null
+++ b/drivers/dma/tegra186-gpc-dma.c
@@ -0,0 +1,1281 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * DMA driver for NVIDIA Tegra186 and Tegra194 GPC DMA controller.
+ *
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/minmax.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/reset.h>
+#include <linux/iommu.h>
+#include <linux/platform_device.h>
+#include <linux/version.h>
+#include <dt-bindings/memory/tegra186-mc.h>
+#include "virt-dma.h"
+
+/* CSR register */
+#define TEGRA_GPCDMA_CHAN_CSR 0x00
+#define TEGRA_GPCDMA_CSR_ENB BIT(31)
+#define TEGRA_GPCDMA_CSR_IE_EOC BIT(30)
+#define TEGRA_GPCDMA_CSR_ONCE BIT(27)
+
+#define TEGRA_GPCDMA_CSR_FC_MODE GENMASK(25, 24)
+#define TEGRA_GPCDMA_CSR_FC_MODE_NO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 0)
+#define TEGRA_GPCDMA_CSR_FC_MODE_ONE_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 1)
+#define TEGRA_GPCDMA_CSR_FC_MODE_TWO_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 2)
+#define TEGRA_GPCDMA_CSR_FC_MODE_FOUR_MMIO \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_FC_MODE, 3)
+
+#define TEGRA_GPCDMA_CSR_DMA GENMASK(23, 21)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 0)
+#define TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 1)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_NO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 2)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 3)
+#define TEGRA_GPCDMA_CSR_DMA_MEM2MEM \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 4)
+#define TEGRA_GPCDMA_CSR_DMA_FIXED_PAT \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_DMA, 6)
+
+#define TEGRA_GPCDMA_CSR_REQ_SEL_MASK GENMASK(20, 16)
+#define TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED \
+ FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
+#define TEGRA_GPCDMA_CSR_IRQ_MASK BIT(15)
+#define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10)
+
+/* STATUS register */
+#define TEGRA_GPCDMA_CHAN_STATUS 0x004
+#define TEGRA_GPCDMA_STATUS_BUSY BIT(31)
+#define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30)
+#define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28)
+#define TEGRA_GPCDMA_STATUS_DMA_ACTIVITY BIT(27)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_PAUSE BIT(26)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_RX BIT(25)
+#define TEGRA_GPCDMA_STATUS_CHANNEL_TX BIT(24)
+#define TEGRA_GPCDMA_STATUS_IRQ_INTR_STA BIT(23)
+#define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21)
+#define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20)
+
+#define TEGRA_GPCDMA_CHAN_CSRE 0x008
+#define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31)
+
+/* Source address */
+#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C
+
+/* Destination address */
+#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010
+
+/* High address pointer */
+#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014
+#define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0)
+#define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16)
+
+/* MC sequence register */
+#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18
+#define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31)
+#define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25)
+#define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23)
+#define TEGRA_GPCDMA_MCSEQ_BURST_2 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 0)
+#define TEGRA_GPCDMA_MCSEQ_BURST_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MCSEQ_BURST, 3)
+#define TEGRA_GPCDMA_MCSEQ_WRAP1 GENMASK(22, 20)
+#define TEGRA_GPCDMA_MCSEQ_WRAP0 GENMASK(19, 17)
+#define TEGRA_GPCDMA_MCSEQ_WRAP_NONE 0
+
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK GENMASK(13, 7)
+#define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0)
+
+/* MMIO sequence register */
+#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c
+#define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 0)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 1)
+#define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32 \
+ FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH, 2)
+#define TEGRA_GPCDMA_MMIOSEQ_DATA_SWAP BIT(27)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST GENMASK(26, 23)
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT 23
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_MIN 1U
+#define TEGRA_GPCDMA_MMIOSEQ_BURST_MAX 16U
+#define TEGRA_GPCDMA_MMIOSEQ_MASTER_ID GENMASK(22, 19)
+#define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16)
+#define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7)
+
+/* Channel WCOUNT */
+#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20
+
+/* Transfer count */
+#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24
+
+/* DMA byte count status */
+#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28
+
+/* Error Status Register */
+#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF
+#define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \
+ ((err) >> TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT) & \
+ TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK)
+#define TEGRA_DMA_BM_FIFO_FULL_ERR 0xF
+#define TEGRA_DMA_PERIPH_FIFO_FULL_ERR 0xE
+#define TEGRA_DMA_PERIPH_ID_ERR 0xD
+#define TEGRA_DMA_STREAM_ID_ERR 0xC
+#define TEGRA_DMA_MC_SLAVE_ERR 0xB
+#define TEGRA_DMA_MMIO_SLAVE_ERR 0xA
+
+/* Fixed Pattern */
+#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34
+
+#define TEGRA_GPCDMA_CHAN_TZ 0x38
+#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0)
+#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1)
+
+#define TEGRA_GPCDMA_CHAN_SPARE 0x3c
+#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16)
+
+/*
+ * If any burst is in flight and DMA paused then this is the time to complete
+ * on-flight burst and update DMA status register.
+ */
+#define TEGRA_GPCDMA_BURST_COMPLETE_TIME 20
+#define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 100
+
+/* Channel base address offset from GPCDMA base address */
+#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x10000
+
+struct tegra_dma;
+
+/*
+ * tegra_dma_chip_data Tegra chip specific DMA data
+ * @nr_channels: Number of channels available in the controller.
+ * @channel_reg_size: Channel register size.
+ * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
+ * @hw_support_pause: DMA HW engine support pause of the channel.
+ */
+struct tegra_dma_chip_data {
+ unsigned int nr_channels;
+ unsigned int channel_reg_size;
+ unsigned int max_dma_count;
+ bool hw_support_pause;
+};
+
+/* DMA channel registers */
+struct tegra_dma_channel_regs {
+ unsigned long csr;
+ unsigned long src_ptr;
+ unsigned long dst_ptr;
+ unsigned long high_addr_ptr;
+ unsigned long mc_seq;
+ unsigned long mmio_seq;
+ unsigned long wcount;
+ unsigned long fixed_pattern;
+};
+
+/*
+ * tegra_dma_desc: Tegra DMA descriptors which uses virt_dma_desc to
+ * manage client request and keep track of transfer status, callbacks
+ * and request counts etc.
+ */
+struct tegra_dma_desc {
+ struct virt_dma_desc vd;
+ int bytes_requested;
+ int bytes_transferred;
+ struct tegra_dma_channel *tdc;
+};
+
+struct tegra_dma_channel;
+
+/*
+ * tegra_dma_channel: Channel specific information
+ */
+struct tegra_dma_channel {
+ struct virt_dma_chan vc;
+ struct tegra_dma_desc *dma_desc;
+ char name[30];
+ bool config_init;
+ int id;
+ int irq;
+ unsigned int stream_id;
+ unsigned long chan_base_offset;
+ struct tegra_dma_channel_regs ch_regs;
+ raw_spinlock_t lock;
+ bool busy;
+ struct tegra_dma *tdma;
+ int slave_id;
+ enum dma_transfer_direction sid_dir;
+ struct dma_slave_config dma_sconfig;
+};
+
+/*
+ * tegra_dma: Tegra DMA specific information
+ */
+struct tegra_dma {
+ struct dma_device dma_dev;
+ struct device *dev;
+ void __iomem *base_addr;
+ const struct tegra_dma_chip_data *chip_data;
+ struct reset_control *rst;
+ unsigned long sid_m2d_reserved;
+ unsigned long sid_d2m_reserved;
+ unsigned long sid_m2m_reserved;
+ struct tegra_dma_channel channels[0];
+};
+
+static inline void tdc_write(struct tegra_dma_channel *tdc,
+ u32 reg, u32 val)
+{
+ writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
+{
+ return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg);
+}
+
+static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
+{
+ return container_of(dc, struct tegra_dma_channel, vc.chan);
+}
+
+static inline struct tegra_dma_desc *vd_to_tegra_dma_desc(struct virt_dma_desc *vd)
+{
+ return container_of(vd, struct tegra_dma_desc, vd);
+}
+
+static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
+{
+ return tdc->vc.chan.device->dev;
+}
+
+static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)
+{
+ dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n",
+ tdc->id, tdc->name);
+ dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR)
+ );
+ dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT),
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS)
+ );
+ dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n",
+ tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS));
+}
+
+static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ if (!is_slave_direction(direction))
+ return 0;
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ case DMA_DEV_TO_MEM:
+ if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) {
+ dev_err(tdma->dev, "slave id already in use\n");
+ return -EINVAL;
+ }
+ break;
+ default:
+ break;
+ }
+
+ tdc->sid_dir = direction;
+
+ return 0;
+}
+
+static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma *tdma = tdc->tdma;
+ unsigned int sid = tdc->slave_id;
+
+ switch (tdc->sid_dir) {
+ case DMA_MEM_TO_DEV:
+ clear_bit(sid, &tdma->sid_m2d_reserved);
+ break;
+ case DMA_DEV_TO_MEM:
+ clear_bit(sid, &tdma->sid_d2m_reserved);
+ break;
+ }
+
+ tdc->sid_dir = DMA_TRANS_NONE;
+}
+
+static void tegra_dma_desc_free(struct virt_dma_desc *vd)
+{
+ kfree(container_of(vd, struct tegra_dma_desc, vd));
+}
+
+static int tegra_dma_slave_config(struct dma_chan *dc,
+ struct dma_slave_config *sconfig)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
+ tdc->config_init = true;
+
+ return 0;
+}
+
+static int tegra_dma_pause(struct tegra_dma_channel *tdc)
+{
+ u32 val;
+ int ret;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, TEGRA_GPCDMA_CHAN_CSRE_PAUSE);
+
+ /* Wait until busy bit is de-asserted */
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS,
+ val,
+ !(val & TEGRA_GPCDMA_STATUS_BUSY),
+ TEGRA_GPCDMA_BURST_COMPLETE_TIME,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+
+ if (ret)
+ dev_err(tdc2dev(tdc), "DMA pause timed out\n");
+
+ return ret;
+}
+
+static void tegra_dma_stop(struct tegra_dma_channel *tdc)
+{
+ u32 csr, status;
+
+ csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ /* Disable interrupts */
+ csr &= ~TEGRA_GPCDMA_CSR_IE_EOC;
+
+ /* Disable DMA */
+ csr &= ~TEGRA_GPCDMA_CSR_ENB;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+
+ /* Clear interrupt status if it is there */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status);
+ }
+ tdc->busy = false;
+}
+
+static void tegra_dma_start(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_channel_regs *ch_regs = &tdc->ch_regs;
+ struct virt_dma_desc *vdesc;
+
+ if (tdc->busy)
+ return;
+
+ vdesc = vchan_next_desc(&tdc->vc);
+ if (!vdesc)
+ return;
+
+ tdc->dma_desc = vd_to_tegra_dma_desc(vdesc);
+ list_del(&vdesc->node);
+
+ tdc->dma_desc->tdc = tdc;
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, 0);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr);
+
+ /* Start DMA */
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR,
+ ch_regs->csr | TEGRA_GPCDMA_CSR_ENB);
+
+ tdc->busy = true;
+}
+
+static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc)
+{
+ struct tegra_dma_desc *dma_desc;
+
+ tdc->busy = false;
+ dma_desc = tdc->dma_desc;
+ dma_desc->bytes_transferred += dma_desc->bytes_requested;
+
+ vchan_cookie_complete(&tdc->dma_desc->vd);
+}
+
+static void tegra_dma_chan_decode_error(struct tegra_dma_channel *tdc,
+ unsigned int err_status)
+{
+ switch (TEGRA_GPCDMA_CHAN_ERR_TYPE(err_status)) {
+ case TEGRA_DMA_BM_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d bm fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_FIFO_FULL_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d peripheral fifo full\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_PERIPH_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal peripheral id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_STREAM_ID_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d illegal stream id\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MC_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mc slave error\n", tdc->id);
+ break;
+
+ case TEGRA_DMA_MMIO_SLAVE_ERR:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d mmio slave error\n", tdc->id);
+ break;
+
+ default:
+ dev_err(tdc->tdma->dev,
+ "GPCDMA CH%d security violation %x\n", tdc->id,
+ err_status);
+ }
+}
+
+static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
+{
+ struct tegra_dma_channel *tdc = dev_id;
+ irqreturn_t ret = IRQ_NONE;
+ u32 status;
+
+ raw_spin_lock(&tdc->lock);
+
+ /* Check channel error status register */
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS);
+ if (status) {
+ tegra_dma_chan_decode_error(tdc, status);
+ tegra_dma_dump_chan_regs(tdc);
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF);
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS,
+ TEGRA_GPCDMA_STATUS_ISE_EOC);
+
+ tegra_dma_xfer_complete(tdc);
+ tegra_dma_start(tdc);
+
+ ret = IRQ_HANDLED;
+ }
+
+ raw_spin_unlock(&tdc->lock);
+ return ret;
+}
+
+static void tegra_dma_issue_pending(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->busy)
+ if (vchan_issue_pending(&tdc->vc))
+ tegra_dma_start(tdc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static void tegra_dma_reset_client(struct tegra_dma_channel *tdc)
+{
+ u32 csr = tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR);
+
+ csr &= ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK);
+ csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr);
+}
+
+static int tegra_dma_stop_client(struct tegra_dma_channel *tdc)
+{
+ int ret;
+ unsigned long status;
+
+ /* Before Reading DMA status to figure out number
+ * of bytes transferred by DMA channel:
+ * Change the client associated with the DMA channel
+ * to stop DMA engine from starting any more bursts for
+ * the given client and wait for in flight bursts to complete
+ */
+ tegra_dma_reset_client(tdc);
+
+ /* Wait for in flight data transfer to finish */
+ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME);
+
+ /* If TX/RX path is still active wait till it becomes
+ * inactive
+ */
+
+ ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr +
+ tdc->chan_base_offset +
+ TEGRA_GPCDMA_CHAN_STATUS,
+ status,
+ !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX |
+ TEGRA_GPCDMA_STATUS_CHANNEL_RX)),
+ 5,
+ TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT);
+ if (ret) {
+ dev_err(tdc2dev(tdc), "Timeout waiting for DMA burst completion!\n");
+ tegra_dma_dump_chan_regs(tdc);
+ }
+
+ return ret;
+}
+
+static int tegra_dma_terminate_all(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long wcount = 0;
+ unsigned long status;
+ unsigned long flags;
+ int err;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ if (!tdc->dma_desc) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+ }
+
+ if (!tdc->busy)
+ goto skip_dma_stop;
+
+ if (tdc->tdma->chip_data->hw_support_pause)
+ err = tegra_dma_pause(tdc);
+ else
+ err = tegra_dma_stop_client(tdc);
+
+ if (err) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return err;
+ }
+
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) {
+ dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
+ tegra_dma_xfer_complete(tdc);
+ status = tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS);
+ }
+
+ wcount = tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT);
+ tegra_dma_stop(tdc);
+
+ tdc->dma_desc->bytes_transferred +=
+ tdc->dma_desc->bytes_requested - (wcount * 4);
+
+skip_dma_stop:
+ tegra_dma_sid_free(tdc);
+ kfree(tdc->dma_desc);
+ vchan_free_chan_resources(&tdc->vc);
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return 0;
+}
+
+static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ struct tegra_dma_desc *dma_desc = NULL;
+ struct virt_dma_desc *vd;
+ unsigned int residual;
+ enum dma_status ret;
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+
+ ret = dma_cookie_status(dc, cookie, txstate);
+ if (ret == DMA_COMPLETE) {
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+ }
+
+ vd = vchan_find_desc(&tdc->vc, cookie);
+ if (vd) {
+ dma_desc = vd_to_tegra_dma_desc(vd);
+ residual = dma_desc->bytes_requested;
+ dma_set_residue(txstate, residual);
+ } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) {
+ dma_desc = tdc->dma_desc;
+ residual = dma_desc->bytes_requested -
+ (dma_desc->bytes_transferred %
+ dma_desc->bytes_requested);
+ dma_set_residue(txstate, residual);
+ } else {
+ dev_err(tdc2dev(tdc), "cookie %d is not found\n", cookie);
+ }
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+ return ret;
+}
+
+static inline int get_bus_width(struct tegra_dma_channel *tdc,
+ enum dma_slave_buswidth slave_bw)
+{
+ switch (slave_bw) {
+ case DMA_SLAVE_BUSWIDTH_1_BYTE:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8;
+ case DMA_SLAVE_BUSWIDTH_2_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_16;
+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
+ return TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_32;
+ default:
+ dev_err(tdc2dev(tdc), "given slave bus width is not supported\n");
+ return -EINVAL;
+ }
+}
+
+static unsigned int get_burst_size(struct tegra_dma_channel *tdc,
+ u32 burst_size, enum dma_slave_buswidth slave_bw,
+ int len)
+{
+ unsigned int burst_mmio_width, burst_byte;
+
+ /*
+ * burst_size from client is in terms of the bus_width.
+ * convert that into words.
+ * If burst_size is not specified from client, then use
+ * len to calculate the optimum burst size
+ */
+ burst_byte = burst_size ? burst_size * slave_bw : len;
+ burst_mmio_width = burst_byte / 4;
+
+ clamp(burst_mmio_width, TEGRA_GPCDMA_MMIOSEQ_BURST_MIN,
+ TEGRA_GPCDMA_MMIOSEQ_BURST_MAX);
+
+ return (fls(burst_mmio_width) - 1) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT;
+}
+
+static int get_transfer_param(struct tegra_dma_channel *tdc,
+ enum dma_transfer_direction direction,
+ unsigned long *apb_addr,
+ unsigned long *mmio_seq,
+ unsigned long *csr,
+ unsigned int *burst_size,
+ enum dma_slave_buswidth *slave_bw)
+{
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ *apb_addr = tdc->dma_sconfig.dst_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
+ *burst_size = tdc->dma_sconfig.dst_maxburst;
+ *slave_bw = tdc->dma_sconfig.dst_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2IO_FC;
+ return 0;
+ case DMA_DEV_TO_MEM:
+ *apb_addr = tdc->dma_sconfig.src_addr;
+ *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
+ *burst_size = tdc->dma_sconfig.src_maxburst;
+ *slave_bw = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_IO2MEM_FC;
+ return 0;
+ case DMA_MEM_TO_MEM:
+ *burst_size = tdc->dma_sconfig.src_addr_width;
+ *csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ return 0;
+ default:
+ dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
+ }
+
+ return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,
+ size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ if ((len & 3) || (dest & 3) || len > max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ return NULL;
+ }
+
+ /* Set dma mode to fixed pattern */
+ csr = TEGRA_GPCDMA_CSR_DMA_FIXED_PAT;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ dma_desc->bytes_requested += len;
+ tdc->ch_regs.src_ptr = 0;
+ tdc->ch_regs.dst_ptr = dest;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ tdc->ch_regs.fixed_pattern = value;
+ /* Word count reg takes value as (N +1) words */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = 0;
+ tdc->ch_regs.mc_seq = mc_seq;
+
+ tdc->dma_desc = dma_desc;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,
+ dma_addr_t src, size_t len, unsigned long flags)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;
+ struct tegra_dma_desc *dma_desc;
+ unsigned long csr, mc_seq;
+
+ if ((len & 3) || (src & 3) || (dest & 3) || len > max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ return NULL;
+ }
+
+ /* Set dma mode to memory to memory transfer */
+ csr = TEGRA_GPCDMA_CSR_DMA_MEM2MEM;
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+ /* Configure default priority weight for the channel */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) |
+ (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ /* Set the address wrapping */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+
+ /* Program outstanding MC requests */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+ /* Set burst size */
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ dma_desc->bytes_requested += len;
+ tdc->ch_regs.src_ptr = src;
+ tdc->ch_regs.dst_ptr = dest;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
+ tdc->ch_regs.high_addr_ptr |=
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
+ /* Word count reg takes value as (N +1) words */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = 0;
+ tdc->ch_regs.mc_seq = mc_seq;
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static struct dma_async_tx_descriptor *
+tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long csr, mc_seq, apb_ptr = 0, mmio_seq = 0;
+ enum dma_slave_buswidth slave_bw;
+ struct tegra_dma_desc *dma_desc;
+ struct scatterlist *sg;
+ u32 burst_size;
+ unsigned int i;
+ int ret;
+
+ if (!tdc->config_init) {
+ dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
+ return NULL;
+ }
+ if (sg_len < 1) {
+ dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
+ return NULL;
+ }
+
+ ret = tegra_dma_sid_reserve(tdc, direction);
+ if (ret)
+ return NULL;
+
+ ret = get_transfer_param(tdc, direction, &apb_ptr, &mmio_seq, &csr,
+ &burst_size, &slave_bw);
+ if (ret < 0)
+ return NULL;
+
+ /* Enable once or continuous mode */
+ csr |= TEGRA_GPCDMA_CSR_ONCE;
+ /* Program the slave id in requestor select */
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id);
+ /* Enable IRQ mask */
+ csr |= TEGRA_GPCDMA_CSR_IRQ_MASK;
+ /* Configure default priority weight for the channel*/
+ csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1);
+
+ /* Enable the dma interrupt */
+ if (flags & DMA_PREP_INTERRUPT)
+ csr |= TEGRA_GPCDMA_CSR_IE_EOC;
+
+ mc_seq = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+ /* retain stream-id and clean rest */
+ mc_seq &= TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK;
+
+ /* Set the address wrapping on both MC and MMIO side */
+
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP0,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_WRAP1,
+ TEGRA_GPCDMA_MCSEQ_WRAP_NONE);
+ mmio_seq |= FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1);
+
+ /* Program 2 MC outstanding requests by default. */
+ mc_seq |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_REQ_COUNT, 1);
+
+ /* Setting MC burst size depending on MMIO burst size */
+ if (burst_size == 64)
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_16;
+ else
+ mc_seq |= TEGRA_GPCDMA_MCSEQ_BURST_2;
+
+ dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
+ if (!dma_desc)
+ return NULL;
+
+ dma_desc->bytes_requested = 0;
+ dma_desc->bytes_transferred = 0;
+
+ /* Make transfer requests */
+ for_each_sg(sgl, sg, sg_len, i) {
+ u32 len;
+ dma_addr_t mem;
+
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+
+ if ((len & 3) || (mem & 3) ||
+ len > tdc->tdma->chip_data->max_dma_count) {
+ dev_err(tdc2dev(tdc),
+ "DMA length/memory address is not supported\n");
+ kfree(dma_desc);
+ return NULL;
+ }
+
+ mmio_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
+ dma_desc->bytes_requested += len;
+
+ if (direction == DMA_MEM_TO_DEV) {
+ tdc->ch_regs.src_ptr = mem;
+ tdc->ch_regs.dst_ptr = apb_ptr;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
+ } else if (direction == DMA_DEV_TO_MEM) {
+ tdc->ch_regs.src_ptr = apb_ptr;
+ tdc->ch_regs.dst_ptr = mem;
+ tdc->ch_regs.high_addr_ptr =
+ FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
+ }
+
+ /*
+ * Word count register takes input in words. Writing a value
+ * of N into word count register means a req of (N+1) words.
+ */
+ tdc->ch_regs.wcount = ((len - 4) >> 2);
+ tdc->ch_regs.csr = csr;
+ tdc->ch_regs.mmio_seq = mmio_seq;
+ tdc->ch_regs.mc_seq = mc_seq;
+ tdc->dma_desc = dma_desc;
+ }
+
+ return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags);
+}
+
+static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ dma_cookie_init(&tdc->vc.chan);
+ tdc->config_init = false;
+ return 0;
+}
+
+static void tegra_dma_chan_synchronize(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+
+ vchan_synchronize(&tdc->vc);
+}
+
+static void tegra_dma_free_chan_resources(struct dma_chan *dc)
+{
+ struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
+ unsigned long flags;
+
+ dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
+
+ tegra_dma_terminate_all(dc);
+
+ tegra_dma_chan_synchronize(dc);
+
+ tasklet_kill(&tdc->vc.task);
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ tdc->config_init = false;
+ tdc->slave_id = -1;
+ tdc->sid_dir = DMA_TRANS_NONE;
+
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+}
+
+static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct tegra_dma *tdma = ofdma->of_dma_data;
+ struct tegra_dma_channel *tdc;
+ struct dma_chan *chan;
+
+ chan = dma_get_any_slave_channel(&tdma->dma_dev);
+ if (!chan)
+ return NULL;
+
+ tdc = to_tegra_dma_chan(chan);
+ tdc->slave_id = dma_spec->args[0];
+
+ return chan;
+}
+
+static const struct tegra_dma_chip_data tegra186_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = false,
+};
+
+static const struct tegra_dma_chip_data tegra194_dma_chip_data = {
+ .nr_channels = 32,
+ .channel_reg_size = SZ_64K,
+ .max_dma_count = SZ_1G,
+ .hw_support_pause = true,
+};
+
+static const struct of_device_id tegra_dma_of_match[] = {
+ {
+ .compatible = "nvidia,tegra186-gpcdma",
+ .data = &tegra186_dma_chip_data,
+ }, {
+ .compatible = "nvidia,tegra194-gpcdma",
+ .data = &tegra194_dma_chip_data,
+ }, {
+ },
+};
+MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
+
+static int tegra_dma_program_sid(struct tegra_dma_channel *tdc,
+ int chan, int stream_id)
+{
+ unsigned int reg_val = tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ);
+
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK);
+ reg_val &= ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK);
+
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id);
+ reg_val |= FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id);
+
+ tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val);
+ return 0;
+}
+
+static int tegra_dma_probe(struct platform_device *pdev)
+{
+ const struct tegra_dma_chip_data *cdata = NULL;
+ struct iommu_fwspec *iommu_spec;
+ unsigned int stream_id, i;
+ struct tegra_dma *tdma;
+ struct resource *res;
+ int ret;
+
+ cdata = of_device_get_match_data(&pdev->dev);
+
+ tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *
+ sizeof(struct tegra_dma_channel), GFP_KERNEL);
+ if (!tdma)
+ return -ENOMEM;
+
+ tdma->dev = &pdev->dev;
+ tdma->chip_data = cdata;
+ platform_set_drvdata(pdev, tdma);
+
+ tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(tdma->base_addr))
+ return PTR_ERR(tdma->base_addr);
+
+ tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma");
+ if (IS_ERR(tdma->rst)) {
+ dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),
+ "Missing controller reset\n");
+ return PTR_ERR(tdma->rst);
+ }
+ reset_control_reset(tdma->rst);
+
+ tdma->dma_dev.dev = &pdev->dev;
+
+ iommu_spec = dev_iommu_fwspec_get(&pdev->dev);
+ if (!iommu_spec) {
+ dev_err(&pdev->dev, "Missing iommu stream-id\n");
+ return -EINVAL;
+ }
+ stream_id = iommu_spec->ids[0] & 0xffff;
+
+ INIT_LIST_HEAD(&tdma->dma_dev.channels);
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET +
+ i * cdata->channel_reg_size;
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
+ if (!res) {
+ dev_err(&pdev->dev, "No irq resource for chan %d\n", i);
+ return -EINVAL;
+ }
+ tdc->irq = res->start;
+ snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i);
+
+ tdc->tdma = tdma;
+ tdc->id = i;
+ tdc->slave_id = -1;
+
+ vchan_init(&tdc->vc, &tdma->dma_dev);
+ tdc->vc.desc_free = tegra_dma_desc_free;
+ raw_spin_lock_init(&tdc->lock);
+
+ /* program stream-id for this channel */
+ tegra_dma_program_sid(tdc, i, stream_id);
+ tdc->stream_id = stream_id;
+ }
+
+ dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);
+ dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask);
+
+ /*
+ * Only word aligned transfers are supported. Set the copy
+ * alignment shift.
+ */
+ tdma->dma_dev.copy_align = 2;
+ tdma->dma_dev.fill_align = 2;
+ tdma->dma_dev.device_alloc_chan_resources =
+ tegra_dma_alloc_chan_resources;
+ tdma->dma_dev.device_free_chan_resources =
+ tegra_dma_free_chan_resources;
+ tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
+ tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy;
+ tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset;
+ tdma->dma_dev.device_config = tegra_dma_slave_config;
+ tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
+ tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
+ tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
+ tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize;
+ tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+ /* Register DMA channel interrupt handlers after everything is setup */
+ for (i = 0; i < cdata->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ ret = devm_request_irq(&pdev->dev, tdc->irq,
+ tegra_dma_isr, 0, tdc->name, tdc);
+ if (ret) {
+ dev_err_probe(&pdev->dev, ret,
+ "request_irq failed for channel %d\n", i);
+ return ret;
+ }
+ }
+
+ ret = dma_async_device_register(&tdma->dma_dev);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA driver registration failed\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ tegra_dma_of_xlate, tdma);
+ if (ret < 0) {
+ dev_err_probe(&pdev->dev, ret,
+ "GPC DMA OF registration failed\n");
+
+ dma_async_device_unregister(&tdma->dma_dev);
+ return ret;
+ }
+
+ dev_info(&pdev->dev, "GPC DMA driver register %d channels\n",
+ cdata->nr_channels);
+
+ return 0;
+}
+
+static int tegra_dma_remove(struct platform_device *pdev)
+{
+ struct tegra_dma *tdma = platform_get_drvdata(pdev);
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&tdma->dma_dev);
+
+ return 0;
+}
+
+/*
+ * Save and restore csr and channel register on pm_suspend
+ * and pm_resume respectively
+ */
+static int __maybe_unused tegra_dma_pm_suspend(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned long flags;
+ unsigned int i;
+ bool busy;
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ raw_spin_lock_irqsave(&tdc->lock, flags);
+ busy = tdc->busy;
+ raw_spin_unlock_irqrestore(&tdc->lock, flags);
+
+ if (busy) {
+ dev_err(tdma->dev, "channel %u busy\n", i);
+ return -EBUSY;
+ }
+ }
+
+ return 0;
+}
+
+static int __maybe_unused tegra_dma_pm_resume(struct device *dev)
+{
+ struct tegra_dma *tdma = dev_get_drvdata(dev);
+ unsigned int i;
+
+ reset_control_reset(tdma->rst);
+
+ for (i = 0; i < tdma->chip_data->nr_channels; i++) {
+ struct tegra_dma_channel *tdc = &tdma->channels[i];
+
+ tegra_dma_program_sid(tdc, i, tdc->stream_id);
+ }
+
+ return 0;
+}
+
+static const struct __maybe_unused dev_pm_ops tegra_dma_dev_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(tegra_dma_pm_suspend, tegra_dma_pm_resume)
+};
+
+static struct platform_driver tegra_dmac_driver = {
+ .driver = {
+ .name = "tegra-gpcdma",
+ .owner = THIS_MODULE,
+ .pm = &tegra_dma_dev_pm_ops,
+ .of_match_table = tegra_dma_of_match,
+ },
+ .probe = tegra_dma_probe,
+ .remove = tegra_dma_remove,
+};
+
+module_platform_driver(tegra_dmac_driver);
+
+MODULE_ALIAS("platform:tegra-gpc-dma");
+MODULE_DESCRIPTION("NVIDIA Tegra GPC DMA Controller driver");
+MODULE_AUTHOR("Pavan Kunapuli <pkunapuli@nvidia.com>");
+MODULE_AUTHOR("Rajesh Gumasta <rgumasta@nvidia.com>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v12 3/4] arm64: defconfig: tegra: Enable GPCDMA
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-11-09 14:35 ` [PATCH v12 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-11-09 14:35 ` [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-11-09 14:35 ` Akhil R
2021-11-09 14:35 ` [PATCH v12 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
3 siblings, 0 replies; 21+ messages in thread
From: Akhil R @ 2021-11-09 14:35 UTC (permalink / raw)
To: akhilrajeev
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul
Enable TEGRA_GPC_DMA in defconfig for Tegra186 and Tegra196 gpc
dma controller driver
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 156d96a..6616148 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -928,6 +928,7 @@ CONFIG_MV_XOR=y
CONFIG_MV_XOR_V2=y
CONFIG_OWL_DMA=y
CONFIG_PL330_DMA=y
+CONFIG_TEGRA186_GPC_DMA=m
CONFIG_TEGRA20_APB_DMA=y
CONFIG_TEGRA210_ADMA=m
CONFIG_QCOM_BAM_DMA=y
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v12 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
` (2 preceding siblings ...)
2021-11-09 14:35 ` [PATCH v12 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
@ 2021-11-09 14:35 ` Akhil R
3 siblings, 0 replies; 21+ messages in thread
From: Akhil R @ 2021-11-09 14:35 UTC (permalink / raw)
To: akhilrajeev
Cc: dan.j.williams, devicetree, dmaengine, jonathanh, kyarlagadda,
ldewangan, linux-kernel, linux-tegra, p.zabel, rgumasta, robh+dt,
thierry.reding, vkoul
Add device tree node for GPCDMA controller on Tegra186 target
and Tegra194 target.
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 44 ++++++++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 44 ++++++++++++++++++++++++++
4 files changed, 96 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
index fcd71bf..f5ef04d3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi
@@ -56,6 +56,10 @@
};
};
+ dma-controller@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index e94f8ad..355d53c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -73,6 +73,50 @@
snps,rxpbl = <8>;
};
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra186-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA186_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA186_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra186-aconnect",
"nvidia,tegra210-aconnect";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index c4058ee..5bc74af 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -49,6 +49,10 @@
};
};
+ dma-controller@2600000 {
+ status = "okay";
+ };
+
memory-controller@2c00000 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c8250a3..94094f3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -72,6 +72,50 @@
snps,rxpbl = <8>;
};
+ dma-controller@2600000 {
+ compatible = "nvidia,tegra194-gpcdma";
+ reg = <0x2600000 0x210000>;
+ resets = <&bpmp TEGRA194_RESET_GPCDMA>;
+ reset-names = "gpcdma";
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ iommus = <&smmu TEGRA194_SID_GPCDMA_0>;
+ dma-coherent;
+ status = "disabled";
+ };
+
aconnect@2900000 {
compatible = "nvidia,tegra194-aconnect",
"nvidia,tegra210-aconnect";
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-11-09 14:35 ` [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-11-12 19:10 ` kernel test robot
2021-11-17 17:39 ` kernel test robot
1 sibling, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-11-12 19:10 UTC (permalink / raw)
To: Akhil R
Cc: kbuild-all, dan.j.williams, devicetree, dmaengine, jonathanh,
kyarlagadda, ldewangan, linux-kernel, linux-tegra, p.zabel
[-- Attachment #1: Type: text/plain, Size: 4943 bytes --]
Hi Akhil,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on vkoul-dmaengine/next arm64/for-next/core v5.15 next-20211112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: m68k-allyesconfig (attached as .config)
compiler: m68k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
git checkout faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=m68k
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Werror=switch]
326 | switch (tdc->sid_dir) {
| ^~~~~~
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Werror=switch]
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Werror=switch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_reset_client':
>> drivers/dma/tegra186-gpc-dma.c:55:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
55 | FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
| ^~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c:535:16: note: in expansion of macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
535 | csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:787:74: error: right shift count >= width of type [-Werror=shift-count-overflow]
787 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:854:65: error: right shift count >= width of type [-Werror=shift-count-overflow]
854 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:856:66: error: right shift count >= width of type [-Werror=shift-count-overflow]
856 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:962:81: error: right shift count >= width of type [-Werror=shift-count-overflow]
962 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:967:81: error: right shift count >= width of type [-Werror=shift-count-overflow]
967 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
| ^~
cc1: all warnings being treated as errors
vim +/DMA_MEM_TO_MEM +326 drivers/dma/tegra186-gpc-dma.c
320
321 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
322 {
323 struct tegra_dma *tdma = tdc->tdma;
324 unsigned int sid = tdc->slave_id;
325
> 326 switch (tdc->sid_dir) {
327 case DMA_MEM_TO_DEV:
328 clear_bit(sid, &tdma->sid_m2d_reserved);
329 break;
330 case DMA_DEV_TO_MEM:
331 clear_bit(sid, &tdma->sid_d2m_reserved);
332 break;
333 }
334
335 tdc->sid_dir = DMA_TRANS_NONE;
336 }
337
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 61588 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver
@ 2021-11-12 19:10 ` kernel test robot
0 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-11-12 19:10 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 5032 bytes --]
Hi Akhil,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on vkoul-dmaengine/next arm64/for-next/core v5.15 next-20211112]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: m68k-allyesconfig (attached as .config)
compiler: m68k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
git checkout faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=m68k
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Werror=switch]
326 | switch (tdc->sid_dir) {
| ^~~~~~
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Werror=switch]
>> drivers/dma/tegra186-gpc-dma.c:326:9: error: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Werror=switch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_reset_client':
>> drivers/dma/tegra186-gpc-dma.c:55:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
55 | FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
| ^~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c:535:16: note: in expansion of macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
535 | csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:787:74: error: right shift count >= width of type [-Werror=shift-count-overflow]
787 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:854:65: error: right shift count >= width of type [-Werror=shift-count-overflow]
854 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:856:66: error: right shift count >= width of type [-Werror=shift-count-overflow]
856 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:962:81: error: right shift count >= width of type [-Werror=shift-count-overflow]
962 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));
| ^~
drivers/dma/tegra186-gpc-dma.c:967:81: error: right shift count >= width of type [-Werror=shift-count-overflow]
967 | FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));
| ^~
cc1: all warnings being treated as errors
vim +/DMA_MEM_TO_MEM +326 drivers/dma/tegra186-gpc-dma.c
320
321 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
322 {
323 struct tegra_dma *tdma = tdc->tdma;
324 unsigned int sid = tdc->slave_id;
325
> 326 switch (tdc->sid_dir) {
327 case DMA_MEM_TO_DEV:
328 clear_bit(sid, &tdma->sid_m2d_reserved);
329 break;
330 case DMA_DEV_TO_MEM:
331 clear_bit(sid, &tdma->sid_d2m_reserved);
332 break;
333 }
334
335 tdc->sid_dir = DMA_TRANS_NONE;
336 }
337
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 61588 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver
2021-11-09 14:35 ` [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
@ 2021-11-17 17:39 ` kernel test robot
2021-11-17 17:39 ` kernel test robot
1 sibling, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-11-17 17:39 UTC (permalink / raw)
To: Akhil R
Cc: kbuild-all, dan.j.williams, devicetree, dmaengine, jonathanh,
kyarlagadda, ldewangan, linux-kernel, linux-tegra, p.zabel
[-- Attachment #1: Type: text/plain, Size: 5069 bytes --]
Hi Akhil,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on vkoul-dmaengine/next arm64/for-next/core v5.16-rc1 next-20211117]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: sparc64-randconfig-p002-20211115 (attached as .config)
compiler: sparc64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
git checkout faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=sparc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
326 | switch (tdc->sid_dir) {
| ^~~~~~
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_desc_free':
>> drivers/dma/tegra186-gpc-dma.c:340:9: error: implicit declaration of function 'kfree'; did you mean 'kvfree'? [-Werror=implicit-function-declaration]
340 | kfree(container_of(vd, struct tegra_dma_desc, vd));
| ^~~~~
| kvfree
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_reset_client':
drivers/dma/tegra186-gpc-dma.c:55:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
55 | FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
| ^~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c:535:16: note: in expansion of macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
535 | csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:776:20: error: implicit declaration of function 'kzalloc'; did you mean 'kvzalloc'? [-Werror=implicit-function-declaration]
776 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^~~~~~~
| kvzalloc
>> drivers/dma/tegra186-gpc-dma.c:776:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
776 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:843:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
843 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:932:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
932 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
cc1: some warnings being treated as errors
vim +340 drivers/dma/tegra186-gpc-dma.c
320
321 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
322 {
323 struct tegra_dma *tdma = tdc->tdma;
324 unsigned int sid = tdc->slave_id;
325
> 326 switch (tdc->sid_dir) {
327 case DMA_MEM_TO_DEV:
328 clear_bit(sid, &tdma->sid_m2d_reserved);
329 break;
330 case DMA_DEV_TO_MEM:
331 clear_bit(sid, &tdma->sid_d2m_reserved);
332 break;
333 }
334
335 tdc->sid_dir = DMA_TRANS_NONE;
336 }
337
338 static void tegra_dma_desc_free(struct virt_dma_desc *vd)
339 {
> 340 kfree(container_of(vd, struct tegra_dma_desc, vd));
341 }
342
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 37084 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver
@ 2021-11-17 17:39 ` kernel test robot
0 siblings, 0 replies; 21+ messages in thread
From: kernel test robot @ 2021-11-17 17:39 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 5166 bytes --]
Hi Akhil,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on vkoul-dmaengine/next arm64/for-next/core v5.16-rc1 next-20211117]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: sparc64-randconfig-p002-20211115 (attached as .config)
compiler: sparc64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Akhil-R/dt-bindings-dmaengine-Add-doc-for-tegra-gpcdma/20211109-233646
git checkout faf61a8fc90e3ea731c65a8cebce3eb6c0444d21
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=sparc64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_sid_free':
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_MEM_TO_MEM' not handled in switch [-Wswitch]
326 | switch (tdc->sid_dir) {
| ^~~~~~
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_DEV_TO_DEV' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c:326:9: warning: enumeration value 'DMA_TRANS_NONE' not handled in switch [-Wswitch]
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_desc_free':
>> drivers/dma/tegra186-gpc-dma.c:340:9: error: implicit declaration of function 'kfree'; did you mean 'kvfree'? [-Werror=implicit-function-declaration]
340 | kfree(container_of(vd, struct tegra_dma_desc, vd));
| ^~~~~
| kvfree
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_reset_client':
drivers/dma/tegra186-gpc-dma.c:55:41: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
55 | FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, 4)
| ^~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c:535:16: note: in expansion of macro 'TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED'
535 | csr |= TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memset':
>> drivers/dma/tegra186-gpc-dma.c:776:20: error: implicit declaration of function 'kzalloc'; did you mean 'kvzalloc'? [-Werror=implicit-function-declaration]
776 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^~~~~~~
| kvzalloc
>> drivers/dma/tegra186-gpc-dma.c:776:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
776 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_dma_memcpy':
drivers/dma/tegra186-gpc-dma.c:843:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
843 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
drivers/dma/tegra186-gpc-dma.c: In function 'tegra_dma_prep_slave_sg':
drivers/dma/tegra186-gpc-dma.c:932:18: warning: assignment to 'struct tegra_dma_desc *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
932 | dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
| ^
cc1: some warnings being treated as errors
vim +340 drivers/dma/tegra186-gpc-dma.c
320
321 static void tegra_dma_sid_free(struct tegra_dma_channel *tdc)
322 {
323 struct tegra_dma *tdma = tdc->tdma;
324 unsigned int sid = tdc->slave_id;
325
> 326 switch (tdc->sid_dir) {
327 case DMA_MEM_TO_DEV:
328 clear_bit(sid, &tdma->sid_m2d_reserved);
329 break;
330 case DMA_DEV_TO_MEM:
331 clear_bit(sid, &tdma->sid_d2m_reserved);
332 break;
333 }
334
335 tdc->sid_dir = DMA_TRANS_NONE;
336 }
337
338 static void tegra_dma_desc_free(struct virt_dma_desc *vd)
339 {
> 340 kfree(container_of(vd, struct tegra_dma_desc, vd));
341 }
342
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 37084 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma
2021-11-03 10:34 ` Akhil R
@ 2021-11-18 23:35 ` Rob Herring
0 siblings, 0 replies; 21+ messages in thread
From: Rob Herring @ 2021-11-18 23:35 UTC (permalink / raw)
To: Akhil R
Cc: dan.j.williams, devicetree, dmaengine, Jonathan Hunter,
Krishna Yarlagadda, Laxman Dewangan, linux-kernel, linux-tegra,
p.zabel, Rajesh Gumasta, thierry.reding, vkoul
On Wed, Nov 3, 2021 at 5:34 AM Akhil R <akhilrajeev@nvidia.com> wrote:
>
> > On Thu, Oct 28, 2021 at 06:53:36PM +0530, Akhil R wrote:
> > > Add DT binding document for Nvidia Tegra GPCDMA controller.
> > >
> > > Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
> > > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> > > Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
> > > ---
> > > .../bindings/dma/nvidia,tegra186-gpc-dma.yaml | 115
> > +++++++++++++++++++++
> > > 1 file changed, 115 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> > > b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml
> > > new file mode 100644
> > > index 0000000..bc97efc
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.ya
> > > +++ ml
> > > @@ -0,0 +1,115 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/dma/nvidia,tegra186-gpc-dma.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NVIDIA Tegra GPC DMA Controller Device Tree Bindings
> > > +
> > > +description: |
> > > + The Tegra General Purpose Central (GPC) DMA controller is used for
> > > +faster
> > > + data transfers between memory to memory, memory to device and
> > > +device to
> > > + memory.
> > > +
> > > +maintainers:
> > > + - Jon Hunter <jonathanh@nvidia.com>
> > > + - Rajesh Gumasta <rgumasta@nvidia.com>
> > > +
> > > +allOf:
> > > + - $ref: "dma-controller.yaml#"
> > > +
> > > +properties:
> > > + compatible:
> > > + oneOf:
> > > + - enum:
> > > + - nvidia,tegra186-gpcdma
> > > + - nvidia,tegra194-gpcdma
> > > + - items:
> > > + - const: nvidia,tegra186-gpcdma
> > > + - const: nvidia,tegra194-gpcdma
> >
> > One of these is wrong. Either 186 has a fallback to 194 or it doesn't.
> Not sure if I understood this correctly. Tegra186 and 194 have different chip data
> inside driver based on the compatible. I guess, it then needs to be one of these.
> Or is the mistake something related to formatting?
It's not about what the driver uses, but what is valid in a DT file.
Either you say the 2 implementations are different and in no way
compatible with each other:
enum:
- nvidia,tegra186-gpcdma
- nvidia,tegra194-gpcdma
Or you say 186 is backwards compatible with 194 (meaning 186 is a
superset of 194 so a driver written for 194 still works on 186 (though
not any new features)).
oneOf:
- const: nvidia,tegra194-gpcdma
- items:
- const: nvidia,tegra186-gpcdma
- const: nvidia,tegra194-gpcdma
Rob
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-11-18 23:35 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-28 13:23 [PATCH v11 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-10-28 13:23 ` [PATCH v11 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-11-02 13:20 ` Rob Herring
2021-11-03 10:34 ` Akhil R
2021-11-18 23:35 ` Rob Herring
2021-10-28 13:23 ` [PATCH v11 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2021-10-29 2:00 ` kernel test robot
2021-10-29 2:00 ` kernel test robot
2021-10-29 14:27 ` kernel test robot
2021-10-29 14:27 ` kernel test robot
2021-10-28 13:23 ` [PATCH v11 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-10-28 13:23 ` [PATCH v11 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
2021-11-09 14:35 ` [PATCH v12 0/4] Add NVIDIA Tegra GPC-DMA driver Akhil R
2021-11-09 14:35 ` [PATCH v12 1/4] dt-bindings: dmaengine: Add doc for tegra gpcdma Akhil R
2021-11-09 14:35 ` [PATCH v12 2/4] dmaengine: tegra: Add tegra gpcdma driver Akhil R
2021-11-12 19:10 ` kernel test robot
2021-11-12 19:10 ` kernel test robot
2021-11-17 17:39 ` kernel test robot
2021-11-17 17:39 ` kernel test robot
2021-11-09 14:35 ` [PATCH v12 3/4] arm64: defconfig: tegra: Enable GPCDMA Akhil R
2021-11-09 14:35 ` [PATCH v12 4/4] arm64: tegra: Add GPCDMA node for tegra186 and tegra194 Akhil R
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