From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BF9BC433EF for ; Wed, 16 Mar 2022 15:13:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1356988AbiCPPPF (ORCPT ); Wed, 16 Mar 2022 11:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357975AbiCPPOL (ORCPT ); Wed, 16 Mar 2022 11:14:11 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 462066C1D6; Wed, 16 Mar 2022 08:12:06 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 100031515; Wed, 16 Mar 2022 08:11:58 -0700 (PDT) Received: from [10.57.6.128] (unknown [10.57.6.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1FB673F7D7; Wed, 16 Mar 2022 08:11:54 -0700 (PDT) Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used To: Leo Yan , Ali Saidi Cc: acme@kernel.org, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, benh@kernel.crashing.org, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org, yao.jin@linux.intel.com, Nick.Forrington@arm.com References: <20220314183721.3198-1-alisaidi@amazon.com> <172ce478-b539-2aa4-0470-1b96c6b8169b@arm.com> <7b3aaa4d-5194-a729-f8ad-d55ada7fa58f@arm.com> <20220316124208.GA310478@leoy-ThinkPad-X240s> From: German Gomez Message-ID: <1637567b-42df-57d5-2987-939ffbf451ef@arm.com> Date: Wed, 16 Mar 2022 15:10:55 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20220316124208.GA310478@leoy-ThinkPad-X240s> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/03/2022 12:42, Leo Yan wrote: > On Wed, Mar 16, 2022 at 11:43:52AM +0000, German Gomez wrote: > > [...] > >>>>> I had a look at the TRMs for the N1[1], V1[2] and N2[3] Neoverse cores >>>>> (specifically the LL_CACHE_RD pmu events). If we were to assign a number >>>>> to the system cache (assuming all caches are implemented): >>>>> >>>>> *For N1*, if L2 and L3 are implemented, system cache would follow at *L4* >>>> To date no one has built 4 level though. Everyone has only built three. >>> The N1SDP board advertises 4 levels (we use it regularly for testing perf patches) >> That said, it's probably the odd one out. >> >> I'm not against assuming 3 levels. Later if there's is a strong need for L4, indeed we can go back and change it. > Thanks for the info. > > For exploring cache hierarchy via sysFS is a good idea, the only one > concern for me is: can we simply take the system cache as the same > thing as the highest level cache? If so, I think another option is to For Neoverse, it should be. LL_CACHE_RD pmu event says (if system cache is implemented): * If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'interconnect cache'. > define a cache level as "PERF_MEM_LVLNUM_SYSTEM_CACHE" and extend the > decoding code for support it. > > With PERF_MEM_LVLNUM_SYSTEM_CACHE, it can tell users clearly the data > source from system cache, and users can easily map this info with the > cache media on the working platform. > > In practice, I don't object to use cache level 3 at first step. At > least this can meet the requirement at current stage. Ok, I agree. I think for now it is a good compromise. Detecting the caches seems like an additional/separate perf feature. Thanks, German > Thanks, > Leo From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A806C433EF for ; Wed, 16 Mar 2022 15:14:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=J5D1vez8wcN2PGi5e+X3pL35Q48xLr+ne2tSY7HXmzs=; b=PXYJ3ks1EzhOUCTj+0ynLRzKir hVqWs1umyAOQ2KqyPGC+2OoHOMlxhqBvewO+p5cFozChuOHzKLxiMv5+sn3qirLAXwAaH7ou0/etH wxFn7/uVCKjw3ms29cAV3MNbbWQXmfMPc8SI5TSgFywuimoDNbC5B2vYYq1r9IEU28Ec+7T98QL07 fTPopoCJ9SJSokjhQbiFwydi1Oa1ZsaJ5ILZO9VSGE4eNTTYGZdg07Q1wwCUbNwbDynGhGpAPwEtn B9lYvKnWi7LQQ9K4tEI4BjCYOHrd3RavA2JFetFr/Zt/P9UhThMEIEUJKKZQEHuCaBngDWXydxS9m 4KxJgKow==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUVKS-00DRt9-Oi; Wed, 16 Mar 2022 15:12:49 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUVJf-00DRcf-6A for linux-arm-kernel@lists.infradead.org; Wed, 16 Mar 2022 15:12:00 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 100031515; Wed, 16 Mar 2022 08:11:58 -0700 (PDT) Received: from [10.57.6.128] (unknown [10.57.6.128]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1FB673F7D7; Wed, 16 Mar 2022 08:11:54 -0700 (PDT) Subject: Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used To: Leo Yan , Ali Saidi Cc: acme@kernel.org, alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com, benh@kernel.crashing.org, james.clark@arm.com, john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com, lihuafei1@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, mark.rutland@arm.com, mathieu.poirier@linaro.org, mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org, will@kernel.org, yao.jin@linux.intel.com, Nick.Forrington@arm.com References: <20220314183721.3198-1-alisaidi@amazon.com> <172ce478-b539-2aa4-0470-1b96c6b8169b@arm.com> <7b3aaa4d-5194-a729-f8ad-d55ada7fa58f@arm.com> <20220316124208.GA310478@leoy-ThinkPad-X240s> From: German Gomez Message-ID: <1637567b-42df-57d5-2987-939ffbf451ef@arm.com> Date: Wed, 16 Mar 2022 15:10:55 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20220316124208.GA310478@leoy-ThinkPad-X240s> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220316_081159_340192_355DEF19 X-CRM114-Status: GOOD ( 19.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 16/03/2022 12:42, Leo Yan wrote: > On Wed, Mar 16, 2022 at 11:43:52AM +0000, German Gomez wrote: > > [...] > >>>>> I had a look at the TRMs for the N1[1], V1[2] and N2[3] Neoverse cores >>>>> (specifically the LL_CACHE_RD pmu events). If we were to assign a number >>>>> to the system cache (assuming all caches are implemented): >>>>> >>>>> *For N1*, if L2 and L3 are implemented, system cache would follow at *L4* >>>> To date no one has built 4 level though. Everyone has only built three. >>> The N1SDP board advertises 4 levels (we use it regularly for testing perf patches) >> That said, it's probably the odd one out. >> >> I'm not against assuming 3 levels. Later if there's is a strong need for L4, indeed we can go back and change it. > Thanks for the info. > > For exploring cache hierarchy via sysFS is a good idea, the only one > concern for me is: can we simply take the system cache as the same > thing as the highest level cache? If so, I think another option is to For Neoverse, it should be. LL_CACHE_RD pmu event says (if system cache is implemented): * If CPUECTLR.EXTLLC is set: This event counts any cacheable read transaction which returns a data source of 'interconnect cache'. > define a cache level as "PERF_MEM_LVLNUM_SYSTEM_CACHE" and extend the > decoding code for support it. > > With PERF_MEM_LVLNUM_SYSTEM_CACHE, it can tell users clearly the data > source from system cache, and users can easily map this info with the > cache media on the working platform. > > In practice, I don't object to use cache level 3 at first step. At > least this can meet the requirement at current stage. Ok, I agree. I think for now it is a good compromise. Detecting the caches seems like an additional/separate perf feature. Thanks, German > Thanks, > Leo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel