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From: Xiaojuan Yang <yangxiaojuan@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com,
	chenhuacai@loongson.cn, philmd@redhat.com, i.qemu@xen0n.name,
	mark.cave-ayland@ilande.co.uk, laurent@vivier.eu,
	peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn,
	alistair.francis@wdc.com, maobibo@loongson.cn,
	pbonzini@redhat.com, richard.henderson@linaro.org,
	alex.bennee@linaro.org, gaosong@loongson.cn
Subject: [RFC PATCH v3 12/27] target/loongarch: Add timer related instructions support.
Date: Sat,  4 Dec 2021 20:07:10 +0800	[thread overview]
Message-ID: <1638619645-11283-13-git-send-email-yangxiaojuan@loongson.cn> (raw)
In-Reply-To: <1638619645-11283-1-git-send-email-yangxiaojuan@loongson.cn>

This includes:
-RDTIME{L/H}.W
-RDTIME.D

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
 target/loongarch/helper.h                     |  1 +
 target/loongarch/insn_trans/trans_extra.c.inc | 32 +++++++++++++++++++
 target/loongarch/translate.c                  |  2 ++
 3 files changed, 35 insertions(+)

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index c916f2650b..035bd141ed 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -116,4 +116,5 @@ DEF_HELPER_4(lddir, tl, env, tl, tl, i32)
 DEF_HELPER_4(ldpte, void, env, tl, tl, i32)
 DEF_HELPER_1(ertn, void, env)
 DEF_HELPER_1(idle, void, env)
+DEF_HELPER_1(rdtime_d, i64, env)
 #endif /* !CONFIG_USER_ONLY */
diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
index 2ce95d3382..8d3425ba61 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -33,22 +33,54 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)
     return true;
 }
 
+#ifndef CONFIG_USER_ONLY
+static bool gen_rdtime(DisasContext *ctx, arg_rr *a,
+                       bool word, bool high)
+{
+    TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE);
+    TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE);
+
+    if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+        gen_io_start();
+    }
+    gen_helper_rdtime_d(dst1, cpu_env);
+    if (word) {
+        tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32);
+    }
+    tcg_gen_ld_i64(dst2, cpu_env, offsetof(CPULoongArchState, CSR_TID));
+
+    return true;
+}
+#endif
+
 static bool trans_rdtimel_w(DisasContext *ctx, arg_rdtimel_w *a)
 {
+#ifdef CONFIG_USER_ONLY
     tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
     return true;
+#else
+    return gen_rdtime(ctx, a, 1, 0);
+#endif
 }
 
 static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a)
 {
+#ifdef CONFIG_USER_ONLY
     tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
     return true;
+#else
+    return gen_rdtime(ctx, a, 1, 1);
+#endif
 }
 
 static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a)
 {
+#ifdef CONFIG_USER_ONLY
     tcg_gen_movi_tl(cpu_gpr[a->rd], 0);
     return true;
+#else
+    return gen_rdtime(ctx, a, 0, 0);
+#endif
 }
 
 static bool trans_cpucfg(DisasContext *ctx, arg_cpucfg *a)
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index ddb97661fa..53a5ef3aa9 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -25,6 +25,8 @@ static TCGv cpu_lladdr, cpu_llval;
 TCGv_i32 cpu_fcsr0;
 TCGv_i64 cpu_fpr[32];
 
+#include "exec/gen-icount.h"
+
 #define DISAS_STOP       DISAS_TARGET_0
 #define DISAS_EXIT       DISAS_TARGET_1
 
-- 
2.27.0



  parent reply	other threads:[~2021-12-04 12:14 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-04 12:06 [RFC PATCH v3 00/27] Add LoongArch softmmu support Xiaojuan Yang
2021-12-04 12:06 ` [RFC PATCH v3 01/27] target/loongarch: Update README Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 02/27] target/loongarch: Add CSR registers definition Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 03/27] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 04/27] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 05/27] target/loongarch: Add stabletimer support Xiaojuan Yang
2021-12-06  4:38   ` chen huacai
2021-12-07  7:04     ` maobibo
2021-12-04 12:07 ` [RFC PATCH v3 06/27] target/loongarch: Add MMU support for LoongArch CPU Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 07/27] target/loongarch: Add LoongArch CSR instruction Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 08/27] target/loongarch: Add LoongArch IOCSR instruction Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 09/27] target/loongarch: Add TLB instruction support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 10/27] target/loongarch: Add other core instructions support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 11/27] target/loongarch: Add LoongArch interrupt and exception handle Xiaojuan Yang
2021-12-04 12:07 ` Xiaojuan Yang [this message]
2021-12-04 12:07 ` [RFC PATCH v3 13/27] target/loongarch: Add gdb support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 14/27] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson3 Platform Xiaojuan Yang
2021-12-17 23:39   ` Mark Cave-Ayland
2021-12-20 11:42     ` yangxiaojuan
2021-12-04 12:07 ` [RFC PATCH v3 15/27] hw/loongarch: Add support loongson3-ls7a machine type Xiaojuan Yang
2021-12-06  4:36   ` chen huacai
2021-12-06  6:57     ` yangxiaojuan
2021-12-17 23:48   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 16/27] hw/loongarch: Add LoongArch cpu interrupt support(CPUINTC) Xiaojuan Yang
2021-12-17 23:54   ` Mark Cave-Ayland
2021-12-21  3:43     ` yangxiaojuan
2021-12-04 12:07 ` [RFC PATCH v3 17/27] hw/loongarch: Add LoongArch ipi interrupt support(IPI) Xiaojuan Yang
2021-12-18  0:09   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 18/27] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2021-12-18  0:33   ` Mark Cave-Ayland
2021-12-22  2:38     ` yangxiaojuan
2021-12-23 10:21       ` Mark Cave-Ayland
2022-01-08  9:44         ` yangxiaojuan
2021-12-04 12:07 ` [RFC PATCH v3 19/27] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2021-12-18  0:36   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 20/27] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2021-12-18  0:50   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 21/27] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2021-12-18  9:45   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 22/27] hw/loongarch: Add some devices support for 3A5000 Xiaojuan Yang
2021-12-04 17:54   ` Philippe Mathieu-Daudé
2021-12-06  6:55     ` yangxiaojuan
2021-12-18 10:02   ` Mark Cave-Ayland
2021-12-22  8:26     ` yangxiaojuan
2021-12-23 10:52       ` Mark Cave-Ayland
2022-01-10  2:26         ` yangxiaojuan
2022-01-15 14:03           ` Mark Cave-Ayland
2022-01-12  9:37         ` maobibo
2022-01-15 14:05           ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 23/27] hw/loongarch: Add LoongArch ls7a rtc device support Xiaojuan Yang
2021-12-18 10:10   ` Mark Cave-Ayland
2021-12-04 12:07 ` [RFC PATCH v3 24/27] hw/loongarch: Add default bios startup support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 25/27] hw/loongarch: Add -kernel and -initrd options support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 26/27] hw/loongarch: Add LoongArch smbios support Xiaojuan Yang
2021-12-04 12:07 ` [RFC PATCH v3 27/27] hw/loongarch: Add LoongArch acpi support Xiaojuan Yang
2021-12-13  3:13 ` [RFC PATCH v3 00/27] Add LoongArch softmmu support yangxiaojuan
2021-12-13 22:43   ` Mark Cave-Ayland
2021-12-14  1:08     ` yangxiaojuan

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