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Tue, 11 Jan 2022 18:46:09 +0000 From: Ashish Mhetre To: , , , , , CC: , Subject: [Patch V1 4/4] memory: tegra: add mc-err support for T194 Date: Wed, 12 Jan 2022 00:15:50 +0530 Message-ID: <1641926750-27544-5-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> References: <1641926750-27544-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68804713-fa48-42ff-c8c2-08d9d532a3b4 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0187:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:168; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RynJXY3uWiIOsAWZy+Evsz0FMvpwfjfimq8zng7LdPxVaas4P3ZLlbpD+VDA2DMV+OuGaT6r/czNuFwPDXoHeJ/SGRjsIe0kG6uyXLraHSrftCZIF3Ziu1y5/vOjnAVRo2XtmnqwWWAyxYlqgbPiLw5wOlEXffEg0CIDsqgWYSoSFybKtmoND0w6ol8nqzmv1jp58hglKmzvuduTy0XfUwkbKYHthhEhbX4L88jt/d+N0BlezMPLQHhlss2Kf3zcRbN62NUnABVsmIg5q5x7zDMNAThTH6SRXvieLsSytXmgHjPsb96T1/0DTdxCQFwHKsj3reSBPiLPdqQt+qWXrlCfLPBABcftNf8nPzoaMSPcwrFlQyN2n4GfsSl6NJBATTBIFlcZm8mNOWR452bSU4NfWyEOUKVcIPmarFofPuWnoUJzgD3XFWcI8GP28Tisrr9MIWKcBpIZ3YDvHbYo1W1qqEK4nrzVTW4AAa2tVkHk24m58PxELcu9j2++GovD3k8ZjLOVZsDbH1HSeULZp4g7U49LWhegX7ikegMMEwOykPOF7bSXK/3TTUy0C5JoTbzNSfc56V2g2ituHkPOqlJIXKTvUVS+1lhd6YfASAEVR5+ZcB5uFu4nTUbyi0looSPbfMUrzIRT2hNP6R6YMcuaW0GEbhGBjjBML9JRAEjtI/L96fUFcJOYet2g3lVVsaw2d0AkgmDAiu26nvo4HwW8wo6c6EFK69TFNyQyJQPyfFeQFcgNYEttuYw4vTNI+Ypka61wXM370REyNzgXiwY/cVug66mtjcmA+STA6Dg= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(4636009)(40470700002)(46966006)(36840700001)(426003)(5660300002)(26005)(86362001)(36756003)(82310400004)(7696005)(36860700001)(70586007)(316002)(110136005)(4326008)(107886003)(508600001)(40460700001)(356005)(6666004)(70206006)(81166007)(186003)(8936002)(8676002)(54906003)(2616005)(47076005)(2906002)(83380400001)(336012)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2022 18:46:11.9844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68804713-fa48-42ff-c8c2-08d9d532a3b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0187 Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add all basic mc-errors supported by T194. Implement mc interrupt handling routine for T194. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.h | 2 + drivers/memory/tegra/tegra194.c | 108 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 7817492..1d881e7 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -43,6 +43,7 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc +#define MC_ERR_ADR_HI 0x11fc #define MC_ERR_VPR_STATUS 0x654 #define MC_ERR_VPR_ADR 0x658 @@ -50,6 +51,7 @@ #define MC_ERR_SEC_ADR 0x680 #define MC_ERR_MTS_STATUS 0x9b0 #define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1 0xbfc #define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 #define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra194.c index 76ba3da..a0af6a0 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -4,6 +4,7 @@ */ #include +#include #include @@ -16,8 +17,114 @@ static void tegra194_mc_clear_interrupt(struct tegra_mc *mc) mc_writel(mc, MC_INTSTATUS_CLEAR, MC_INTSTATUS); } +static const struct tegra_mc_error int_mc_errors[] = { + { + .int_bit = MC_INT_DECERR_EMEM, + .msg = "EMEM address decode error", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + .addr_reg_hi = MC_ERR_ADR_HI, + }, + { + .int_bit = MC_INT_SECURITY_VIOLATION, + .msg = "non secure access to secure region", + .status_reg = MC_ERR_STATUS, + .addr_reg = MC_ERR_ADR, + .addr_reg_hi = MC_ERR_ADR_HI, + }, + { + .int_bit = MC_INT_DECERR_VPR, + .msg = "MC request violates VPR requirements", + .status_reg = MC_ERR_VPR_STATUS, + .addr_reg = MC_ERR_VPR_ADR, + }, + { + .int_bit = MC_INT_SECERR_SEC, + .msg = "MC request violated SEC carveout requirements", + .status_reg = MC_ERR_SEC_STATUS, + .addr_reg = MC_ERR_SEC_ADR, + }, + { + .int_bit = MC_INT_DECERR_MTS, + .msg = "MTS carveout access violation", + .status_reg = MC_ERR_MTS_STATUS, + .addr_reg = MC_ERR_MTS_ADR, + }, + { + .int_bit = MC_INT_DECERR_GENERALIZED_CARVEOUT, + .msg = "GSC access violation", + .status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS, + .addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR, + .addr_reg_hi = MC_ERR_GENERALIZED_CARVEOUT_STATUS_1, + }, +}; + +static irqreturn_t tegra194_mc_handle_irq(int irq, void *data) +{ + struct tegra_mc *mc = data; + unsigned long status; + unsigned int bit; + + status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + if (!status) + return IRQ_NONE; + + for_each_set_bit(bit, &status, 32) { + const char *error = int_mc_errors[bit].msg ?: "unknown"; + const char *client = "unknown"; + const char *direction, *secure; + phys_addr_t addr = 0; + unsigned int i; + u8 id; + u32 value; + + value = mc_readl(mc, int_mc_errors[bit].status_reg); + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->num_address_bits > 32) { + if (int_mc_errors[bit].addr_reg_hi) + addr = mc_readl(mc, + int_mc_errors[bit].addr_reg_hi); + else + addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); + addr <<= 32; + } +#endif + addr |= mc_readl(mc, int_mc_errors[bit].addr_reg); + + if (value & MC_ERR_STATUS_RW) + direction = "write"; + else + direction = "read"; + + if (value & MC_ERR_STATUS_SECURITY) + secure = "secure "; + else + secure = ""; + + id = value & mc->soc->client_id_mask; + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == id) { + client = mc->soc->clients[i].name; + break; + } + } + + dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s\n", + client, secure, direction, &addr, error); + } + + /* clear interrupts */ + mc_writel(mc, status, MC_INTSTATUS); + + return IRQ_HANDLED; +} + const struct tegra_mc_interrupt_ops tegra194_mc_interrupt_ops = { .clear_interrupt = tegra194_mc_clear_interrupt, + .handle_irq = tegra194_mc_handle_irq, }; static const struct tegra_mc_client tegra194_mc_clients[] = { @@ -1358,6 +1465,7 @@ const struct tegra_mc_soc tegra194_mc_soc = { .num_clients = ARRAY_SIZE(tegra194_mc_clients), .clients = tegra194_mc_clients, .num_address_bits = 40, + .client_id_mask = 0xff, .intmask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_WCAM_ERR | MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | -- 2.7.4