[PATCH 0/6] Add I2C and PWM support for T234

[PATCH 0/6] Add I2C and PWM support for T234

[Akhil R]

The patchset contains driver and devicetree changes to support I2C and
PWM for Tegra234

Akhil R (6):
  i2c: tegra: Add support for Tegra234 I2C
  dt-bindings: i2c: tegra: Add Tegra234 details
  dt-bindings: Add headers for Tegra234 I2C
  arm64: tegra: Add Tegra234 I2C devicetree nodes
  dt-bindings: Add headers for Tegra234 PWM
  arm64: tegra: Add Tegra234 PWM devicetree nodes

 .../bindings/i2c/nvidia,tegra20-i2c.yaml           |   5 +
 arch/arm64/boot/dts/nvidia/tegra234.dtsi           | 133 +++++++++++++++++++++
 drivers/i2c/busses/i2c-tegra.c                     |  25 ++++
 include/dt-bindings/clock/tegra234-clock.h         |  36 ++++++
 include/dt-bindings/reset/tegra234-reset.h         |  16 +++
 5 files changed, 215 insertions(+)

-- 
2.7.4

[PATCH 1/6] i2c: tegra: Add support for Tegra234 I2C

[Akhil R]

Add Tegra234 specific hw struct and compatible in i2c-tegra driver

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 drivers/i2c/busses/i2c-tegra.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 03cea10..3e8f3f5 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -1614,7 +1614,32 @@ static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
 	.has_interface_timing_reg = true,
 };
 
+static const struct tegra_i2c_hw_feature tegra234_i2c_hw = {
+	.has_continue_xfer_support = true,
+	.has_per_pkt_xfer_complete_irq = true,
+	.clk_divisor_hs_mode = 0x2,
+	.clk_divisor_std_mode = 0x4f,
+	.clk_divisor_fast_mode = 0x58,
+	.clk_divisor_fast_plus_mode = 0x24,
+	.has_config_load_reg = true,
+	.has_multi_master_mode = true,
+	.has_slcg_override_reg = true,
+	.has_mst_fifo = true,
+	.quirks = &tegra194_i2c_quirks,
+	.supports_bus_clear = true,
+	.has_apb_dma = false,
+	.tlow_std_mode = 0x8,
+	.thigh_std_mode = 0x7,
+	.tlow_fast_fastplus_mode = 0x1,
+	.thigh_fast_fastplus_mode = 0x1,
+	.setup_hold_time_std_mode = 0x08080808,
+	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
+	.setup_hold_time_hs_mode = 0x090909,
+	.has_interface_timing_reg = true,
+};
+
 static const struct of_device_id tegra_i2c_of_match[] = {
+	{ .compatible = "nvidia,tegra234-i2c", .data = &tegra234_i2c_hw, },
 	{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
 	{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
 	{ .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
-- 
2.7.4

[PATCH 2/6] dt-bindings: i2c: tegra: Add Tegra234 details

[Akhil R]

Add documentation for Tegra234 I2C compatible.

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
index 424a4fc..c58e256 100644
--- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
@@ -80,6 +80,11 @@ properties:
           support for 64 KiB transactions whereas earlier chips supported no
           more than 4 KiB per transactions.
         const: nvidia,tegra194-i2c
+      - description: |
+          Tegra234 has 8 generic I2C controllers, two of which are in the AON
+          (always-on) partition of the SoC. All of these controllers are
+          similar to those found on Tegra194.
+        const: nvidia,tegra234-i2c
 
   reg:
     maxItems: 1
-- 
2.7.4

[PATCH 3/6] dt-bindings: Add headers for Tegra234 I2C

[Akhil R]

Add dt-bindings header files for I2C controllers for Tegra234

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 include/dt-bindings/clock/tegra234-clock.h | 19 +++++++++++++++++++
 include/dt-bindings/reset/tegra234-reset.h |  8 ++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 8d7e66e..5d05c19 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -30,5 +30,24 @@
 #define TEGRA234_CLK_PLLC4			237U
 /** @brief 32K input clock provided by PMIC */
 #define TEGRA234_CLK_CLK_32K			289U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
+#define TEGRA234_CLK_I2C1			48U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
+#define TEGRA234_CLK_I2C2			49U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
+#define TEGRA234_CLK_I2C3			50U
+/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
+#define TEGRA234_CLK_I2C4			51U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
+#define TEGRA234_CLK_I2C6			52U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
+#define TEGRA234_CLK_I2C7			53U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
+#define TEGRA234_CLK_I2C8			54U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
+#define TEGRA234_CLK_I2C9			55U
+
+/** @brief PLLP clk output */
+#define TEGRA234_CLK_PLLP_OUT0			102U
 
 #endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 50e13bc..e07e898 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -12,6 +12,14 @@
  */
 #define TEGRA234_RESET_SDMMC4			85U
 #define TEGRA234_RESET_UARTA			100U
+#define TEGRA234_RESET_I2C1			24U
+#define TEGRA234_RESET_I2C2			29U
+#define TEGRA234_RESET_I2C3			30U
+#define TEGRA234_RESET_I2C4			31U
+#define TEGRA234_RESET_I2C6			32U
+#define TEGRA234_RESET_I2C7			33U
+#define TEGRA234_RESET_I2C8			34U
+#define TEGRA234_RESET_I2C9			35U
 
 /** @} */
 
-- 
2.7.4

[PATCH 4/6] arm64: tegra: Add Tegra234 I2C devicetree nodes

[Akhil R]

Add device tree nodes for Tegra234 I2C controllers

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 121 +++++++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 6b6f1580..51aff7d 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -144,6 +144,96 @@
 			status = "disabled";
 		};
 
+		gen1_i2c: i2c@3160000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x3160000 0x100>;
+			status = "disabled";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <400000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C1
+				  &bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C1>;
+			reset-names = "i2c";
+		};
+
+		cam_i2c: i2c@3180000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x3180000 0x100>;
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <400000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C3
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C3>;
+			reset-names = "i2c";
+		};
+
+		dp_aux_ch1_i2c: i2c@3190000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x3190000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <100000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C4
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C4>;
+			reset-names = "i2c";
+		};
+
+		dp_aux_ch0_i2c: i2c@31b0000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x31b0000 0x100>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <100000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C6
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C6>;
+			reset-names = "i2c";
+		};
+
+		dp_aux_ch2_i2c: i2c@31c0000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x31c0000 0x100>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <100000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C7
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C7>;
+			reset-names = "i2c";
+		};
+
+		dp_aux_ch3_i2c: i2c@31e0000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0x31e0000 0x100>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <100000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C9
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			resets = <&bpmp TEGRA234_RESET_I2C9>;
+			reset-names = "i2c";
+		};
+
 		mmc@3460000 {
 			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
 			reg = <0x03460000 0x20000>;
@@ -212,6 +302,37 @@
 			#mbox-cells = <2>;
 		};
 
+		gen2_i2c: i2c@c240000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0xc240000 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <100000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C2
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			resets = <&bpmp TEGRA234_RESET_I2C2>;
+			reset-names = "i2c";
+		};
+
+		gen8_i2c: i2c@c250000 {
+			compatible = "nvidia,tegra234-i2c";
+			reg = <0xc250000 0x100>;
+			nvidia,hw-instance-id = <0x7>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			clock-frequency = <400000>;
+			clocks = <&bpmp TEGRA234_CLK_I2C8
+				&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			clock-names = "div-clk", "parent";
+			assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
+			assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+			resets = <&bpmp TEGRA234_RESET_I2C8>;
+			reset-names = "i2c";
+		};
+
 		rtc@c2a0000 {
 			compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
 			reg = <0x0c2a0000 0x10000>;
-- 
2.7.4

[PATCH 5/6] dt-bindings: Add headers for Tegra234 PWM

[Akhil R]

Add dt-bindings header files for PWM of Tegra234

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 include/dt-bindings/clock/tegra234-clock.h | 17 +++++++++++++++++
 include/dt-bindings/reset/tegra234-reset.h |  8 ++++++++
 2 files changed, 25 insertions(+)

diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index 5d05c19..9d17309 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -50,4 +50,21 @@
 /** @brief PLLP clk output */
 #define TEGRA234_CLK_PLLP_OUT0			102U
 
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
+#define TEGRA234_CLK_PWM1			105U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
+#define TEGRA234_CLK_PWM2			106U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
+#define TEGRA234_CLK_PWM3			107U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
+#define TEGRA234_CLK_PWM4			108U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
+#define TEGRA234_CLK_PWM5			109U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
+#define TEGRA234_CLK_PWM6			110U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
+#define TEGRA234_CLK_PWM7			111U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
+#define TEGRA234_CLK_PWM8			112U
+
 #endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index e07e898..288524f 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -20,6 +20,14 @@
 #define TEGRA234_RESET_I2C7			33U
 #define TEGRA234_RESET_I2C8			34U
 #define TEGRA234_RESET_I2C9			35U
+#define TEGRA234_RESET_PWM1			68U
+#define TEGRA234_RESET_PWM2			69U
+#define TEGRA234_RESET_PWM3			70U
+#define TEGRA234_RESET_PWM4			71U
+#define TEGRA234_RESET_PWM5			72U
+#define TEGRA234_RESET_PWM6			73U
+#define TEGRA234_RESET_PWM7			74U
+#define TEGRA234_RESET_PWM8			75U
 
 /** @} */
 
-- 
2.7.4

[PATCH 6/6] arm64: tegra: Add Tegra234 PWM devicetree nodes

[Akhil R]

Add device tree nodes for Tegra234 PWM

Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 51aff7d..53a5475 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -234,6 +234,18 @@
 			reset-names = "i2c";
 		};
 
+		pwm1: pwm@3280000 {
+			compatible = "nvidia,tegra194-pwm",
+				     "nvidia,tegra186-pwm";
+			reg = <0x3280000 0x10000>;
+			clocks = <&bpmp TEGRA234_CLK_PWM1>;
+			clock-names = "pwm";
+			resets = <&bpmp TEGRA234_RESET_PWM1>;
+			reset-names = "pwm";
+			status = "disabled";
+			#pwm-cells = <2>;
+		};
+
 		mmc@3460000 {
 			compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
 			reg = <0x03460000 0x20000>;
-- 
2.7.4

Re: [PATCH 1/6] i2c: tegra: Add support for Tegra234 I2C

[Dmitry Osipenko]

13.01.2022 16:30, Akhil R пишет:
> +static const struct tegra_i2c_hw_feature tegra234_i2c_hw = {
> +	.has_continue_xfer_support = true,
> +	.has_per_pkt_xfer_complete_irq = true,
> +	.clk_divisor_hs_mode = 0x2,
> +	.clk_divisor_std_mode = 0x4f,
> +	.clk_divisor_fast_mode = 0x58,
> +	.clk_divisor_fast_plus_mode = 0x24,
> +	.has_config_load_reg = true,
> +	.has_multi_master_mode = true,
> +	.has_slcg_override_reg = true,
> +	.has_mst_fifo = true,
> +	.quirks = &tegra194_i2c_quirks,
> +	.supports_bus_clear = true,
> +	.has_apb_dma = false,
> +	.tlow_std_mode = 0x8,
> +	.thigh_std_mode = 0x7,
> +	.tlow_fast_fastplus_mode = 0x1,
> +	.thigh_fast_fastplus_mode = 0x1,
> +	.setup_hold_time_std_mode = 0x08080808,
> +	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
> +	.setup_hold_time_hs_mode = 0x090909,
> +	.has_interface_timing_reg = true,
> +};

Why tegra194_i2c_hw can't be reused by T234? Looks like I2C h/w hasn't
changed and somebody just made a minor tuning of the timing parameters,
does it really matter in practice?

RE: [PATCH 1/6] i2c: tegra: Add support for Tegra234 I2C

[Akhil R]

> 13.01.2022 16:30, Akhil R пишет:
> > +static const struct tegra_i2c_hw_feature tegra234_i2c_hw = {
> > +     .has_continue_xfer_support = true,
> > +     .has_per_pkt_xfer_complete_irq = true,
> > +     .clk_divisor_hs_mode = 0x2,
> > +     .clk_divisor_std_mode = 0x4f,
> > +     .clk_divisor_fast_mode = 0x58,
> > +     .clk_divisor_fast_plus_mode = 0x24,
> > +     .has_config_load_reg = true,
> > +     .has_multi_master_mode = true,
> > +     .has_slcg_override_reg = true,
> > +     .has_mst_fifo = true,
> > +     .quirks = &tegra194_i2c_quirks,
> > +     .supports_bus_clear = true,
> > +     .has_apb_dma = false,
> > +     .tlow_std_mode = 0x8,
> > +     .thigh_std_mode = 0x7,
> > +     .tlow_fast_fastplus_mode = 0x1,
> > +     .thigh_fast_fastplus_mode = 0x1,
> > +     .setup_hold_time_std_mode = 0x08080808,
> > +     .setup_hold_time_fast_fast_plus_mode = 0x02020202,
> > +     .setup_hold_time_hs_mode = 0x090909,
> > +     .has_interface_timing_reg = true, };
> 
> Why tegra194_i2c_hw can't be reused by T234? Looks like I2C h/w hasn't
> changed and somebody just made a minor tuning of the timing parameters, does
> it really matter in practice?
The timing parameters are important to get the desired data rate for I2C. The values,
unfortunately, cannot be reused from Tegra194.

Thanks,
Akhil

--
nvpublic

Re: [PATCH 1/6] i2c: tegra: Add support for Tegra234 I2C

[Dmitry Osipenko]

19.01.2022 11:20, Akhil R пишет:
>> 13.01.2022 16:30, Akhil R пишет:
>>> +static const struct tegra_i2c_hw_feature tegra234_i2c_hw = {
>>> +     .has_continue_xfer_support = true,
>>> +     .has_per_pkt_xfer_complete_irq = true,
>>> +     .clk_divisor_hs_mode = 0x2,
>>> +     .clk_divisor_std_mode = 0x4f,
>>> +     .clk_divisor_fast_mode = 0x58,
>>> +     .clk_divisor_fast_plus_mode = 0x24,
>>> +     .has_config_load_reg = true,
>>> +     .has_multi_master_mode = true,
>>> +     .has_slcg_override_reg = true,
>>> +     .has_mst_fifo = true,
>>> +     .quirks = &tegra194_i2c_quirks,
>>> +     .supports_bus_clear = true,
>>> +     .has_apb_dma = false,
>>> +     .tlow_std_mode = 0x8,
>>> +     .thigh_std_mode = 0x7,
>>> +     .tlow_fast_fastplus_mode = 0x1,
>>> +     .thigh_fast_fastplus_mode = 0x1,
>>> +     .setup_hold_time_std_mode = 0x08080808,
>>> +     .setup_hold_time_fast_fast_plus_mode = 0x02020202,
>>> +     .setup_hold_time_hs_mode = 0x090909,
>>> +     .has_interface_timing_reg = true, };
>>
>> Why tegra194_i2c_hw can't be reused by T234? Looks like I2C h/w hasn't
>> changed and somebody just made a minor tuning of the timing parameters, does
>> it really matter in practice?
> The timing parameters are important to get the desired data rate for I2C. The values,
> unfortunately, cannot be reused from Tegra194.

From where those T194 parameters specified in the Tegra I2C driver came
from?

I'm now looking at T194 TRM (Xavier_TRM_DP09253002_v1.3p 10.2.3.1.1
Example Settings for Various I2C Speeds) and see that all the values
should match T234. Please check whether T194 configuration is correct
and fix it if needed.

RE: [PATCH 1/6] i2c: tegra: Add support for Tegra234 I2C

[Akhil R]

> >>> +static const struct tegra_i2c_hw_feature tegra234_i2c_hw = {
> >>> +     .has_continue_xfer_support = true,
> >>> +     .has_per_pkt_xfer_complete_irq = true,
> >>> +     .clk_divisor_hs_mode = 0x2,
> >>> +     .clk_divisor_std_mode = 0x4f,
> >>> +     .clk_divisor_fast_mode = 0x58,
> >>> +     .clk_divisor_fast_plus_mode = 0x24,
> >>> +     .has_config_load_reg = true,
> >>> +     .has_multi_master_mode = true,
> >>> +     .has_slcg_override_reg = true,
> >>> +     .has_mst_fifo = true,
> >>> +     .quirks = &tegra194_i2c_quirks,
> >>> +     .supports_bus_clear = true,
> >>> +     .has_apb_dma = false,
> >>> +     .tlow_std_mode = 0x8,
> >>> +     .thigh_std_mode = 0x7,
> >>> +     .tlow_fast_fastplus_mode = 0x1,
> >>> +     .thigh_fast_fastplus_mode = 0x1,
> >>> +     .setup_hold_time_std_mode = 0x08080808,
> >>> +     .setup_hold_time_fast_fast_plus_mode = 0x02020202,
> >>> +     .setup_hold_time_hs_mode = 0x090909,
> >>> +     .has_interface_timing_reg = true, };
> >>
> >> Why tegra194_i2c_hw can't be reused by T234? Looks like I2C h/w hasn't
> >> changed and somebody just made a minor tuning of the timing parameters,
> does
> >> it really matter in practice?
> > The timing parameters are important to get the desired data rate for I2C. The
> values,
> > unfortunately, cannot be reused from Tegra194.
> 
> From where those T194 parameters specified in the Tegra I2C driver came
> from?
> 
> I'm now looking at T194 TRM (Xavier_TRM_DP09253002_v1.3p 10.2.3.1.1
> Example Settings for Various I2C Speeds) and see that all the values
> should match T234. Please check whether T194 configuration is correct
> and fix it if needed.

Thanks for highlighting this. There are adjustments in the default timing values
of T194 from TRM. I am checking if these changes can be used for T234 as well.
Will send an updated patch if the same values apply for T234.

Thanks,
Akhil

Re: [PATCH 2/6] dt-bindings: i2c: tegra: Add Tegra234 details

[Rob Herring]

On Thu, Jan 13, 2022 at 07:00:19PM +0530, Akhil R wrote:
> Add documentation for Tegra234 I2C compatible.
> 
> Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> ---
>  Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> index 424a4fc..c58e256 100644
> --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> @@ -80,6 +80,11 @@ properties:
>            support for 64 KiB transactions whereas earlier chips supported no
>            more than 4 KiB per transactions.
>          const: nvidia,tegra194-i2c
> +      - description: |
> +          Tegra234 has 8 generic I2C controllers, two of which are in the AON
> +          (always-on) partition of the SoC. All of these controllers are
> +          similar to those found on Tegra194.
> +        const: nvidia,tegra234-i2c

Sounds like this needs a fallback to nvidia,tegra194-i2c if it works, 
but without optimal timing.

Rob

RE: [PATCH 2/6] dt-bindings: i2c: tegra: Add Tegra234 details

[Akhil R]

> On Thu, Jan 13, 2022 at 07:00:19PM +0530, Akhil R wrote:
> > Add documentation for Tegra234 I2C compatible.
> >
> > Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
> > ---
> >  Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml | 5
> > +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> > b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> > index 424a4fc..c58e256 100644
> > --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> > +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml
> > @@ -80,6 +80,11 @@ properties:
> >            support for 64 KiB transactions whereas earlier chips supported no
> >            more than 4 KiB per transactions.
> >          const: nvidia,tegra194-i2c
> > +      - description: |
> > +          Tegra234 has 8 generic I2C controllers, two of which are in the AON
> > +          (always-on) partition of the SoC. All of these controllers are
> > +          similar to those found on Tegra194.
> > +        const: nvidia,tegra234-i2c
> 
> Sounds like this needs a fallback to nvidia,tegra194-i2c if it works, but without
> optimal timing.
Yes. The timing for tegra194 works for tegra234 as well. So, this change is reverted.
I had sent the patch updated. Latest is here - https://lkml.org/lkml/2022/1/24/335
Only the device tree nodes are required to be added now.

Thanks,
Akhil