* [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush
@ 2022-01-28 22:10 Michael Cheng
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
` (7 more replies)
0 siblings, 8 replies; 22+ messages in thread
From: Michael Cheng @ 2022-01-28 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, matthew.auld, mika.kuoppala
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
Michael Cheng (4):
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Re-work invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
.../gpu/drm/i915/gt/intel_execlists_submission.c | 6 ++++--
3 files changed, 11 insertions(+), 16 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
@ 2022-01-28 22:10 ` Michael Cheng
2022-01-29 7:21 ` Bowman, Casey G
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries Michael Cheng
` (6 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Michael Cheng @ 2022-01-28 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, matthew.auld, mika.kuoppala
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 08559ace0ada..beb979e40a13 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
@ 2022-01-28 22:10 ` Michael Cheng
2022-01-29 7:21 ` Bowman, Casey G
2022-01-31 13:51 ` Tvrtko Ursulin
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
` (5 subsequent siblings)
7 siblings, 2 replies; 22+ messages in thread
From: Michael Cheng @ 2022-01-28 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, matthew.auld, mika.kuoppala
Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 960a9aaf4f3a..90b5daf9433d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1647,8 +1647,8 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
static void invalidate_csb_entries(const u64 *first, const u64 *last)
{
- clflush((void *)first);
- clflush((void *)last);
+ drm_clflush_virt_range((void *)first, sizeof(*first));
+ drm_clflush_virt_range((void *)last, sizeof(*last));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries Michael Cheng
@ 2022-01-28 22:10 ` Michael Cheng
2022-01-29 7:23 ` Bowman, Casey G
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
` (4 subsequent siblings)
7 siblings, 1 reply; 22+ messages in thread
From: Michael Cheng @ 2022-01-28 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, matthew.auld, mika.kuoppala
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 90b5daf9433d..e8a2e2683b81 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2951,6 +2951,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
mb(); /* paranoia: read the CSB pointers from after the reset */
clflush(execlists->csb_write);
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
mb();
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (2 preceding siblings ...)
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
@ 2022-01-28 22:10 ` Michael Cheng
2022-01-29 7:24 ` Bowman, Casey G
2022-01-31 14:55 ` Tvrtko Ursulin
2022-01-28 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev2) Patchwork
` (3 subsequent siblings)
7 siblings, 2 replies; 22+ messages in thread
From: Michael Cheng @ 2022-01-28 22:10 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, matthew.auld, mika.kuoppala
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev2)
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (3 preceding siblings ...)
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
@ 2022-01-28 22:31 ` Patchwork
2022-01-28 22:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
7 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-28 22:31 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c57ea525b16d drm/i915/gt: Re-work intel_write_status_page
addcbfa4043f drm/i915/gt: Re-work invalidate_csb_entries
1818a889230d drm/i915/gt: Re-work reset_csb
-:20: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#20: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2955:
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
total: 0 errors, 0 warnings, 1 checks, 8 lines checked
f9a30ee54be5 drm/i915/: Re-work clflush_write32
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush (rev2)
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (4 preceding siblings ...)
2022-01-28 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev2) Patchwork
@ 2022-01-28 22:33 ` Patchwork
2022-01-28 22:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-29 3:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-28 22:33 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Use drm_clflush* instead of clflush (rev2)
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (5 preceding siblings ...)
2022-01-28 22:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-01-28 22:59 ` Patchwork
2022-01-29 3:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
7 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-28 22:59 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5574 bytes --]
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11159 -> Patchwork_22141
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/index.html
Participating hosts (42 -> 40)
------------------------------
Missing (2): fi-bsw-cyan fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22141 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][2] ([i915#4547])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-skl-6600u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4] ([i915#2940])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][5] -> [DMESG-FAIL][6] ([i915#295])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][7] -> [DMESG-WARN][8] ([i915#295]) +10 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@runner@aborted:
- fi-skl-6600u: NOTRUN -> [FAIL][9] ([i915#4312])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-skl-6600u/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][10] ([fdo#109271] / [i915#1436] / [i915#3428] / [i915#4312])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-bsw-n3050/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][11] ([i915#3921]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- {bat-adlp-6}: [DMESG-WARN][13] ([i915#1888]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/bat-adlp-6/igt@i915_selftest@live@hugepages.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/bat-adlp-6/igt@i915_selftest@live@hugepages.html
#### Warnings ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][15] ([i915#4785]) -> [INCOMPLETE][16] ([i915#3303])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
Build changes
-------------
* Linux: CI_DRM_11159 -> Patchwork_22141
CI-20190529: 20190529
CI_DRM_11159: 7b9572e09d0679204bd24288e3d1b82f1fef8357 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6336: ae2eb9e18bc58a4c45f28cfd80962938198dec3c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22141: f9a30ee54be591ed41d245c9bb9bc79d5687b15d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f9a30ee54be5 drm/i915/: Re-work clflush_write32
1818a889230d drm/i915/gt: Re-work reset_csb
addcbfa4043f drm/i915/gt: Re-work invalidate_csb_entries
c57ea525b16d drm/i915/gt: Re-work intel_write_status_page
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/index.html
[-- Attachment #2: Type: text/html, Size: 6430 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Use drm_clflush* instead of clflush (rev2)
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
` (6 preceding siblings ...)
2022-01-28 22:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-29 3:00 ` Patchwork
7 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2022-01-29 3:00 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30265 bytes --]
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev2)
URL : https://patchwork.freedesktop.org/series/99450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11159_full -> Patchwork_22141_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22141_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22141_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22141_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-tglb7/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-tglb6/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
Known issues
------------
Here are the changes found in Patchwork_22141_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-1us:
- shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-tglb1/igt@gem_eio@in-flight-1us.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-tglb1/igt@gem_eio@in-flight-1us.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb7/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_capture@pi@vecs0:
- shard-skl: NOTRUN -> [INCOMPLETE][7] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@gem_exec_capture@pi@vecs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][8] ([i915#2846])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl8/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-glk7/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_schedule@u-semaphore-user:
- shard-snb: NOTRUN -> [SKIP][14] ([fdo#109271]) +77 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-snb4/igt@gem_exec_schedule@u-semaphore-user.html
* igt@gem_exec_whisper@basic-fds-forked:
- shard-glk: [PASS][15] -> [DMESG-WARN][16] ([i915#118]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-glk1/igt@gem_exec_whisper@basic-fds-forked.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-glk6/igt@gem_exec_whisper@basic-fds-forked.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-kbl: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl1/igt@gem_pread@exhaustion.html
* igt@gem_softpin@allocator-evict-all-engines:
- shard-glk: [PASS][20] -> [FAIL][21] ([i915#4171])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-glk3/igt@gem_softpin@allocator-evict-all-engines.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-glk4/igt@gem_softpin@allocator-evict-all-engines.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][22] ([i915#4990])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-kbl: NOTRUN -> [FAIL][23] ([i915#3318])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@gem_userptr_blits@vma-merge.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: NOTRUN -> [FAIL][24] ([i915#454])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
- shard-skl: NOTRUN -> [FAIL][25] ([i915#454])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#3743]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][27] ([i915#3763])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3777])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#110723])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][30] ([i915#2705])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +6 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl7/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +5 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@hdmi-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +8 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl1/igt@kms_chamelium@hdmi-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +18 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl7/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_chamelium@hdmi-hpd-with-enabled-mode:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#109284] / [fdo#111827])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-snb: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-snb4/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][37] ([i915#1319])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109278]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [FAIL][41] ([i915#2346] / [i915#533])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271]) +205 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][43] -> [FAIL][44] ([i915#2122]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [INCOMPLETE][45] ([i915#3701])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-kbl: NOTRUN -> [SKIP][46] ([fdo#109271]) +111 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109280]) +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: NOTRUN -> [FAIL][48] ([i915#1188]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl1/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-apl: [PASS][49] -> [DMESG-WARN][50] ([i915#180]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-apl2/igt@kms_hdr@bpc-switch-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl8/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][52] ([fdo#108145] / [i915#265]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][53] ([i915#265]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][56] -> [SKIP][57] ([fdo#109441])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2437])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl1/igt@kms_writeback@writeback-check-output.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][59] -> [FAIL][60] ([i915#1542])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl1/igt@perf@polling-parameterized.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl6/igt@perf@polling-parameterized.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][61] -> [FAIL][62] ([i915#1722])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl10/igt@perf@polling-small-buf.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl8/igt@perf@polling-small-buf.html
* igt@sysfs_clients@create:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2994]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl4/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-0:
- shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#2994])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl1/igt@sysfs_clients@fair-0.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][65] ([i915#658]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb6/igt@feature_discovery@psr2.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_eio@in-flight-immediate:
- shard-skl: [TIMEOUT][67] ([i915#3063]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl4/igt@gem_eio@in-flight-immediate.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl4/igt@gem_eio@in-flight-immediate.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][69] ([i915#4525]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [INCOMPLETE][71] ([i915#4547]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl8/igt@gem_exec_capture@pi@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][73] ([i915#2846]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@gem_exec_fair@basic-deadline.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][75] ([i915#2842]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-apl1/igt@gem_exec_fair@basic-none@vcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][79] ([i915#2842]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-glk7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][81] ([i915#2842]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-snb: [DMESG-FAIL][83] ([i915#4998]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-snb7/igt@gem_ppgtt@blt-vs-render-ctxn.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-snb5/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][85] ([i915#1436] / [i915#716]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl7/igt@gen9_exec_parse@allowed-single.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-skl: [FAIL][89] ([i915#79]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip@flip-vs-fences-interruptible@a-vga1:
- shard-snb: [INCOMPLETE][91] -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-snb6/igt@kms_flip@flip-vs-fences-interruptible@a-vga1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-snb4/igt@kms_flip@flip-vs-fences-interruptible@a-vga1.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [INCOMPLETE][93] ([i915#3614]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [FAIL][95] ([i915#2122]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl1/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +1 similar issue
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb3/igt@kms_psr@psr2_cursor_render.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: [INCOMPLETE][99] ([i915#180] / [i915#794]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@perf_pmu@rc6-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl1/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][101] ([i915#232]) -> [TIMEOUT][102] ([i915#3063] / [i915#3648])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-tglb8/igt@gem_eio@unwedge-stress.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][103] ([i915#1804] / [i915#2684]) -> [WARN][104] ([i915#2684])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][105] ([i915#2920]) -> [SKIP][106] ([fdo#111068] / [i915#658])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][107] ([i915#4148]) -> [SKIP][108] ([fdo#109642] / [fdo#111068] / [i915#658])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-iclb5/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112], [FAIL][113]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@runner@aborted.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl7/igt@runner@aborted.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@runner@aborted.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@runner@aborted.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-kbl4/igt@runner@aborted.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@runner@aborted.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl4/igt@runner@aborted.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl4/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl6/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl7/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-kbl4/igt@runner@aborted.html
- shard-apl: ([FAIL][120], [FAIL][121]) ([i915#3002] / [i915#4312]) -> ([FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126]) ([i915#180] / [i915#3002] / [i915#4312])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-apl2/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-apl1/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl3/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl7/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl8/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-apl8/igt@runner@aborted.html
- shard-skl: ([FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130]) ([i915#1436] / [i915#3002] / [i915#4312]) -> ([FAIL][131], [FAIL][132], [FAIL][133]) ([i915#3002] / [i915#4312])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl9/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl8/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11159/shard-skl7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl9/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl6/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/shard-skl10/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3763]: https://gitlab.freedesktop.org/drm/intel/issues/3763
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4148]: https://gitlab.freedesktop.org/drm/intel/issues/4148
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4990]: https://gitlab.freedesktop.org/drm/intel/issues/4990
[i915#4998]: https://gitlab.freedesktop.org/drm/intel/issues/4998
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Build changes
-------------
* Linux:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22141/index.html
[-- Attachment #2: Type: text/html, Size: 37158 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
@ 2022-01-29 7:21 ` Bowman, Casey G
0 siblings, 0 replies; 22+ messages in thread
From: Bowman, Casey G @ 2022-01-29 7:21 UTC (permalink / raw)
To: Cheng, Michael, intel-gfx; +Cc: Kuoppala, Mika, De Marchi, Lucas, Auld, Matthew
> -----Original Message-----
> From: Cheng, Michael <michael.cheng@intel.com>
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael <michael.cheng@intel.com>; Bowman, Casey G
> <casey.g.bowman@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Boyer, Wayne <wayne.boyer@intel.com>;
> ville.syrjala@linux.intel.com; Kuoppala, Mika <mika.kuoppala@intel.com>;
> Auld, Matthew <matthew.auld@intel.com>
> Subject: [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page
>
> Re-work intel_write_status_page to use drm_clflush_virt_range. This will
> prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
> 1 file changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h
> b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 08559ace0ada..beb979e40a13 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -4,6 +4,7 @@
>
> #include <asm/cacheflush.h>
> #include <drm/drm_util.h>
> +#include <drm/drm_cache.h>
>
> #include <linux/hashtable.h>
> #include <linux/irq_work.h>
> @@ -144,15 +145,9 @@ intel_write_status_page(struct intel_engine_cs
> *engine, int reg, u32 value)
> * of extra paranoia to try and ensure that the HWS takes the value
> * we give and that it doesn't end up trapped inside the CPU!
> */
> - if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
> - mb();
> - clflush(&engine->status_page.addr[reg]);
> - engine->status_page.addr[reg] = value;
> - clflush(&engine->status_page.addr[reg]);
> - mb();
> - } else {
> - WRITE_ONCE(engine->status_page.addr[reg], value);
> - }
> + drm_clflush_virt_range(&engine->status_page.addr[reg],
> sizeof(value));
> + WRITE_ONCE(engine->status_page.addr[reg], value);
> + drm_clflush_virt_range(&engine->status_page.addr[reg],
> sizeof(value));
> }
>
> /*
> --
> 2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries Michael Cheng
@ 2022-01-29 7:21 ` Bowman, Casey G
2022-01-31 13:51 ` Tvrtko Ursulin
1 sibling, 0 replies; 22+ messages in thread
From: Bowman, Casey G @ 2022-01-29 7:21 UTC (permalink / raw)
To: Cheng, Michael, intel-gfx; +Cc: Kuoppala, Mika, De Marchi, Lucas, Auld, Matthew
> -----Original Message-----
> From: Cheng, Michael <michael.cheng@intel.com>
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael <michael.cheng@intel.com>; Bowman, Casey G
> <casey.g.bowman@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Boyer, Wayne <wayne.boyer@intel.com>;
> ville.syrjala@linux.intel.com; Kuoppala, Mika <mika.kuoppala@intel.com>;
> Auld, Matthew <matthew.auld@intel.com>
> Subject: [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
>
> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
> prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 960a9aaf4f3a..90b5daf9433d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1647,8 +1647,8 @@ cancel_port_requests(struct intel_engine_execlists
> * const execlists,
>
> static void invalidate_csb_entries(const u64 *first, const u64 *last) {
> - clflush((void *)first);
> - clflush((void *)last);
> + drm_clflush_virt_range((void *)first, sizeof(*first));
> + drm_clflush_virt_range((void *)last, sizeof(*last));
> }
>
> /*
> --
> 2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
@ 2022-01-29 7:23 ` Bowman, Casey G
0 siblings, 0 replies; 22+ messages in thread
From: Bowman, Casey G @ 2022-01-29 7:23 UTC (permalink / raw)
To: Cheng, Michael, intel-gfx; +Cc: Kuoppala, Mika, De Marchi, Lucas, Auld, Matthew
> -----Original Message-----
> From: Cheng, Michael <michael.cheng@intel.com>
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael <michael.cheng@intel.com>; Bowman, Casey G
> <casey.g.bowman@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Boyer, Wayne <wayne.boyer@intel.com>;
> ville.syrjala@linux.intel.com; Kuoppala, Mika <mika.kuoppala@intel.com>;
> Auld, Matthew <matthew.auld@intel.com>
> Subject: [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb
>
> Use drm_clflush_virt_range instead of directly invoking clflush. This will
> prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 90b5daf9433d..e8a2e2683b81 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2951,6 +2951,8 @@ reset_csb(struct intel_engine_cs *engine, struct
> i915_request **inactive)
>
> mb(); /* paranoia: read the CSB pointers from after the reset */
> clflush(execlists->csb_write);
> + drm_clflush_virt_range(execlists->csb_write,
> + sizeof(execlists->csb_write));
I only see the insertion of drm_clflush_virt_range() here, not the removal of the
clflush() call, which sounds like it's supposed to be replaced here, based on your
commit message.
> mb();
>
> inactive = process_csb(engine, inactive); /* drain preemption events
> */
> --
> 2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
@ 2022-01-29 7:24 ` Bowman, Casey G
2022-01-31 14:55 ` Tvrtko Ursulin
1 sibling, 0 replies; 22+ messages in thread
From: Bowman, Casey G @ 2022-01-29 7:24 UTC (permalink / raw)
To: Cheng, Michael, intel-gfx; +Cc: Kuoppala, Mika, De Marchi, Lucas, Auld, Matthew
> -----Original Message-----
> From: Cheng, Michael <michael.cheng@intel.com>
> Sent: Friday, January 28, 2022 2:10 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Cheng, Michael <michael.cheng@intel.com>; Bowman, Casey G
> <casey.g.bowman@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>; Boyer, Wayne <wayne.boyer@intel.com>;
> ville.syrjala@linux.intel.com; Kuoppala, Mika <mika.kuoppala@intel.com>;
> Auld, Matthew <matthew.auld@intel.com>
> Subject: [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
>
> Use drm_clflush_virt_range instead of clflushopt and remove the memory
> barrier, since drm_clflush_virt_range takes care of that.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Casey Bowman <casey.g.bowman@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 498b458fd784..0854276ff7ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
> static void clflush_write32(u32 *addr, u32 value, unsigned int flushes) {
> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
> - if (flushes & CLFLUSH_BEFORE) {
> - clflushopt(addr);
> - mb();
> - }
> + if (flushes & CLFLUSH_BEFORE)
> + drm_clflush_virt_range(addr, sizeof(addr));
>
> *addr = value;
>
> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value,
> unsigned int flushes)
> * to ensure ordering of clflush wrt to the system.
> */
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
> } else
> *addr = value;
> }
> --
> 2.25.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries Michael Cheng
2022-01-29 7:21 ` Bowman, Casey G
@ 2022-01-31 13:51 ` Tvrtko Ursulin
2022-01-31 14:15 ` Mika Kuoppala
1 sibling, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2022-01-31 13:51 UTC (permalink / raw)
To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
On 28/01/2022 22:10, Michael Cheng wrote:
> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
> prevent compiler errors when building for non-x86 architectures.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 960a9aaf4f3a..90b5daf9433d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -1647,8 +1647,8 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
>
> static void invalidate_csb_entries(const u64 *first, const u64 *last)
> {
> - clflush((void *)first);
> - clflush((void *)last);
> + drm_clflush_virt_range((void *)first, sizeof(*first));
> + drm_clflush_virt_range((void *)last, sizeof(*last));
How about dropping the helper and from the single call site do:
drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
One less function call and CSB is a single cacheline before Gen11 ayway,
two afterwards, so overall better conversion I think. How does that sound?
Regards,
Tvrtko
> }
>
> /*
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
2022-01-31 13:51 ` Tvrtko Ursulin
@ 2022-01-31 14:15 ` Mika Kuoppala
2022-02-01 9:32 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Mika Kuoppala @ 2022-01-31 14:15 UTC (permalink / raw)
To: Tvrtko Ursulin, Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> writes:
> On 28/01/2022 22:10, Michael Cheng wrote:
>> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
>> prevent compiler errors when building for non-x86 architectures.
>>
>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index 960a9aaf4f3a..90b5daf9433d 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -1647,8 +1647,8 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
>>
>> static void invalidate_csb_entries(const u64 *first, const u64 *last)
>> {
>> - clflush((void *)first);
>> - clflush((void *)last);
>> + drm_clflush_virt_range((void *)first, sizeof(*first));
>> + drm_clflush_virt_range((void *)last, sizeof(*last));
>
> How about dropping the helper and from the single call site do:
>
> drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>
> One less function call and CSB is a single cacheline before Gen11 ayway,
> two afterwards, so overall better conversion I think. How does that sound?
It would definitely work. Now trying to remember why it went into
explicit clflushes: iirc as this is gpu/cpu coherency, the
wbinvd_on_all_cpus we get with *virt_range would then be just
unnecessary perf hit.
-Mika
>
> Regards,
>
> Tvrtko
>
>> }
>>
>> /*
>>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-01-29 7:24 ` Bowman, Casey G
@ 2022-01-31 14:55 ` Tvrtko Ursulin
2022-01-31 17:02 ` Michael Cheng
1 sibling, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2022-01-31 14:55 UTC (permalink / raw)
To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
On 28/01/2022 22:10, Michael Cheng wrote:
> Use drm_clflush_virt_range instead of clflushopt and remove the memory
> barrier, since drm_clflush_virt_range takes care of that.
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 498b458fd784..0854276ff7ba 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
> static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> {
> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
> - if (flushes & CLFLUSH_BEFORE) {
> - clflushopt(addr);
> - mb();
> - }
> + if (flushes & CLFLUSH_BEFORE)
> + drm_clflush_virt_range(addr, sizeof(addr));
>
> *addr = value;
>
> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
> * to ensure ordering of clflush wrt to the system.
> */
> if (flushes & CLFLUSH_AFTER)
> - clflushopt(addr);
> + drm_clflush_virt_range(addr, sizeof(addr));
> } else
> *addr = value;
> }
Slightly annoying thing here (maybe in some other patches from the series as well) is that the change adds a function call to x86 only code path, because relocations are not supported on discrete as per:
static in
eb_validate_vma(...)
/* Relocations are disallowed for all platforms after TGL-LP. This
* also covers all platforms with local memory.
*/
if (entry->relocation_count &&
GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
return -EINVAL;
How acceptable would be, for the whole series, to introduce a static inline i915 cluflush wrapper and so be able to avoid functions calls on x86? Is this something that has been discussed and discounted already?
Regards,
Tvrtko
P.S. Hmm I am now reminded of my really old per platform build patches. With them you would be able to compile out large portions of the driver when building for ARM. Probably like a 3rd if my memory serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-01-31 14:55 ` Tvrtko Ursulin
@ 2022-01-31 17:02 ` Michael Cheng
2022-02-01 9:25 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Michael Cheng @ 2022-01-31 17:02 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
Hey Tvrtko,
Are you saying when adding drm_clflush_virt_range(addr, sizeof(addr),
this function forces an x86 code path only? If that is the case,
drm_clflush_virt_range(addr, sizeof(addr) currently has ifdefs that
seperate out x86 and powerpc, so we can add an ifdef for arm in the near
future when needed.
On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
> On 28/01/2022 22:10, Michael Cheng wrote:
>> Use drm_clflush_virt_range instead of clflushopt and remove the memory
>> barrier, since drm_clflush_virt_range takes care of that.
>>
>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> index 498b458fd784..0854276ff7ba 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
>> static void clflush_write32(u32 *addr, u32 value, unsigned int
>> flushes)
>> {
>> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
>> - if (flushes & CLFLUSH_BEFORE) {
>> - clflushopt(addr);
>> - mb();
>> - }
>> + if (flushes & CLFLUSH_BEFORE)
>> + drm_clflush_virt_range(addr, sizeof(addr));
>> *addr = value;
>> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32
>> value, unsigned int flushes)
>> * to ensure ordering of clflush wrt to the system.
>> */
>> if (flushes & CLFLUSH_AFTER)
>> - clflushopt(addr);
>> + drm_clflush_virt_range(addr, sizeof(addr));
>> } else
>> *addr = value;
>> }
>
> Slightly annoying thing here (maybe in some other patches from the
> series as well) is that the change adds a function call to x86 only
> code path, because relocations are not supported on discrete as per:
>
> static in
> eb_validate_vma(...)
> /* Relocations are disallowed for all platforms after TGL-LP.
> This
> * also covers all platforms with local memory.
> */
>
> if (entry->relocation_count &&
> GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
> return -EINVAL;
>
> How acceptable would be, for the whole series, to introduce a static
> inline i915 cluflush wrapper and so be able to avoid functions calls
> on x86? Is this something that has been discussed and discounted already?
>
> Regards,
>
> Tvrtko
>
> P.S. Hmm I am now reminded of my really old per platform build
> patches. With them you would be able to compile out large portions of
> the driver when building for ARM. Probably like a 3rd if my memory
> serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-01-31 17:02 ` Michael Cheng
@ 2022-02-01 9:25 ` Tvrtko Ursulin
2022-02-01 15:41 ` Michael Cheng
0 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2022-02-01 9:25 UTC (permalink / raw)
To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
On 31/01/2022 17:02, Michael Cheng wrote:
> Hey Tvrtko,
>
> Are you saying when adding drm_clflush_virt_range(addr, sizeof(addr),
> this function forces an x86 code path only? If that is the case,
> drm_clflush_virt_range(addr, sizeof(addr) currently has ifdefs that
> seperate out x86 and powerpc, so we can add an ifdef for arm in the near
> future when needed.
No, I was noticing that the change you are making in this patch, while
it indeed fixes a build failure, it is a code path which does not get
executed on Arm at all.
So what effectively happens is a single assembly instruction gets
replaced with a function call on all integrated GPUs up to and including
Tigerlake.
That was the slightly annoying part I was referring to and asking
whether it was discussed before.
Sadly I don't think there is a super nice solution apart from
duplicating drm_clflush_virt_range as for example i915_clflush_range and
having it static inline. That would allow the integrated GPU code path
to remain of the same performance profile, while solving the Arm
problem. However it would be code duplication so might be frowned upon.
I'd be tempted to go that route but it is something which needs a bit of
discussion if that hasn't happened already.
Regards,
Tvrtko
> On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
>> On 28/01/2022 22:10, Michael Cheng wrote:
>>> Use drm_clflush_virt_range instead of clflushopt and remove the memory
>>> barrier, since drm_clflush_virt_range takes care of that.
>>>
>>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
>>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> index 498b458fd784..0854276ff7ba 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
>>> static void clflush_write32(u32 *addr, u32 value, unsigned int
>>> flushes)
>>> {
>>> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
>>> - if (flushes & CLFLUSH_BEFORE) {
>>> - clflushopt(addr);
>>> - mb();
>>> - }
>>> + if (flushes & CLFLUSH_BEFORE)
>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>> *addr = value;
>>> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32
>>> value, unsigned int flushes)
>>> * to ensure ordering of clflush wrt to the system.
>>> */
>>> if (flushes & CLFLUSH_AFTER)
>>> - clflushopt(addr);
>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>> } else
>>> *addr = value;
>>> }
>>
>> Slightly annoying thing here (maybe in some other patches from the
>> series as well) is that the change adds a function call to x86 only
>> code path, because relocations are not supported on discrete as per:
>>
>> static in
>> eb_validate_vma(...)
>> /* Relocations are disallowed for all platforms after TGL-LP.
>> This
>> * also covers all platforms with local memory.
>> */
>>
>> if (entry->relocation_count &&
>> GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
>> return -EINVAL;
>>
>> How acceptable would be, for the whole series, to introduce a static
>> inline i915 cluflush wrapper and so be able to avoid functions calls
>> on x86? Is this something that has been discussed and discounted already?
>>
>> Regards,
>>
>> Tvrtko
>>
>> P.S. Hmm I am now reminded of my really old per platform build
>> patches. With them you would be able to compile out large portions of
>> the driver when building for ARM. Probably like a 3rd if my memory
>> serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries
2022-01-31 14:15 ` Mika Kuoppala
@ 2022-02-01 9:32 ` Tvrtko Ursulin
0 siblings, 0 replies; 22+ messages in thread
From: Tvrtko Ursulin @ 2022-02-01 9:32 UTC (permalink / raw)
To: Mika Kuoppala, Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld
On 31/01/2022 14:15, Mika Kuoppala wrote:
> Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> writes:
>
>> On 28/01/2022 22:10, Michael Cheng wrote:
>>> Re-work invalidate_csb_entries to use drm_clflush_virt_range. This will
>>> prevent compiler errors when building for non-x86 architectures.
>>>
>>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 4 ++--
>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index 960a9aaf4f3a..90b5daf9433d 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -1647,8 +1647,8 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
>>>
>>> static void invalidate_csb_entries(const u64 *first, const u64 *last)
>>> {
>>> - clflush((void *)first);
>>> - clflush((void *)last);
>>> + drm_clflush_virt_range((void *)first, sizeof(*first));
>>> + drm_clflush_virt_range((void *)last, sizeof(*last));
>>
>> How about dropping the helper and from the single call site do:
>>
>> drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
>>
>> One less function call and CSB is a single cacheline before Gen11 ayway,
>> two afterwards, so overall better conversion I think. How does that sound?
>
> It would definitely work. Now trying to remember why it went into
> explicit clflushes: iirc as this is gpu/cpu coherency, the
> wbinvd_on_all_cpus we get with *virt_range would then be just
> unnecessary perf hit.
Right, apart that AFAICS wbinvd_on_all_cpus does not run on the
X86_FEATURE_CLFLUSH path of drm_clflush_virt_range, which made me think
invalidate_csb_entries might have been an a) optimisation which used the
knowledge CSB is at most two cachelines large, and b) there is no need
for the memory barrier since as you say it is about CPU/GPU effect so
CPU ordering is not a concern.
Anyway, larger hammer probably does not harm much, apart that it really
should be one call to drm_clflush_virt_range.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-02-01 9:25 ` Tvrtko Ursulin
@ 2022-02-01 15:41 ` Michael Cheng
2022-02-01 16:32 ` Tvrtko Ursulin
0 siblings, 1 reply; 22+ messages in thread
From: Michael Cheng @ 2022-02-01 15:41 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
Ah, thanks for the clarification! While discussion goes on about the
route you suggested, could we land these patches (after addressing the
reviews) to unblock compiling i915 on arm?
On 2022-02-01 1:25 a.m., Tvrtko Ursulin wrote:
>
> On 31/01/2022 17:02, Michael Cheng wrote:
>> Hey Tvrtko,
>>
>> Are you saying when adding drm_clflush_virt_range(addr, sizeof(addr),
>> this function forces an x86 code path only? If that is the case,
>> drm_clflush_virt_range(addr, sizeof(addr) currently has ifdefs that
>> seperate out x86 and powerpc, so we can add an ifdef for arm in the
>> near future when needed.
>
> No, I was noticing that the change you are making in this patch, while
> it indeed fixes a build failure, it is a code path which does not get
> executed on Arm at all.
>
> So what effectively happens is a single assembly instruction gets
> replaced with a function call on all integrated GPUs up to and
> including Tigerlake.
>
> That was the slightly annoying part I was referring to and asking
> whether it was discussed before.
>
> Sadly I don't think there is a super nice solution apart from
> duplicating drm_clflush_virt_range as for example i915_clflush_range
> and having it static inline. That would allow the integrated GPU code
> path to remain of the same performance profile, while solving the Arm
> problem. However it would be code duplication so might be frowned upon.
>
> I'd be tempted to go that route but it is something which needs a bit
> of discussion if that hasn't happened already.
>
> Regards,
>
> Tvrtko
>
>> On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
>>> On 28/01/2022 22:10, Michael Cheng wrote:
>>>> Use drm_clflush_virt_range instead of clflushopt and remove the memory
>>>> barrier, since drm_clflush_virt_range takes care of that.
>>>>
>>>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
>>>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>> index 498b458fd784..0854276ff7ba 100644
>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
>>>> static void clflush_write32(u32 *addr, u32 value, unsigned int
>>>> flushes)
>>>> {
>>>> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
>>>> - if (flushes & CLFLUSH_BEFORE) {
>>>> - clflushopt(addr);
>>>> - mb();
>>>> - }
>>>> + if (flushes & CLFLUSH_BEFORE)
>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>> *addr = value;
>>>> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32
>>>> value, unsigned int flushes)
>>>> * to ensure ordering of clflush wrt to the system.
>>>> */
>>>> if (flushes & CLFLUSH_AFTER)
>>>> - clflushopt(addr);
>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>> } else
>>>> *addr = value;
>>>> }
>>>
>>> Slightly annoying thing here (maybe in some other patches from the
>>> series as well) is that the change adds a function call to x86 only
>>> code path, because relocations are not supported on discrete as per:
>>>
>>> static in
>>> eb_validate_vma(...)
>>> /* Relocations are disallowed for all platforms after
>>> TGL-LP. This
>>> * also covers all platforms with local memory.
>>> */
>>>
>>> if (entry->relocation_count &&
>>> GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
>>> return -EINVAL;
>>>
>>> How acceptable would be, for the whole series, to introduce a static
>>> inline i915 cluflush wrapper and so be able to avoid functions calls
>>> on x86? Is this something that has been discussed and discounted
>>> already?
>>>
>>> Regards,
>>>
>>> Tvrtko
>>>
>>> P.S. Hmm I am now reminded of my really old per platform build
>>> patches. With them you would be able to compile out large portions
>>> of the driver when building for ARM. Probably like a 3rd if my
>>> memory serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-02-01 15:41 ` Michael Cheng
@ 2022-02-01 16:32 ` Tvrtko Ursulin
2022-02-02 16:35 ` Michael Cheng
0 siblings, 1 reply; 22+ messages in thread
From: Tvrtko Ursulin @ 2022-02-01 16:32 UTC (permalink / raw)
To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
On 01/02/2022 15:41, Michael Cheng wrote:
> Ah, thanks for the clarification! While discussion goes on about the
> route you suggested, could we land these patches (after addressing the
> reviews) to unblock compiling i915 on arm?
I am 60-40 to no, since follow up can be hard. I'd prefer a little bit
of discussion before merging.
Also, what will be the Arm implementation of drm_clflush_virt_range?
Noob question - why is i915 the only driver calling it? Do other GPUs
never need to flush CPU cache?
Regards,
Tvrtko
> On 2022-02-01 1:25 a.m., Tvrtko Ursulin wrote:
>>
>> On 31/01/2022 17:02, Michael Cheng wrote:
>>> Hey Tvrtko,
>>>
>>> Are you saying when adding drm_clflush_virt_range(addr, sizeof(addr),
>>> this function forces an x86 code path only? If that is the case,
>>> drm_clflush_virt_range(addr, sizeof(addr) currently has ifdefs that
>>> seperate out x86 and powerpc, so we can add an ifdef for arm in the
>>> near future when needed.
>>
>> No, I was noticing that the change you are making in this patch, while
>> it indeed fixes a build failure, it is a code path which does not get
>> executed on Arm at all.
>>
>> So what effectively happens is a single assembly instruction gets
>> replaced with a function call on all integrated GPUs up to and
>> including Tigerlake.
>>
>> That was the slightly annoying part I was referring to and asking
>> whether it was discussed before.
>>
>> Sadly I don't think there is a super nice solution apart from
>> duplicating drm_clflush_virt_range as for example i915_clflush_range
>> and having it static inline. That would allow the integrated GPU code
>> path to remain of the same performance profile, while solving the Arm
>> problem. However it would be code duplication so might be frowned upon.
>>
>> I'd be tempted to go that route but it is something which needs a bit
>> of discussion if that hasn't happened already.
>>
>> Regards,
>>
>> Tvrtko
>>
>>> On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
>>>> On 28/01/2022 22:10, Michael Cheng wrote:
>>>>> Use drm_clflush_virt_range instead of clflushopt and remove the memory
>>>>> barrier, since drm_clflush_virt_range takes care of that.
>>>>>
>>>>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
>>>>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>> index 498b458fd784..0854276ff7ba 100644
>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
>>>>> static void clflush_write32(u32 *addr, u32 value, unsigned int
>>>>> flushes)
>>>>> {
>>>>> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
>>>>> - if (flushes & CLFLUSH_BEFORE) {
>>>>> - clflushopt(addr);
>>>>> - mb();
>>>>> - }
>>>>> + if (flushes & CLFLUSH_BEFORE)
>>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>>> *addr = value;
>>>>> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32
>>>>> value, unsigned int flushes)
>>>>> * to ensure ordering of clflush wrt to the system.
>>>>> */
>>>>> if (flushes & CLFLUSH_AFTER)
>>>>> - clflushopt(addr);
>>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>>> } else
>>>>> *addr = value;
>>>>> }
>>>>
>>>> Slightly annoying thing here (maybe in some other patches from the
>>>> series as well) is that the change adds a function call to x86 only
>>>> code path, because relocations are not supported on discrete as per:
>>>>
>>>> static in
>>>> eb_validate_vma(...)
>>>> /* Relocations are disallowed for all platforms after
>>>> TGL-LP. This
>>>> * also covers all platforms with local memory.
>>>> */
>>>>
>>>> if (entry->relocation_count &&
>>>> GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
>>>> return -EINVAL;
>>>>
>>>> How acceptable would be, for the whole series, to introduce a static
>>>> inline i915 cluflush wrapper and so be able to avoid functions calls
>>>> on x86? Is this something that has been discussed and discounted
>>>> already?
>>>>
>>>> Regards,
>>>>
>>>> Tvrtko
>>>>
>>>> P.S. Hmm I am now reminded of my really old per platform build
>>>> patches. With them you would be able to compile out large portions
>>>> of the driver when building for ARM. Probably like a 3rd if my
>>>> memory serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32
2022-02-01 16:32 ` Tvrtko Ursulin
@ 2022-02-02 16:35 ` Michael Cheng
0 siblings, 0 replies; 22+ messages in thread
From: Michael Cheng @ 2022-02-02 16:35 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: lucas.demarchi, matthew.auld, mika.kuoppala
As far as I know, we haven't gotten to the arm implementation yet, since
we are trying to get i915 compile for arm without using random ifdefs
and dummy functions.
"Noob question - why is i915 the only driver calling it? Do other GPUs
never need to flush CPU cache?"
Unfortunately I don't have enough expertise to comfortable answer this
question. Maybe someone else can chime in here? Lucas? Matt?
On 2022-02-01 8:32 a.m., Tvrtko Ursulin wrote:
>
> On 01/02/2022 15:41, Michael Cheng wrote:
>> Ah, thanks for the clarification! While discussion goes on about the
>> route you suggested, could we land these patches (after addressing
>> the reviews) to unblock compiling i915 on arm?
>
> I am 60-40 to no, since follow up can be hard. I'd prefer a little bit
> of discussion before merging.
>
> Also, what will be the Arm implementation of drm_clflush_virt_range?
> Noob question - why is i915 the only driver calling it? Do other GPUs
> never need to flush CPU cache?
>
> Regards,
>
> Tvrtko
>
>> On 2022-02-01 1:25 a.m., Tvrtko Ursulin wrote:
>>>
>>> On 31/01/2022 17:02, Michael Cheng wrote:
>>>> Hey Tvrtko,
>>>>
>>>> Are you saying when adding drm_clflush_virt_range(addr,
>>>> sizeof(addr), this function forces an x86 code path only? If that
>>>> is the case, drm_clflush_virt_range(addr, sizeof(addr) currently
>>>> has ifdefs that seperate out x86 and powerpc, so we can add an
>>>> ifdef for arm in the near future when needed.
>>>
>>> No, I was noticing that the change you are making in this patch,
>>> while it indeed fixes a build failure, it is a code path which does
>>> not get executed on Arm at all.
>>>
>>> So what effectively happens is a single assembly instruction gets
>>> replaced with a function call on all integrated GPUs up to and
>>> including Tigerlake.
>>>
>>> That was the slightly annoying part I was referring to and asking
>>> whether it was discussed before.
>>>
>>> Sadly I don't think there is a super nice solution apart from
>>> duplicating drm_clflush_virt_range as for example i915_clflush_range
>>> and having it static inline. That would allow the integrated GPU
>>> code path to remain of the same performance profile, while solving
>>> the Arm problem. However it would be code duplication so might be
>>> frowned upon.
>>>
>>> I'd be tempted to go that route but it is something which needs a
>>> bit of discussion if that hasn't happened already.
>>>
>>> Regards,
>>>
>>> Tvrtko
>>>
>>>> On 2022-01-31 6:55 a.m., Tvrtko Ursulin wrote:
>>>>> On 28/01/2022 22:10, Michael Cheng wrote:
>>>>>> Use drm_clflush_virt_range instead of clflushopt and remove the
>>>>>> memory
>>>>>> barrier, since drm_clflush_virt_range takes care of that.
>>>>>>
>>>>>> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
>>>>>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>>> index 498b458fd784..0854276ff7ba 100644
>>>>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>>>>> @@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma
>>>>>> *vma,
>>>>>> static void clflush_write32(u32 *addr, u32 value, unsigned int
>>>>>> flushes)
>>>>>> {
>>>>>> if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
>>>>>> - if (flushes & CLFLUSH_BEFORE) {
>>>>>> - clflushopt(addr);
>>>>>> - mb();
>>>>>> - }
>>>>>> + if (flushes & CLFLUSH_BEFORE)
>>>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>>>> *addr = value;
>>>>>> @@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr,
>>>>>> u32 value, unsigned int flushes)
>>>>>> * to ensure ordering of clflush wrt to the system.
>>>>>> */
>>>>>> if (flushes & CLFLUSH_AFTER)
>>>>>> - clflushopt(addr);
>>>>>> + drm_clflush_virt_range(addr, sizeof(addr));
>>>>>> } else
>>>>>> *addr = value;
>>>>>> }
>>>>>
>>>>> Slightly annoying thing here (maybe in some other patches from the
>>>>> series as well) is that the change adds a function call to x86
>>>>> only code path, because relocations are not supported on discrete
>>>>> as per:
>>>>>
>>>>> static in
>>>>> eb_validate_vma(...)
>>>>> /* Relocations are disallowed for all platforms after
>>>>> TGL-LP. This
>>>>> * also covers all platforms with local memory.
>>>>> */
>>>>>
>>>>> if (entry->relocation_count &&
>>>>> GRAPHICS_VER(eb->i915) >= 12 && !IS_TIGERLAKE(eb->i915))
>>>>> return -EINVAL;
>>>>>
>>>>> How acceptable would be, for the whole series, to introduce a
>>>>> static inline i915 cluflush wrapper and so be able to avoid
>>>>> functions calls on x86? Is this something that has been discussed
>>>>> and discounted already?
>>>>>
>>>>> Regards,
>>>>>
>>>>> Tvrtko
>>>>>
>>>>> P.S. Hmm I am now reminded of my really old per platform build
>>>>> patches. With them you would be able to compile out large portions
>>>>> of the driver when building for ARM. Probably like a 3rd if my
>>>>> memory serves me right.
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2022-02-02 16:35 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-28 22:10 [Intel-gfx] [PATCH v2 0/4] Use drm_clflush* instead of clflush Michael Cheng
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-01-29 7:21 ` Bowman, Casey G
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/gt: Re-work invalidate_csb_entries Michael Cheng
2022-01-29 7:21 ` Bowman, Casey G
2022-01-31 13:51 ` Tvrtko Ursulin
2022-01-31 14:15 ` Mika Kuoppala
2022-02-01 9:32 ` Tvrtko Ursulin
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-01-29 7:23 ` Bowman, Casey G
2022-01-28 22:10 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-01-29 7:24 ` Bowman, Casey G
2022-01-31 14:55 ` Tvrtko Ursulin
2022-01-31 17:02 ` Michael Cheng
2022-02-01 9:25 ` Tvrtko Ursulin
2022-02-01 15:41 ` Michael Cheng
2022-02-01 16:32 ` Tvrtko Ursulin
2022-02-02 16:35 ` Michael Cheng
2022-01-28 22:31 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev2) Patchwork
2022-01-28 22:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-28 22:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-29 3:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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