* [PATCH v9 0/6] Use drm_clflush* instead of clflush
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
v9: Rebased
Michael Cheng (6):
drm: Add arch arm64 for drm_clflush_virt_range
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 5 +++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
.../drm/i915/gt/intel_execlists_submission.c | 19 ++++++-------------
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
8 files changed, 27 insertions(+), 36 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 0/6] Use drm_clflush* instead of clflush
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
This patch series re-work a few i915 functions to use drm_clflush_virt_range
instead of calling clflush or clflushopt directly. This will prevent errors
when building for non-x86 architectures.
v2: s/PAGE_SIZE/sizeof(value) for Re-work intel_write_status_page and added
more patches to convert additional clflush/clflushopt to use drm_clflush*.
(Michael Cheng)
v3: Drop invalidate_csb_entries and directly invoke drm_clflush_virt_ran
v4: Remove extra memory barriers
v5: s/cache_clflush_range/drm_clflush_virt_range
v6: Fix up "Drop invalidate_csb_entries" to use correct parameters. Also
added in arm64 support for drm_clflush_virt_range.
v7: Re-order patches, and use correct macro for dcache flush for arm64.
v8: Remove ifdef for asm/cacheflush.
v9: Rebased
Michael Cheng (6):
drm: Add arch arm64 for drm_clflush_virt_range
drm/i915/gt: Re-work intel_write_status_page
drm/i915/gt: Drop invalidate_csb_entries
drm/i915/gt: Re-work reset_csb
drm/i915/: Re-work clflush_write32
drm/i915/gt: replace cache_clflush_range
drivers/gpu/drm/drm_cache.c | 5 +++++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
.../drm/i915/gt/intel_execlists_submission.c | 19 ++++++-------------
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
8 files changed, 27 insertions(+), 36 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/drm_cache.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..ec8d91b088ff 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
*/
+#include <asm/cacheflush.h>
#include <linux/cc_platform.h>
#include <linux/export.h>
#include <linux/highmem.h>
@@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
performs a flush by first performing a clean, follow by an invalidation
operation.
v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
dcache.
v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
v4 (Michael Cheng): Rebase
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/drm_cache.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
index 66597e411764..ec8d91b088ff 100644
--- a/drivers/gpu/drm/drm_cache.c
+++ b/drivers/gpu/drm/drm_cache.c
@@ -28,6 +28,7 @@
* Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
*/
+#include <asm/cacheflush.h>
#include <linux/cc_platform.h>
#include <linux/export.h>
#include <linux/highmem.h>
@@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
if (wbinvd_on_all_cpus())
pr_err("Timed out waiting for cache flush\n");
+
+#elif defined(CONFIG_ARM64)
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
#else
WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 2/6] drm/i915/gt: Re-work intel_write_status_page
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 2/6] drm/i915/gt: Re-work intel_write_status_page
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Re-work intel_write_status_page to use drm_clflush_virt_range. This
will prevent compiler errors when building for non-x86 architectures.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 0e353d8c2bc8..986777c2430d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -4,6 +4,7 @@
#include <asm/cacheflush.h>
#include <drm/drm_util.h>
+#include <drm/drm_cache.h>
#include <linux/hashtable.h>
#include <linux/irq_work.h>
@@ -143,15 +144,9 @@ intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
* of extra paranoia to try and ensure that the HWS takes the value
* we give and that it doesn't end up trapped inside the CPU!
*/
- if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
- mb();
- clflush(&engine->status_page.addr[reg]);
- engine->status_page.addr[reg] = value;
- clflush(&engine->status_page.addr[reg]);
- mb();
- } else {
- WRITE_ONCE(engine->status_page.addr[reg], value);
- }
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
+ WRITE_ONCE(engine->status_page.addr[reg], value);
+ drm_clflush_virt_range(&engine->status_page.addr[reg], sizeof(value));
}
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 3/6] drm/i915/gt: Drop invalidate_csb_entries
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..28f2581d3046 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size * sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 3/6] drm/i915/gt: Drop invalidate_csb_entries
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Drop invalidate_csb_entries and directly call drm_clflush_virt_range.
This allows for one less function call, and prevent complier errors when
building for non-x86 architectures.
v2(Michael Cheng): Drop invalidate_csb_entries function and directly
invoke drm_clflush_virt_range. Thanks to Tvrtko for the
sugguestion.
v3(Michael Cheng): Use correct parameters for drm_clflush_virt_range.
Thanks to Tvrtko for pointing this out.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9bb7c863172f..28f2581d3046 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1646,12 +1646,6 @@ cancel_port_requests(struct intel_engine_execlists * const execlists,
return inactive;
}
-static void invalidate_csb_entries(const u64 *first, const u64 *last)
-{
- clflush((void *)first);
- clflush((void *)last);
-}
-
/*
* Starting with Gen12, the status has a new format:
*
@@ -1999,7 +1993,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
* the wash as hardware, working or not, will need to do the
* invalidation before.
*/
- invalidate_csb_entries(&buf[0], &buf[num_entries - 1]);
+ drm_clflush_virt_range(&buf[0], num_entries * sizeof(buf[0]));
/*
* We assume that any event reflects a change in context flow
@@ -2783,8 +2777,8 @@ static void reset_csb_pointers(struct intel_engine_cs *engine)
/* Check that the GPU does indeed update the CSB entries! */
memset(execlists->csb_status, -1, (reset_value + 1) * sizeof(u64));
- invalidate_csb_entries(&execlists->csb_status[0],
- &execlists->csb_status[reset_value]);
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size * sizeof(execlists->csb_status[0]));
/* Once more for luck and our trusty paranoia */
ENGINE_WRITE(engine, RING_CONTEXT_STATUS_PTR,
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 4/6] drm/i915/gt: Re-work reset_csb
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 28f2581d3046..cc561cfae808 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 4/6] drm/i915/gt: Re-work reset_csb
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 28f2581d3046..cc561cfae808 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 5/6] drm/i915/: Re-work clflush_write32
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 5/6] drm/i915/: Re-work clflush_write32
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Use drm_clflush_virt_range instead of clflushopt and remove the memory
barrier, since drm_clflush_virt_range takes care of that.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..0854276ff7ba 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1332,10 +1332,8 @@ static void *reloc_vaddr(struct i915_vma *vma,
static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
{
if (unlikely(flushes & (CLFLUSH_BEFORE | CLFLUSH_AFTER))) {
- if (flushes & CLFLUSH_BEFORE) {
- clflushopt(addr);
- mb();
- }
+ if (flushes & CLFLUSH_BEFORE)
+ drm_clflush_virt_range(addr, sizeof(addr));
*addr = value;
@@ -1347,7 +1345,7 @@ static void clflush_write32(u32 *addr, u32 value, unsigned int flushes)
* to ensure ordering of clflush wrt to the system.
*/
if (flushes & CLFLUSH_AFTER)
- clflushopt(addr);
+ drm_clflush_virt_range(addr, sizeof(addr));
} else
*addr = value;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v9 6/6] drm/i915/gt: replace cache_clflush_range
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 1:26 ` Michael Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx
Cc: tvrtko.ursulin, michael.cheng, balasubramani.vivekanandan,
wayne.boyer, casey.g.bowman, lucas.demarchi, dri-devel
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
}
} while (1);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx;
}
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
- clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+ drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index cc561cfae808..bbe33794b34d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
- clflush_cache_range(&vaddr[idx], sizeof(u64));
+ drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
}
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v9 6/6] drm/i915/gt: replace cache_clflush_range
@ 2022-02-10 1:26 ` Michael Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Michael Cheng @ 2022-02-10 1:26 UTC (permalink / raw)
To: intel-gfx; +Cc: michael.cheng, lucas.demarchi, dri-devel
Replace all occurance of cache_clflush_range with
drm_clflush_virt_range. This will prevent compile errors on non-x86
platforms.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
5 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index c43e724afa9f..d0999e92621b 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -444,11 +444,11 @@ gen8_ppgtt_insert_pte(struct i915_ppgtt *ppgtt,
pd = pdp->entry[gen8_pd_index(idx, 2)];
}
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
}
} while (1);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
return idx;
}
@@ -532,7 +532,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
}
} while (rem >= page_size && index < I915_PDES);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
/*
* Is it safe to mark the 2M block as 64K? -- Either we have
@@ -548,7 +548,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
I915_GTT_PAGE_SIZE_2M)))) {
vaddr = px_vaddr(pd);
vaddr[maybe_64K] |= GEN8_PDE_IPS_64K;
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
page_size = I915_GTT_PAGE_SIZE_64K;
/*
@@ -569,7 +569,7 @@ static void gen8_ppgtt_insert_huge(struct i915_address_space *vm,
for (i = 1; i < index; i += 16)
memset64(vaddr + i, encode, 15);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
}
@@ -617,7 +617,7 @@ static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
- clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+ drm_clflush_virt_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
}
static int gen8_init_scratch(struct i915_address_space *vm)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index cc561cfae808..bbe33794b34d 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2822,7 +2822,7 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 0d6bbc8c57f2..9b594be9102f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -255,7 +255,7 @@ fill_page_dma(struct drm_i915_gem_object *p, const u64 val, unsigned int count)
void *vaddr = __px_vaddr(p);
memset64(vaddr, val, count);
- clflush_cache_range(vaddr, PAGE_SIZE);
+ drm_clflush_virt_range(vaddr, PAGE_SIZE);
}
static void poison_scratch_page(struct drm_i915_gem_object *scratch)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 48e6e2f87700..bd474a5123cb 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -90,7 +90,7 @@ write_dma_entry(struct drm_i915_gem_object * const pdma,
u64 * const vaddr = __px_vaddr(pdma);
vaddr[idx] = encoded_entry;
- clflush_cache_range(&vaddr[idx], sizeof(u64));
+ drm_clflush_virt_range(&vaddr[idx], sizeof(u64));
}
void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index b3a429a92c0d..89020706adc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3573,7 +3573,7 @@ static void guc_sanitize(struct intel_engine_cs *engine)
sanitize_hwsp(engine);
/* And scrub the dirty cachelines for the HWSP */
- clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+ drm_clflush_virt_range(engine->status_page.addr, PAGE_SIZE);
intel_engine_reset_pinned_contexts(engine);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev8)
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
` (6 preceding siblings ...)
(?)
@ 2022-02-10 1:38 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-02-10 1:38 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev8)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3bb116c416b9 drm: Add arch arm64 for drm_clflush_virt_range
-:27: WARNING:INCLUDE_LINUX: Use #include <linux/cacheflush.h> instead of <asm/cacheflush.h>
#27: FILE: drivers/gpu/drm/drm_cache.c:31:
+#include <asm/cacheflush.h>
-:38: WARNING:LINE_SPACING: Missing a blank line after declarations
#38: FILE: drivers/gpu/drm/drm_cache.c:181:
+ void *end = addr + length;
+ dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
total: 0 errors, 2 warnings, 0 checks, 17 lines checked
5860a6b50357 drm/i915/gt: Re-work intel_write_status_page
b88c0d0c2e11 drm/i915/gt: Drop invalidate_csb_entries
-:52: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#52: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2781:
+ drm_clflush_virt_range(&execlists->csb_status[0],
+ execlists->csb_size * sizeof(execlists->csb_status[0]));
total: 0 errors, 0 warnings, 1 checks, 30 lines checked
808c2aa68876 drm/i915/gt: Re-work reset_csb
-:28: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#28: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2948:
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
total: 0 errors, 0 warnings, 1 checks, 11 lines checked
c0184abcc96a drm/i915/: Re-work clflush_write32
705b5b446b71 drm/i915/gt: replace cache_clflush_range
-:6: WARNING:TYPO_SPELLING: 'occurance' may be misspelled - perhaps 'occurrence'?
#6:
Replace all occurance of cache_clflush_range with
^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 77 lines checked
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Use drm_clflush* instead of clflush (rev8)
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
` (7 preceding siblings ...)
(?)
@ 2022-02-10 1:39 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-02-10 1:39 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev8)
URL : https://patchwork.freedesktop.org/series/99450/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Use drm_clflush* instead of clflush (rev8)
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
` (8 preceding siblings ...)
(?)
@ 2022-02-10 2:12 ` Patchwork
-1 siblings, 0 replies; 19+ messages in thread
From: Patchwork @ 2022-02-10 2:12 UTC (permalink / raw)
To: Michael Cheng; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5942 bytes --]
== Series Details ==
Series: Use drm_clflush* instead of clflush (rev8)
URL : https://patchwork.freedesktop.org/series/99450/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11207 -> Patchwork_22231
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22231 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22231, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/index.html
Participating hosts (45 -> 42)
------------------------------
Additional (1): bat-rpls-1
Missing (4): fi-bsw-cyan fi-icl-u2 shard-tglu fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22231:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0@smem:
- fi-glk-dsi: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-glk-dsi/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-glk-dsi/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-rkl-guc: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_22231 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@bad-flink:
- fi-skl-6600u: [PASS][5] -> [INCOMPLETE][6] ([i915#4547])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][7] -> [DMESG-FAIL][8] ([i915#4494] / [i915#4957])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][9] ([i915#3921])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@vga-edid-read:
- fi-bdw-5557u: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][11] -> [DMESG-WARN][12] ([i915#4269])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#295]) +12 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][15] ([fdo#109271]) +13 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- fi-kbl-soraka: [INCOMPLETE][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11207/fi-kbl-soraka/igt@i915_selftest@live@requests.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/fi-kbl-soraka/igt@i915_selftest@live@requests.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
Build changes
-------------
* Linux: CI_DRM_11207 -> Patchwork_22231
CI-20190529: 20190529
CI_DRM_11207: 0d650d738ee924dc0c367ff1f33c61237a635933 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6342: 1bd167a3af9e8f6168ac89c64c64b929694d9be7 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22231: 705b5b446b718efd8016a50cf66899795ed6f169 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
705b5b446b71 drm/i915/gt: replace cache_clflush_range
c0184abcc96a drm/i915/: Re-work clflush_write32
808c2aa68876 drm/i915/gt: Re-work reset_csb
b88c0d0c2e11 drm/i915/gt: Drop invalidate_csb_entries
5860a6b50357 drm/i915/gt: Re-work intel_write_status_page
3bb116c416b9 drm: Add arch arm64 for drm_clflush_virt_range
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22231/index.html
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^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
@ 2022-02-10 10:31 ` Tvrtko Ursulin
-1 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2022-02-10 10:31 UTC (permalink / raw)
To: Michael Cheng, intel-gfx; +Cc: lucas.demarchi, dri-devel
On 10/02/2022 01:26, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
>
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> dcache.
>
> v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
>
> v4 (Michael Cheng): Rebase
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/drm_cache.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 66597e411764..ec8d91b088ff 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
> */
>
> +#include <asm/cacheflush.h>
I thought linux/cacheflush.h would be correct.
Regards,
Tvrtko
> #include <linux/cc_platform.h>
> #include <linux/export.h>
> #include <linux/highmem.h>
> @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> + void *end = addr + length;
> + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
> #else
> WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
> #endif
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range
@ 2022-02-10 10:31 ` Tvrtko Ursulin
0 siblings, 0 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2022-02-10 10:31 UTC (permalink / raw)
To: Michael Cheng, intel-gfx
Cc: balasubramani.vivekanandan, wayne.boyer, casey.g.bowman,
lucas.demarchi, dri-devel
On 10/02/2022 01:26, Michael Cheng wrote:
> Add arm64 support for drm_clflush_virt_range. dcache_clean_inval_poc
> performs a flush by first performing a clean, follow by an invalidation
> operation.
>
> v2 (Michael Cheng): Use correct macro for cleaning and invalidation the
> dcache.
>
> v3 (Michael Cheng): Remove ifdef for asm/cacheflush.h
>
> v4 (Michael Cheng): Rebase
>
> Signed-off-by: Michael Cheng <michael.cheng@intel.com>
> ---
> drivers/gpu/drm/drm_cache.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c
> index 66597e411764..ec8d91b088ff 100644
> --- a/drivers/gpu/drm/drm_cache.c
> +++ b/drivers/gpu/drm/drm_cache.c
> @@ -28,6 +28,7 @@
> * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
> */
>
> +#include <asm/cacheflush.h>
I thought linux/cacheflush.h would be correct.
Regards,
Tvrtko
> #include <linux/cc_platform.h>
> #include <linux/export.h>
> #include <linux/highmem.h>
> @@ -174,6 +175,10 @@ drm_clflush_virt_range(void *addr, unsigned long length)
>
> if (wbinvd_on_all_cpus())
> pr_err("Timed out waiting for cache flush\n");
> +
> +#elif defined(CONFIG_ARM64)
> + void *end = addr + length;
> + dcache_clean_inval_poc((unsigned long)addr, (unsigned long)end);
> #else
> WARN_ONCE(1, "Architecture has no drm_cache.c support\n");
> #endif
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2022-02-10 10:32 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 1:26 [PATCH v9 0/6] Use drm_clflush* instead of clflush Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:26 ` [PATCH v9 1/6] drm: Add arch arm64 for drm_clflush_virt_range Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 10:31 ` Tvrtko Ursulin
2022-02-10 10:31 ` Tvrtko Ursulin
2022-02-10 1:26 ` [PATCH v9 2/6] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:26 ` [PATCH v9 3/6] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:26 ` [PATCH v9 4/6] drm/i915/gt: Re-work reset_csb Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:26 ` [PATCH v9 5/6] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:26 ` [PATCH v9 6/6] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-10 1:26 ` [Intel-gfx] " Michael Cheng
2022-02-10 1:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use drm_clflush* instead of clflush (rev8) Patchwork
2022-02-10 1:39 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-10 2:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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