From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8104BC433F5 for ; Sat, 9 Apr 2022 01:29:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240474AbiDIBbW (ORCPT ); Fri, 8 Apr 2022 21:31:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240393AbiDIBaZ (ORCPT ); Fri, 8 Apr 2022 21:30:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F363193F1; Fri, 8 Apr 2022 18:27:42 -0700 (PDT) Date: Sat, 09 Apr 2022 01:27:40 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1649467661; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DIamPipLa2HMu6qbtf3UAGy0nEC+13pjmiWwezcteHo=; b=KK9DrPC2KKMlNIwhkIlT31lDTJjxg/QBUTSjCyMc3ywPzshFDDlq14k+BvQvGXk27eVnZP JJ+N9l8/Vg5D7yc6VnRlyKXeegiyQumurr6d2L1j98+3Cbmh0Ih0NNWEusLexl+6seQoOd iTFHqju1qVcTVJf9Qw7rHGz+KJVWcBjD+e7+Jn+kTV5yazfw/StH6y9NJFqUuBueaIbtp6 uREPtsInAgkvAX2FRmVkE/fCmF246DlmMNWOpW5LtugLS1waOsdnFbRF6yQT6g7f9deMCR zYLnHQAzTCP/hVlTRxFZ2CBwuf2DPTCK//10yVoO/ULEdPMmFe7q3CXXmDGDsg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1649467661; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DIamPipLa2HMu6qbtf3UAGy0nEC+13pjmiWwezcteHo=; b=JhzzKNfpp8uMuONtbhimo2MAq3Fozn+FNKpTV36wPB1LKT53XssOPnwg1Rwx6ggByB/Zj0 IFLRUmxN06bu3/Cg== From: "tip-bot2 for Kirill A. Shutemov" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/tdx] x86/tdx: Exclude shared bit from __PHYSICAL_MASK Cc: Kuppuswamy Sathyanarayanan , "Kirill A. Shutemov" , Dave Hansen , Andi Kleen , Tony Luck , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220405232939.73860-6-kirill.shutemov@linux.intel.com> References: <20220405232939.73860-6-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Message-ID: <164946766003.4207.16570460228314176239.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/tdx branch of tip: Commit-ID: 65fab5bc033aad1a9faf976caec46558c2f88319 Gitweb: https://git.kernel.org/tip/65fab5bc033aad1a9faf976caec46558c2f88319 Author: Kirill A. Shutemov AuthorDate: Wed, 06 Apr 2022 02:29:14 +03:00 Committer: Dave Hansen CommitterDate: Thu, 07 Apr 2022 08:27:51 -07:00 x86/tdx: Exclude shared bit from __PHYSICAL_MASK In TDX guests, by default memory is protected from host access. If a guest needs to communicate with the VMM (like the I/O use case), it uses a single bit in the physical address to communicate the protected/shared attribute of the given page. In the x86 ARCH code, __PHYSICAL_MASK macro represents the width of the physical address in the given architecture. It is used in creating physical PAGE_MASK for address bits in the kernel. Since in TDX guest, a single bit is used as metadata, it needs to be excluded from valid physical address bits to avoid using incorrect addresses bits in the kernel. Enable DYNAMIC_PHYSICAL_MASK to support updating the __PHYSICAL_MASK. Co-developed-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Reviewed-by: Andi Kleen Reviewed-by: Tony Luck Reviewed-by: Thomas Gleixner Link: https://lkml.kernel.org/r/20220405232939.73860-6-kirill.shutemov@linux.intel.com --- arch/x86/Kconfig | 1 + arch/x86/coco/tdx/tdx.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 984315c..aea4cc4 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -883,6 +883,7 @@ config INTEL_TDX_GUEST depends on X86_64 && CPU_SUP_INTEL depends on X86_X2APIC select ARCH_HAS_CC_PLATFORM + select DYNAMIC_PHYSICAL_MASK help Support running as a guest under Intel TDX. Without this support, the guest kernel can not boot or run under TDX. diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 96b2611..e84f6dd 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -89,5 +89,13 @@ void __init tdx_early_init(void) cc_mask = get_cc_mask(); cc_set_mask(cc_mask); + /* + * All bits above GPA width are reserved and kernel treats shared bit + * as flag, not as part of physical address. + * + * Adjust physical mask to only cover valid GPA bits. + */ + physical_mask &= cc_mask - 1; + pr_info("Guest detected\n"); }