Patch Details
Series:drm/i915: Start reordering modeset clock calculations (rev4)
URL:https://patchwork.freedesktop.org/series/101789/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/index.html

CI Bug Log - changes from CI_DRM_11497 -> Patchwork_101789v4

Summary

FAILURE

Serious unknown changes coming with Patchwork_101789v4 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_101789v4, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v4/index.html

Participating hosts (39 -> 45)

Additional (9): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-rpls-1 bat-rpls-2 bat-jsl-1
Missing (3): fi-bsw-cyan bat-jsl-2 fi-bdw-samus

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_101789v4:

IGT changes

Possible regressions

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

Known issues

Here are the changes found in Patchwork_101789v4 that come from known issues:

CI changes

Possible fixes

IGT changes

Issues hit

Possible fixes

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_11497: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6420: a3885810ccc0ce9e6552a20c910a0a322eca466c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_101789v4: d883cffbf2383a96420fd6dc099056295de24a12 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

8bcbf1a105f0 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
657d62592078 drm/i915: Clean up DPLL related debugs
6620e6ec0c7f drm/i915: Do .crtc_compute_clock() earlier
15abcdf728b5 drm/i915: Split shared dpll .get_dplls() into compute and get phases
e040f7af5409 drm/i915: Add crtc .crtc_get_shared_dpll()
7bc23b9fd1e3 drm/i915: Split out dg2_crtc_compute_clock()
dc2a3124a12b drm/i915: Clear the dpll_hw_state when disabling a pipe
1a3d3d447b9f drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
0c9c9bad8151 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
1dfb11c67732 drm/i915: Adjust .crtc_compute_clock() calling convention
835043046151 drm/i915: Remove pointless dpll_funcs checks
bb8310aa0f7c drm/i915: Pass dev_priv to intel_shared_dpll_init()
6f8661ef40a9 drm/i915: Make .get_dplls() return int