Patch Details
Series:drm/i915: Start reordering modeset clock calculations (rev5)
URL:https://patchwork.freedesktop.org/series/101789/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/index.html

CI Bug Log - changes from CI_DRM_11536 -> Patchwork_101789v5

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_101789v5/index.html

Participating hosts (45 -> 45)

Additional (2): fi-cml-u2 bat-dg2-8
Missing (2): fi-hsw-4770 fi-bsw-cyan

Known issues

Here are the changes found in Patchwork_101789v5 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Build changes

CI-20190529: 20190529
CI_DRM_11536: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6444: df584c804e3a44431b0e5ae21c190b6e9acb35ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_101789v5: c4d0bd916d243bad13ce7d4c3a7a00a50e13b73d @ git://anongit.freedesktop.org/gfx-ci/linux

Linux commits

0f670a39fa21 drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
a886e4ec3c73 drm/i915: Clean up DPLL related debugs
1eb7712774b4 drm/i915: Do .crtc_compute_clock() earlier
1857e0fd77d8 drm/i915: Split shared dpll .get_dplls() into compute and get phases
b84885d61b59 drm/i915: Add crtc .crtc_get_shared_dpll()
b218554272e7 drm/i915: Split out dg2_crtc_compute_clock()
e63de3d4a8d5 drm/i915: Clear the dpll_hw_state when disabling a pipe
d09c0685dd19 drm/i915: Move the dpll_hw_state clearing to intel_dpll_crtc_compute_clock()
4037d50836e8 drm/i915: Move stuff into intel_dpll_crtc_compute_clock()
1c5adb67ff46 drm/i915: Adjust .crtc_compute_clock() calling convention
1f49c2d7f8bb drm/i915: Remove pointless dpll_funcs checks
262e89722be2 drm/i915: Pass dev_priv to intel_shared_dpll_init()
a5bfbf68789c drm/i915: Make .get_dplls() return int