* [PATCH 0/2] i915: Turn on compute engine support
@ 2022-04-22 19:50 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the uapi enum and add the CCS engines to the engine lists for the
Xe_HP SDV and DG2.
Userspace (both Mesa and compute drivers) are linked in the ABI patch.
Existing IGT tests (e.g., i915_hangman) provide test coverage for
general engine behavior since compute engines should follow the same
general rules as other engines. We've also recently added some
additional subtests like igt@gem_reset_stats@shared-reset-domain to
cover the user-visible impacts of the compute engines sharing the same
hardware reset domain as the render engine.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Daniele Ceraolo Spurio (1):
drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
Matt Roper (1):
drm/i915/xehp: Add compute engine ABI
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
6 files changed, 64 insertions(+), 10 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 0/2] i915: Turn on compute engine support
@ 2022-04-22 19:50 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, dri-devel
Now that the necessary GuC-based hardware workarounds have landed, we're
finally ready to actually enable compute engines for use by userspace.
All of the "under-the-hood" heavy lifting already landed a while back in
other series so all that remains now is to add I915_ENGINE_CLASS_COMPUTE
to the uapi enum and add the CCS engines to the engine lists for the
Xe_HP SDV and DG2.
Userspace (both Mesa and compute drivers) are linked in the ABI patch.
Existing IGT tests (e.g., i915_hangman) provide test coverage for
general engine behavior since compute engines should follow the same
general rules as other engines. We've also recently added some
additional subtests like igt@gem_reset_stats@shared-reset-domain to
cover the user-visible impacts of the compute engines sharing the same
hardware reset domain as the render engine.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Daniele Ceraolo Spurio (1):
drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
Matt Roper (1):
drm/i915/xehp: Add compute engine ABI
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
6 files changed, 64 insertions(+), 10 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
@ 2022-04-22 19:50 ` Matt Roper
-1 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx
Cc: Tvrtko Ursulin, Jordan Justen, dri-devel, Daniele Ceraolo Spurio,
Szymon Morek, Vinay Belgaumkar
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other
engine types as well.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 0f6cd96b459f..46a174f8aa00 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
+ [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
};
static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 92394f13b42f..c96e123496a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
[VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
[VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
[COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
+ [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
};
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 475a6f824cad..18d38cb59923 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_COPY] = "copy",
[I915_ENGINE_CLASS_VIDEO] = "video",
[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+ [I915_ENGINE_CLASS_COMPUTE] = "compute",
};
static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
index 5f5b02b01ba0..f796c5e8e060 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -13,7 +13,7 @@
#include "gt/intel_engine_types.h"
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
+#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
struct drm_i915_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 35ca528803fd..a2def7b27009 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -154,21 +154,71 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
--
2.35.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-22 19:50 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Szymon Morek
We're now ready to start exposing compute engines to userspace.
While we're at it, let's extend the kerneldoc description for the other
engine types as well.
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Szymon Morek <szymon.morek@intel.com>
UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
UMD (compute): https://github.com/intel/compute-runtime/pull/451
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.c | 1 +
drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 0f6cd96b459f..46a174f8aa00 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
[COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
[VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
[VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
- /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
+ [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
};
static int engine_cmp(void *priv, const struct list_head *A,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 92394f13b42f..c96e123496a5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
[VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
[VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
[COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
+ [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
};
struct drm_i915_private *i915 = gt->i915;
struct intel_uncore *uncore = gt->uncore;
diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
index 475a6f824cad..18d38cb59923 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.c
+++ b/drivers/gpu/drm/i915/i915_drm_client.c
@@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
[I915_ENGINE_CLASS_COPY] = "copy",
[I915_ENGINE_CLASS_VIDEO] = "video",
[I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
+ [I915_ENGINE_CLASS_COMPUTE] = "compute",
};
static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
index 5f5b02b01ba0..f796c5e8e060 100644
--- a/drivers/gpu/drm/i915/i915_drm_client.h
+++ b/drivers/gpu/drm/i915/i915_drm_client.h
@@ -13,7 +13,7 @@
#include "gt/intel_engine_types.h"
-#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
+#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
struct drm_i915_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 35ca528803fd..a2def7b27009 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -154,21 +154,71 @@ enum i915_mocs_table_index {
I915_MOCS_CACHED,
};
-/*
+/**
+ * enum drm_i915_gem_engine_class - uapi engine type enumeration
+ *
* Different engines serve different roles, and there may be more than one
- * engine serving each role. enum drm_i915_gem_engine_class provides a
- * classification of the role of the engine, which may be used when requesting
- * operations to be performed on a certain subset of engines, or for providing
- * information about that group.
+ * engine serving each role. This enum provides a classification of the role
+ * of the engine, which may be used when requesting operations to be performed
+ * on a certain subset of engines, or for providing information about that
+ * group.
*/
enum drm_i915_gem_engine_class {
+ /**
+ * @I915_ENGINE_CLASS_RENDER:
+ *
+ * Render engines support instructions used for 3D, Compute (GPGPU),
+ * and programmable media workloads. These instructions fetch data and
+ * dispatch individual work items to threads that operate in parallel.
+ * The threads run small programs (called "kernels" or "shaders") on
+ * the GPU's execution units (EUs).
+ */
I915_ENGINE_CLASS_RENDER = 0,
+
+ /**
+ * @I915_ENGINE_CLASS_COPY:
+ *
+ * Copy engines (also referred to as "blitters") support instructions
+ * that move blocks of data from one location in memory to another,
+ * or that fill a specified location of memory with fixed data.
+ * Copy engines can perform pre-defined logical or bitwise operations
+ * on the source, destination, or pattern data.
+ */
I915_ENGINE_CLASS_COPY = 1,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO:
+ *
+ * Video engines (also referred to as "bit stream decode" (BSD) or
+ * "vdbox") support instructions that perform fixed-function media
+ * decode and encode.
+ */
I915_ENGINE_CLASS_VIDEO = 2,
+
+ /**
+ * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
+ *
+ * Video enhancement engines (also referred to as "vebox") support
+ * instructions related to image enhancement.
+ */
I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
- /* should be kept compact */
+ /**
+ * @I915_ENGINE_CLASS_COMPUTE:
+ *
+ * Compute engines support a subset of the instructions available
+ * on render engines: compute engines support Compute (GPGPU) and
+ * programmable media workloads, but do not support the 3D pipeline.
+ */
+ I915_ENGINE_CLASS_COMPUTE = 4,
+
+ /* Values in this enum should be kept compact. */
+ /**
+ * @I915_ENGINE_CLASS_INVALID:
+ *
+ * Placeholder value to represent an invalid engine class assignment.
+ */
I915_ENGINE_CLASS_INVALID = -1
};
--
2.35.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
@ 2022-04-22 19:50 ` Matt Roper
-1 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx; +Cc: Vinay Belgaumkar, Daniele Ceraolo Spurio, dri-devel
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b60492826478..7739d6c33481 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
- BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+ BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
};
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
- BIT(VCS0) | BIT(VCS2)
+ BIT(VCS0) | BIT(VCS2) | \
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
--
2.35.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
@ 2022-04-22 19:50 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 19:50 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b60492826478..7739d6c33481 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1037,7 +1037,8 @@ static const struct intel_device_info xehpsdv_info = {
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
BIT(VCS0) | BIT(VCS1) | BIT(VCS2) | BIT(VCS3) |
- BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7),
+ BIT(VCS4) | BIT(VCS5) | BIT(VCS6) | BIT(VCS7) |
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3),
.require_force_probe = 1,
};
@@ -1056,7 +1057,8 @@ static const struct intel_device_info xehpsdv_info = {
.platform_engine_mask = \
BIT(RCS0) | BIT(BCS0) | \
BIT(VECS0) | BIT(VECS1) | \
- BIT(VCS0) | BIT(VCS2)
+ BIT(VCS0) | BIT(VCS2) | \
+ BIT(CCS0) | BIT(CCS1) | BIT(CCS2) | BIT(CCS3)
static const struct intel_device_info dg2_info = {
DG2_FEATURES,
--
2.35.1
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (2 preceding siblings ...)
(?)
@ 2022-04-22 20:20 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-22 20:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Turn on compute engine support
URL : https://patchwork.freedesktop.org/series/103011/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Turn on compute engine support
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (3 preceding siblings ...)
(?)
@ 2022-04-22 20:47 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-22 20:47 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10218 bytes --]
== Series Details ==
Series: i915: Turn on compute engine support
URL : https://patchwork.freedesktop.org/series/103011/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11544 -> Patchwork_103011v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103011v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103011v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/index.html
Participating hosts (45 -> 43)
------------------------------
Missing (2): fi-kbl-soraka fi-bsw-cyan
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103011v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_pm_rpm@module-reload:
- bat-dg1-5: [PASS][1] -> [SKIP][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/bat-dg1-5/igt@i915_pm_rpm@module-reload.html
New tests
---------
New tests have been introduced between CI_DRM_11544 and Patchwork_103011v1:
### New IGT tests (24) ###
* igt@gem_exec_basic@basic@ccs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs1-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs1-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs3-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs3-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fence@basic-await@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-busy@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-busy@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-busy@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-busy@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-wait@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@nb-await@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
* igt@gem_exec_fence@nb-await@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
* igt@gem_exec_fence@nb-await@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@nb-await@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.08] s
Known issues
------------
Here are the changes found in Patchwork_103011v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_pm:
- fi-tgl-1115g4: [PASS][3] -> [DMESG-FAIL][4] ([i915#3987])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-tgl-1115g4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][5] -> [INCOMPLETE][6] ([i915#4785])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [PASS][7] -> [INCOMPLETE][8] ([i915#3921])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
- fi-ivb-3770: [PASS][9] -> [INCOMPLETE][10] ([i915#3303] / [i915#5370])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][11] ([i915#4312])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-bdw-5557u/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312] / [i915#5594])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-hsw-4770/igt@runner@aborted.html
- fi-ivb-3770: NOTRUN -> [FAIL][13] ([fdo#109271] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-ivb-3770/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}: [DMESG-WARN][14] ([i915#4391]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
* igt@dmabuf@all@dma_fence_chain:
- bat-dg1-5: [INCOMPLETE][16] ([i915#4154]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][18] ([i915#146]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][20] ([i915#2940]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][22] ([i915#4494] / [i915#4957]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][24] -> [PASS][25] +17 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/fi-tgl-dsi/igt@i915_selftest@live@perf.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {bat-adlp-6}: [DMESG-WARN][26] ([i915#3576]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4154]: https://gitlab.freedesktop.org/drm/intel/issues/4154
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5338]: https://gitlab.freedesktop.org/drm/intel/issues/5338
[i915#5370]: https://gitlab.freedesktop.org/drm/intel/issues/5370
[i915#5552]: https://gitlab.freedesktop.org/drm/intel/issues/5552
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
Build changes
-------------
* Linux: CI_DRM_11544 -> Patchwork_103011v1
CI-20190529: 20190529
CI_DRM_11544: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6449: 704da775abb83faa9324a665fe2992ab90f4ab03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103011v1: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
462bcb7b6fba drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
a6ce1dee38a9 drm/i915/xehp: Add compute engine ABI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v1/index.html
[-- Attachment #2: Type: text/html, Size: 11897 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev2)
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (4 preceding siblings ...)
(?)
@ 2022-04-22 21:32 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-22 21:32 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Turn on compute engine support (rev2)
URL : https://patchwork.freedesktop.org/series/103011/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Turn on compute engine support (rev2)
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (5 preceding siblings ...)
(?)
@ 2022-04-22 22:07 ` Patchwork
2022-04-22 22:33 ` Matt Roper
-1 siblings, 1 reply; 27+ messages in thread
From: Patchwork @ 2022-04-22 22:07 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 9960 bytes --]
== Series Details ==
Series: i915: Turn on compute engine support (rev2)
URL : https://patchwork.freedesktop.org/series/103011/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11544 -> Patchwork_103011v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103011v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103011v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/index.html
Participating hosts (45 -> 43)
------------------------------
Additional (1): bat-dg2-8
Missing (3): fi-kbl-soraka bat-adlm-1 fi-bsw-cyan
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103011v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gem_contexts:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
New tests
---------
New tests have been introduced between CI_DRM_11544 and Patchwork_103011v2:
### New IGT tests (24) ###
* igt@gem_exec_basic@basic@ccs0-lmem0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs0-smem:
- Statuses : 2 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_basic@basic@ccs1-lmem0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs1-smem:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-lmem0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-smem:
- Statuses : 2 pass(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_basic@basic@ccs3-lmem0:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs3-smem:
- Statuses : 2 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fence@basic-await@ccs0:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.10] s
* igt@gem_exec_fence@basic-await@ccs1:
- Statuses : 2 pass(s)
- Exec time: [0.10, 0.12] s
* igt@gem_exec_fence@basic-await@ccs2:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.11] s
* igt@gem_exec_fence@basic-await@ccs3:
- Statuses : 2 pass(s)
- Exec time: [0.09, 0.10] s
* igt@gem_exec_fence@basic-busy@ccs0:
- Statuses : 2 pass(s)
- Exec time: [0.03, 0.04] s
* igt@gem_exec_fence@basic-busy@ccs1:
- Statuses : 2 pass(s)
- Exec time: [0.03, 0.04] s
* igt@gem_exec_fence@basic-busy@ccs2:
- Statuses : 2 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-busy@ccs3:
- Statuses : 2 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-wait@ccs0:
- Statuses : 2 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-wait@ccs1:
- Statuses : 2 pass(s)
- Exec time: [0.03, 0.04] s
* igt@gem_exec_fence@basic-wait@ccs2:
- Statuses : 2 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-wait@ccs3:
- Statuses : 2 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@nb-await@ccs0:
- Statuses : 2 pass(s)
- Exec time: [0.06, 0.09] s
* igt@gem_exec_fence@nb-await@ccs1:
- Statuses : 2 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@nb-await@ccs2:
- Statuses : 2 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@nb-await@ccs3:
- Statuses : 2 pass(s)
- Exec time: [0.07] s
Known issues
------------
Here are the changes found in Patchwork_103011v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][2] -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +14 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}: [DMESG-WARN][6] ([i915#4391]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
* igt@dmabuf@all@dma_fence_chain:
- bat-dg1-5: [INCOMPLETE][8] ([i915#4154]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][10] ([i915#146]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][14] -> [PASS][15] +17 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-tgl-dsi/igt@i915_selftest@live@perf.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {bat-adlp-6}: [DMESG-WARN][16] ([i915#3576]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4154]: https://gitlab.freedesktop.org/drm/intel/issues/4154
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
Build changes
-------------
* Linux: CI_DRM_11544 -> Patchwork_103011v2
CI-20190529: 20190529
CI_DRM_11544: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6449: 704da775abb83faa9324a665fe2992ab90f4ab03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103011v2: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
228895dda988 drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
743bf0812329 drm/i915/xehp: Add compute engine ABI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/index.html
[-- Attachment #2: Type: text/html, Size: 9938 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for i915: Turn on compute engine support (rev2)
2022-04-22 22:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-04-22 22:33 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-22 22:33 UTC (permalink / raw)
To: intel-gfx
On Fri, Apr 22, 2022 at 10:07:00PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: i915: Turn on compute engine support (rev2)
> URL : https://patchwork.freedesktop.org/series/103011/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_11544 -> Patchwork_103011v2
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_103011v2 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_103011v2, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/index.html
>
> Participating hosts (45 -> 43)
> ------------------------------
>
> Additional (1): bat-dg2-8
> Missing (3): fi-kbl-soraka bat-adlm-1 fi-bsw-cyan
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_103011v2:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live@gem_contexts:
> - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][1]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@i915_selftest@live@gem_contexts.html
Random incomplete on BDW which wouldn't have been impacted by compute
engine support (which only exists on Xe_HP and beyond). Looks like
there was an incomplete from this test on DG1 a few weeks ago at
https://gitlab.freedesktop.org/drm/intel/-/issues/5458, but it's unclear
if it's related since the logs there have expired.
Submitting a re-test.
Matt
>
>
> New tests
> ---------
>
> New tests have been introduced between CI_DRM_11544 and Patchwork_103011v2:
>
> ### New IGT tests (24) ###
>
> * igt@gem_exec_basic@basic@ccs0-lmem0:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_basic@basic@ccs0-smem:
> - Statuses : 2 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_basic@basic@ccs1-lmem0:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_basic@basic@ccs1-smem:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_basic@basic@ccs2-lmem0:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_basic@basic@ccs2-smem:
> - Statuses : 2 pass(s)
> - Exec time: [0.0, 0.00] s
>
> * igt@gem_exec_basic@basic@ccs3-lmem0:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_basic@basic@ccs3-smem:
> - Statuses : 2 pass(s)
> - Exec time: [0.0] s
>
> * igt@gem_exec_fence@basic-await@ccs0:
> - Statuses : 2 pass(s)
> - Exec time: [0.09, 0.10] s
>
> * igt@gem_exec_fence@basic-await@ccs1:
> - Statuses : 2 pass(s)
> - Exec time: [0.10, 0.12] s
>
> * igt@gem_exec_fence@basic-await@ccs2:
> - Statuses : 2 pass(s)
> - Exec time: [0.09, 0.11] s
>
> * igt@gem_exec_fence@basic-await@ccs3:
> - Statuses : 2 pass(s)
> - Exec time: [0.09, 0.10] s
>
> * igt@gem_exec_fence@basic-busy@ccs0:
> - Statuses : 2 pass(s)
> - Exec time: [0.03, 0.04] s
>
> * igt@gem_exec_fence@basic-busy@ccs1:
> - Statuses : 2 pass(s)
> - Exec time: [0.03, 0.04] s
>
> * igt@gem_exec_fence@basic-busy@ccs2:
> - Statuses : 2 pass(s)
> - Exec time: [0.04] s
>
> * igt@gem_exec_fence@basic-busy@ccs3:
> - Statuses : 2 pass(s)
> - Exec time: [0.03] s
>
> * igt@gem_exec_fence@basic-wait@ccs0:
> - Statuses : 2 pass(s)
> - Exec time: [0.03] s
>
> * igt@gem_exec_fence@basic-wait@ccs1:
> - Statuses : 2 pass(s)
> - Exec time: [0.03, 0.04] s
>
> * igt@gem_exec_fence@basic-wait@ccs2:
> - Statuses : 2 pass(s)
> - Exec time: [0.03] s
>
> * igt@gem_exec_fence@basic-wait@ccs3:
> - Statuses : 2 pass(s)
> - Exec time: [0.03] s
>
> * igt@gem_exec_fence@nb-await@ccs0:
> - Statuses : 2 pass(s)
> - Exec time: [0.06, 0.09] s
>
> * igt@gem_exec_fence@nb-await@ccs1:
> - Statuses : 2 pass(s)
> - Exec time: [0.09] s
>
> * igt@gem_exec_fence@nb-await@ccs2:
> - Statuses : 2 pass(s)
> - Exec time: [0.09] s
>
> * igt@gem_exec_fence@nb-await@ccs3:
> - Statuses : 2 pass(s)
> - Exec time: [0.07] s
>
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_103011v2 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@i915_selftest@live@hangcheck:
> - bat-dg1-5: [PASS][2] -> [DMESG-FAIL][3] ([i915#4494] / [i915#4957])
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_chamelium@dp-crc-fast:
> - fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
>
> * igt@kms_setmode@basic-clone-single-crtc:
> - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +14 similar issues
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html
>
>
> #### Possible fixes ####
>
> * igt@core_hotunplug@unbind-rebind:
> - {bat-rpls-2}: [DMESG-WARN][6] ([i915#4391]) -> [PASS][7]
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
>
> * igt@dmabuf@all@dma_fence_chain:
> - bat-dg1-5: [INCOMPLETE][8] ([i915#4154]) -> [PASS][9]
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
>
> * igt@gem_exec_suspend@basic-s3@smem:
> - fi-bdw-5557u: [INCOMPLETE][10] ([i915#146]) -> [PASS][11]
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
>
> * igt@i915_selftest@live@execlists:
> - fi-bsw-n3050: [INCOMPLETE][12] ([i915#2940]) -> [PASS][13]
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
>
> * igt@i915_selftest@live@perf:
> - {fi-tgl-dsi}: [DMESG-WARN][14] -> [PASS][15] +17 similar issues
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-tgl-dsi/igt@i915_selftest@live@perf.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/fi-tgl-dsi/igt@i915_selftest@live@perf.html
>
> * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
> - {bat-adlp-6}: [DMESG-WARN][16] ([i915#3576]) -> [PASS][17]
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
> [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
> [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
> [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
> [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
> [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
> [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
> [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
> [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
> [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
> [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4154]: https://gitlab.freedesktop.org/drm/intel/issues/4154
> [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
> [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
> [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
> [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
> [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
> [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
> [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
> [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
> [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
> [i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
> [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
> [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
> [i915#5356]: https://gitlab.freedesktop.org/drm/intel/issues/5356
> [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_11544 -> Patchwork_103011v2
>
> CI-20190529: 20190529
> CI_DRM_11544: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6449: 704da775abb83faa9324a665fe2992ab90f4ab03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_103011v2: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
>
>
> ### Linux commits
>
> 228895dda988 drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
> 743bf0812329 drm/i915/xehp: Add compute engine ABI
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v2/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev3)
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (6 preceding siblings ...)
(?)
@ 2022-04-22 23:02 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-22 23:02 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: i915: Turn on compute engine support (rev3)
URL : https://patchwork.freedesktop.org/series/103011/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for i915: Turn on compute engine support (rev3)
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (7 preceding siblings ...)
(?)
@ 2022-04-22 23:24 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-22 23:24 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8105 bytes --]
== Series Details ==
Series: i915: Turn on compute engine support (rev3)
URL : https://patchwork.freedesktop.org/series/103011/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11544 -> Patchwork_103011v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/index.html
Participating hosts (45 -> 42)
------------------------------
Missing (3): fi-kbl-soraka bat-adlm-1 fi-bsw-cyan
New tests
---------
New tests have been introduced between CI_DRM_11544 and Patchwork_103011v3:
### New IGT tests (24) ###
* igt@gem_exec_basic@basic@ccs0-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs0-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs1-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs1-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs2-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs3-lmem0:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_basic@basic@ccs3-smem:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@gem_exec_fence@basic-await@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-await@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.09] s
* igt@gem_exec_fence@basic-busy@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-busy@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-busy@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@basic-busy@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.04] s
* igt@gem_exec_fence@basic-wait@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.03] s
* igt@gem_exec_fence@nb-await@ccs0:
- Statuses : 1 pass(s)
- Exec time: [0.06] s
* igt@gem_exec_fence@nb-await@ccs1:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
* igt@gem_exec_fence@nb-await@ccs2:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
* igt@gem_exec_fence@nb-await@ccs3:
- Statuses : 1 pass(s)
- Exec time: [0.07] s
Known issues
------------
Here are the changes found in Patchwork_103011v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][1] -> [DMESG-FAIL][2] ([i915#4494] / [i915#4957])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- fi-hsw-4770: [PASS][3] -> [INCOMPLETE][4] ([i915#4785])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-guc: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-kbl-guc/igt@kms_force_connector_basic@force-load-detect.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][6] ([i915#4312])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-bdw-5557u/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#4312] / [i915#5594])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}: [DMESG-WARN][8] ([i915#4391]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
* igt@dmabuf@all@dma_fence_chain:
- bat-dg1-5: [INCOMPLETE][10] ([i915#4154]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/bat-dg1-5/igt@dmabuf@all@dma_fence_chain.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][12] ([i915#146]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [INCOMPLETE][14] ([i915#2940]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@perf:
- {fi-tgl-dsi}: [DMESG-WARN][16] -> [PASS][17] +17 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/fi-tgl-dsi/igt@i915_selftest@live@perf.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/fi-tgl-dsi/igt@i915_selftest@live@perf.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- {bat-adlp-6}: [DMESG-WARN][18] ([i915#3576]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#4154]: https://gitlab.freedesktop.org/drm/intel/issues/4154
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5594]: https://gitlab.freedesktop.org/drm/intel/issues/5594
Build changes
-------------
* Linux: CI_DRM_11544 -> Patchwork_103011v3
CI-20190529: 20190529
CI_DRM_11544: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6449: 704da775abb83faa9324a665fe2992ab90f4ab03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103011v3: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
96d4bde2d5da drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
562875ded3f1 drm/i915/xehp: Add compute engine ABI
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/index.html
[-- Attachment #2: Type: text/html, Size: 9776 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: Turn on compute engine support (rev3)
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
` (8 preceding siblings ...)
(?)
@ 2022-04-23 1:18 ` Patchwork
-1 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2022-04-23 1:18 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 44872 bytes --]
== Series Details ==
Series: i915: Turn on compute engine support (rev3)
URL : https://patchwork.freedesktop.org/series/103011/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11544_full -> Patchwork_103011v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103011v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103011v3_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 11)
------------------------------
Missing (1): shard-rkl
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103011v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@drm_mm@all@replace:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl1/igt@drm_mm@all@replace.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl8/igt@drm_mm@all@replace.html
* igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180:
- shard-iclb: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180.html
* igt@kms_invalid_mode@clock-too-high:
- shard-kbl: [PASS][4] -> [INCOMPLETE][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-kbl1/igt@kms_invalid_mode@clock-too-high.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl1/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-edp-1-scaler-with-clipping-clamping:
- shard-iclb: [PASS][6] -> [INCOMPLETE][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-edp-1-scaler-with-clipping-clamping.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb2/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-edp-1-scaler-with-clipping-clamping.html
#### Warnings ####
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs:
- shard-tglb: [SKIP][8] ([i915#3689]) -> [INCOMPLETE][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-tglb6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-tglb8/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_ccs.html
Known issues
------------
Here are the changes found in Patchwork_103011v3_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-apl: ([PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34]) -> ([PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51], [FAIL][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59]) ([i915#4386])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl1/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl1/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl1/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl1/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl8/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl8/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl8/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl7/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl7/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl6/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl6/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl2/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl6/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl6/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl3/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl4/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl4/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl4/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl6/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl6/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl6/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl8/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl8/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl8/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl1/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl1/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl1/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl2/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl2/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl2/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl3/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl3/boot.html
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][60] -> [SKIP][61] ([i915#658])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb2/igt@feature_discovery@psr2.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb4/igt@feature_discovery@psr2.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-glk: NOTRUN -> [SKIP][62] ([fdo#109271]) +135 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109314])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [PASS][64] -> [SKIP][65] ([i915#4525])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][66] -> [FAIL][67] ([i915#2842]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-kbl6/igt@gem_exec_fair@basic-none@vcs0.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
- shard-glk: [PASS][68] -> [FAIL][69] ([i915#2842])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: NOTRUN -> [FAIL][70] ([i915#2842]) +3 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk9/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][71] -> [FAIL][72] ([i915#2849])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][73] ([i915#2190])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#4613]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@random:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4613])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@gem_lmem_swapping@random.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#4613])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_pwrite@basic-exhaustion:
- shard-skl: NOTRUN -> [WARN][77] ([i915#2658])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][78] ([i915#768])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][79] -> [DMESG-WARN][80] ([i915#180])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl8/igt@gem_softpin@noreloc-s3.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl6/igt@gem_softpin@noreloc-s3.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-iclb: NOTRUN -> [SKIP][81] ([i915#2856])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109293] / [fdo#109506])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@i915_pm_rpm@pc8-residency.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#3826])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][84] ([i915#5286]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#110725] / [fdo#111614])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-glk: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3777]) +3 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3777]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][88] ([fdo#109278] / [i915#3886]) +4 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#3886]) +7 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#3886]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3886]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl8/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109278]) +20 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@kms_ccs@pipe-d-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-skl: NOTRUN -> [SKIP][93] ([fdo#109271] / [fdo#111827]) +3 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][94] ([fdo#109271] / [fdo#111827]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@kms_chamelium@vga-hpd.html
* igt@kms_color@pipe-d-ctm-0-5:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278] / [i915#1149])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_color@pipe-d-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271] / [fdo#111827]) +12 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk1/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109284] / [fdo#111827]) +6 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@uevent:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109300] / [fdo#111066])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-snb: [PASS][100] -> [SKIP][101] ([fdo#109271]) +6 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-snb2/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-snb2/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109278] / [fdo#109279]) +2 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen:
- shard-kbl: NOTRUN -> [SKIP][103] ([fdo#109271]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-left-edge:
- shard-apl: NOTRUN -> [SKIP][104] ([fdo#109271]) +38 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@kms_cursor_edge_walk@pipe-d-128x128-left-edge.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109274] / [fdo#109278]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_dp_tiled_display@basic-test-pattern:
- shard-iclb: NOTRUN -> [SKIP][106] ([i915#426])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@kms_dp_tiled_display@basic-test-pattern.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled:
- shard-iclb: NOTRUN -> [SKIP][107] ([i915#5287])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-4tiled.html
* igt@kms_dsc@xrgb8888-dsc-compression:
- shard-iclb: NOTRUN -> [SKIP][108] ([i915#3828])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_dsc@xrgb8888-dsc-compression.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-glk: NOTRUN -> [FAIL][109] ([i915#4767])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-iclb: NOTRUN -> [SKIP][110] ([fdo#109274]) +4 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][111] -> [FAIL][112] ([i915#2122])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-hdmi-a1-hdmi-a2.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk3/igt@kms_flip@2x-plain-flip-ts-check-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [FAIL][113] ([i915#2122])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_flip@2x-wf_vblank-ts-check-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][114] -> [FAIL][115] ([i915#79])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [PASS][116] -> [FAIL][117] ([i915#2122])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl10/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl6/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109280]) +9 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-suspend:
- shard-skl: [PASS][119] -> [INCOMPLETE][120] ([i915#123])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl10/igt@kms_frontbuffer_tracking@psr-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html
* igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a:
- shard-skl: [PASS][121] -> [FAIL][122] ([i915#1188])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl1/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl1/igt@kms_hdr@bpc-switch-dpms@bpc-switch-dpms-edp-1-pipe-a.html
* igt@kms_hdr@static-toggle-dpms:
- shard-iclb: NOTRUN -> [SKIP][123] ([i915#3555])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_invalid_mode@clock-too-high:
- shard-skl: NOTRUN -> [SKIP][124] ([fdo#109271]) +43 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@kms_invalid_mode@clock-too-high.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-glk: NOTRUN -> [FAIL][125] ([i915#265])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][126] -> [FAIL][127] ([fdo#108145] / [i915#265])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: NOTRUN -> [FAIL][128] ([fdo#108145] / [i915#265]) +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: NOTRUN -> [SKIP][129] ([i915#3536])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: NOTRUN -> [SKIP][130] ([i915#5235]) +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_plane_scaling@upscale-with-rotation-20x20@pipe-a-edp-1-upscale-with-rotation:
- shard-iclb: NOTRUN -> [SKIP][131] ([i915#5176]) +5 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_plane_scaling@upscale-with-rotation-20x20@pipe-a-edp-1-upscale-with-rotation.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][132] ([fdo#109271] / [i915#658])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [PASS][133] -> [SKIP][134] ([fdo#109441]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109441])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-glk: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#2437])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk1/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][137] ([fdo#109271] / [i915#2437])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl4/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-iclb: NOTRUN -> [SKIP][138] ([i915#2530])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@perf@gen12-mi-rpc:
- shard-iclb: NOTRUN -> [SKIP][139] ([fdo#109289])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@perf@gen12-mi-rpc.html
* igt@prime_nv_api@nv_self_import_to_different_fd:
- shard-iclb: NOTRUN -> [SKIP][140] ([fdo#109291]) +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@prime_nv_api@nv_self_import_to_different_fd.html
* igt@sysfs_clients@create:
- shard-glk: NOTRUN -> [SKIP][141] ([fdo#109271] / [i915#2994]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk1/igt@sysfs_clients@create.html
* igt@sysfs_clients@fair-0:
- shard-iclb: NOTRUN -> [SKIP][142] ([i915#2994])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@sysfs_clients@fair-0.html
* igt@sysfs_heartbeat_interval@precise@vecs0:
- shard-apl: [PASS][143] -> [FAIL][144] ([i915#1755])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/igt@sysfs_heartbeat_interval@precise@vecs0.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl2/igt@sysfs_heartbeat_interval@precise@vecs0.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl: [INCOMPLETE][145] ([i915#4939]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl4/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][147] ([i915#2846]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [FAIL][149] ([i915#2842]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk6/igt@gem_exec_fair@basic-none-share@rcs0.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][151] ([i915#2842]) -> [PASS][152]
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/igt@gem_exec_fair@basic-none@vecs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl4/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][153] ([i915#2842]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_partial_pwrite_pread@write-display:
- shard-skl: [DMESG-WARN][155] ([i915#1982]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl10/igt@gem_partial_pwrite_pread@write-display.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl1/igt@gem_partial_pwrite_pread@write-display.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [DMESG-WARN][157] ([i915#5566] / [i915#716]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk1/igt@gen9_exec_parse@allowed-single.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk9/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@cursor:
- shard-iclb: [INCOMPLETE][159] ([i915#5096]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb7/igt@i915_pm_rpm@cursor.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@i915_pm_rpm@cursor.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][161] ([i915#180]) -> [PASS][162] +1 similar issue
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][163] ([i915#2346] / [i915#533]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [FAIL][165] ([i915#2346]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
- shard-apl: [FAIL][167] ([i915#79]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][169] ([i915#2122]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][171] ([i915#4911]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-glk5/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][173] -> [PASS][174] +1 similar issue
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [INCOMPLETE][175] ([i915#4444]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_lowres@pipe-b-tiling-none:
- shard-snb: [SKIP][177] ([fdo#109271]) -> [PASS][178] +2 similar issues
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-snb2/igt@kms_plane_lowres@pipe-b-tiling-none.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-snb2/igt@kms_plane_lowres@pipe-b-tiling-none.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][179] ([fdo#109441]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- {shard-tglu}: [DMESG-WARN][181] -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-tglu-1/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-tglu-3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [FAIL][183] ([i915#232]) -> [TIMEOUT][184] ([i915#3063] / [i915#3648])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-tglb1/igt@gem_eio@unwedge-stress.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-tglb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel:
- shard-iclb: [DMESG-WARN][185] ([i915#5614]) -> [SKIP][186] ([i915#4525]) +1 similar issue
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb4/igt@gem_exec_balancer@parallel.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb8/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][187] ([i915#4525]) -> [DMESG-WARN][188] ([i915#5614]) +1 similar issue
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][189] ([i915#2842]) -> [FAIL][190] ([i915#2852])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][191] ([i915#4767]) -> [INCOMPLETE][192] ([i915#180])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][193] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][194] ([i915#4148])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11544/shard-iclb8/igt@kms_psr2_su@page_flip-p010.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3648]: https://gitlab.freedesktop.org/drm/intel/issues/3648
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3777]: https://gitlab.freedesktop.org/drm/intel/issues/3777
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4148]: https://gitlab.freedesktop.org/drm/intel/issues/4148
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4444]: https://gitlab.freedesktop.org/drm/intel/issues/4444
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5096]: https://gitlab.freedesktop.org/drm/intel/issues/5096
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11544 -> Patchwork_103011v3
CI-20190529: 20190529
CI_DRM_11544: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6449: 704da775abb83faa9324a665fe2992ab90f4ab03 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103011v3: 5f9019934f9819738661f0618a29865abed617f4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103011v3/index.html
[-- Attachment #2: Type: text/html, Size: 50522 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
@ 2022-04-25 10:41 ` Tvrtko Ursulin
-1 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2022-04-25 10:41 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Cc: Vinay Belgaumkar, Daniele Ceraolo Spurio, Szymon Morek,
dri-devel, Jordan Justen
On 22/04/2022 20:50, Matt Roper wrote:
> We're now ready to start exposing compute engines to userspace.
>
> While we're at it, let's extend the kerneldoc description for the other
> engine types as well.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for
xehp" but content of which seems more about engine query, including the
yet non-existent distance query (and more)?! I certainly does not appear
to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs
clarifying.
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> 5 files changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 0f6cd96b459f..46a174f8aa00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 92394f13b42f..c96e123496a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
Do you know what 0xcf04 is?
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
might need adjusting to always select bit 0 for any compute engine
instance. Not sure how hardware would behave if value other than '1'
would be written into 0xced8.
Regards,
Tvrtko
> };
> struct drm_i915_private *i915 = gt->i915;
> struct intel_uncore *uncore = gt->uncore;
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> index 475a6f824cad..18d38cb59923 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.c
> +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> [I915_ENGINE_CLASS_COPY] = "copy",
> [I915_ENGINE_CLASS_VIDEO] = "video",
> [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> };
>
> static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> index 5f5b02b01ba0..f796c5e8e060 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.h
> +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> @@ -13,7 +13,7 @@
>
> #include "gt/intel_engine_types.h"
>
> -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
>
> struct drm_i915_private;
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 35ca528803fd..a2def7b27009 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> I915_MOCS_CACHED,
> };
>
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
> * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when requesting
> - * operations to be performed on a certain subset of engines, or for providing
> - * information about that group.
> + * engine serving each role. This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
> */
> enum drm_i915_gem_engine_class {
> + /**
> + * @I915_ENGINE_CLASS_RENDER:
> + *
> + * Render engines support instructions used for 3D, Compute (GPGPU),
> + * and programmable media workloads. These instructions fetch data and
> + * dispatch individual work items to threads that operate in parallel.
> + * The threads run small programs (called "kernels" or "shaders") on
> + * the GPU's execution units (EUs).
> + */
> I915_ENGINE_CLASS_RENDER = 0,
> +
> + /**
> + * @I915_ENGINE_CLASS_COPY:
> + *
> + * Copy engines (also referred to as "blitters") support instructions
> + * that move blocks of data from one location in memory to another,
> + * or that fill a specified location of memory with fixed data.
> + * Copy engines can perform pre-defined logical or bitwise operations
> + * on the source, destination, or pattern data.
> + */
> I915_ENGINE_CLASS_COPY = 1,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO:
> + *
> + * Video engines (also referred to as "bit stream decode" (BSD) or
> + * "vdbox") support instructions that perform fixed-function media
> + * decode and encode.
> + */
> I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + *
> + * Video enhancement engines (also referred to as "vebox") support
> + * instructions related to image enhancement.
> + */
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>
> - /* should be kept compact */
> + /**
> + * @I915_ENGINE_CLASS_COMPUTE:
> + *
> + * Compute engines support a subset of the instructions available
> + * on render engines: compute engines support Compute (GPGPU) and
> + * programmable media workloads, but do not support the 3D pipeline.
> + */
> + I915_ENGINE_CLASS_COMPUTE = 4,
> +
> + /* Values in this enum should be kept compact. */
>
> + /**
> + * @I915_ENGINE_CLASS_INVALID:
> + *
> + * Placeholder value to represent an invalid engine class assignment.
> + */
> I915_ENGINE_CLASS_INVALID = -1
> };
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-25 10:41 ` Tvrtko Ursulin
0 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2022-04-25 10:41 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Szymon Morek, dri-devel
On 22/04/2022 20:50, Matt Roper wrote:
> We're now ready to start exposing compute engines to userspace.
>
> While we're at it, let's extend the kerneldoc description for the other
> engine types as well.
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
The compute one points to a commit named "Add compute engine class for
xehp" but content of which seems more about engine query, including the
yet non-existent distance query (and more)?! I certainly does not appear
to be adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs
clarifying.
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> 5 files changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 0f6cd96b459f..46a174f8aa00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 92394f13b42f..c96e123496a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
Do you know what 0xcf04 is?
Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
might need adjusting to always select bit 0 for any compute engine
instance. Not sure how hardware would behave if value other than '1'
would be written into 0xced8.
Regards,
Tvrtko
> };
> struct drm_i915_private *i915 = gt->i915;
> struct intel_uncore *uncore = gt->uncore;
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> index 475a6f824cad..18d38cb59923 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.c
> +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> [I915_ENGINE_CLASS_COPY] = "copy",
> [I915_ENGINE_CLASS_VIDEO] = "video",
> [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> };
>
> static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> index 5f5b02b01ba0..f796c5e8e060 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.h
> +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> @@ -13,7 +13,7 @@
>
> #include "gt/intel_engine_types.h"
>
> -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
>
> struct drm_i915_private;
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 35ca528803fd..a2def7b27009 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> I915_MOCS_CACHED,
> };
>
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
> * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when requesting
> - * operations to be performed on a certain subset of engines, or for providing
> - * information about that group.
> + * engine serving each role. This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
> */
> enum drm_i915_gem_engine_class {
> + /**
> + * @I915_ENGINE_CLASS_RENDER:
> + *
> + * Render engines support instructions used for 3D, Compute (GPGPU),
> + * and programmable media workloads. These instructions fetch data and
> + * dispatch individual work items to threads that operate in parallel.
> + * The threads run small programs (called "kernels" or "shaders") on
> + * the GPU's execution units (EUs).
> + */
> I915_ENGINE_CLASS_RENDER = 0,
> +
> + /**
> + * @I915_ENGINE_CLASS_COPY:
> + *
> + * Copy engines (also referred to as "blitters") support instructions
> + * that move blocks of data from one location in memory to another,
> + * or that fill a specified location of memory with fixed data.
> + * Copy engines can perform pre-defined logical or bitwise operations
> + * on the source, destination, or pattern data.
> + */
> I915_ENGINE_CLASS_COPY = 1,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO:
> + *
> + * Video engines (also referred to as "bit stream decode" (BSD) or
> + * "vdbox") support instructions that perform fixed-function media
> + * decode and encode.
> + */
> I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + *
> + * Video enhancement engines (also referred to as "vebox") support
> + * instructions related to image enhancement.
> + */
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>
> - /* should be kept compact */
> + /**
> + * @I915_ENGINE_CLASS_COMPUTE:
> + *
> + * Compute engines support a subset of the instructions available
> + * on render engines: compute engines support Compute (GPGPU) and
> + * programmable media workloads, but do not support the 3D pipeline.
> + */
> + I915_ENGINE_CLASS_COMPUTE = 4,
> +
> + /* Values in this enum should be kept compact. */
>
> + /**
> + * @I915_ENGINE_CLASS_INVALID:
> + *
> + * Placeholder value to represent an invalid engine class assignment.
> + */
> I915_ENGINE_CLASS_INVALID = -1
> };
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
(?)
(?)
@ 2022-04-25 14:48 ` Andi Shyti
-1 siblings, 0 replies; 27+ messages in thread
From: Andi Shyti @ 2022-04-25 14:48 UTC (permalink / raw)
To: Matt Roper; +Cc: Szymon Morek, intel-gfx, dri-devel
Hi Matt,
On Fri, Apr 22, 2022 at 12:50:06PM -0700, Matt Roper wrote:
> We're now ready to start exposing compute engines to userspace.
>
> While we're at it, let's extend the kerneldoc description for the other
> engine types as well.
I would make two different patches. The kerneldoc description is
the biggest part of the lines added here.
Andi
>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Szymon Morek <szymon.morek@intel.com>
> UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> UMD (compute): https://github.com/intel/compute-runtime/pull/451
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> 5 files changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 0f6cd96b459f..46a174f8aa00 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> };
>
> static int engine_cmp(void *priv, const struct list_head *A,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 92394f13b42f..c96e123496a5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
> };
> struct drm_i915_private *i915 = gt->i915;
> struct intel_uncore *uncore = gt->uncore;
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> index 475a6f824cad..18d38cb59923 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.c
> +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> [I915_ENGINE_CLASS_COPY] = "copy",
> [I915_ENGINE_CLASS_VIDEO] = "video",
> [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> };
>
> static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> index 5f5b02b01ba0..f796c5e8e060 100644
> --- a/drivers/gpu/drm/i915/i915_drm_client.h
> +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> @@ -13,7 +13,7 @@
>
> #include "gt/intel_engine_types.h"
>
> -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
>
> struct drm_i915_private;
>
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 35ca528803fd..a2def7b27009 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> I915_MOCS_CACHED,
> };
>
> -/*
> +/**
> + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> + *
> * Different engines serve different roles, and there may be more than one
> - * engine serving each role. enum drm_i915_gem_engine_class provides a
> - * classification of the role of the engine, which may be used when requesting
> - * operations to be performed on a certain subset of engines, or for providing
> - * information about that group.
> + * engine serving each role. This enum provides a classification of the role
> + * of the engine, which may be used when requesting operations to be performed
> + * on a certain subset of engines, or for providing information about that
> + * group.
> */
> enum drm_i915_gem_engine_class {
> + /**
> + * @I915_ENGINE_CLASS_RENDER:
> + *
> + * Render engines support instructions used for 3D, Compute (GPGPU),
> + * and programmable media workloads. These instructions fetch data and
> + * dispatch individual work items to threads that operate in parallel.
> + * The threads run small programs (called "kernels" or "shaders") on
> + * the GPU's execution units (EUs).
> + */
> I915_ENGINE_CLASS_RENDER = 0,
> +
> + /**
> + * @I915_ENGINE_CLASS_COPY:
> + *
> + * Copy engines (also referred to as "blitters") support instructions
> + * that move blocks of data from one location in memory to another,
> + * or that fill a specified location of memory with fixed data.
> + * Copy engines can perform pre-defined logical or bitwise operations
> + * on the source, destination, or pattern data.
> + */
> I915_ENGINE_CLASS_COPY = 1,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO:
> + *
> + * Video engines (also referred to as "bit stream decode" (BSD) or
> + * "vdbox") support instructions that perform fixed-function media
> + * decode and encode.
> + */
> I915_ENGINE_CLASS_VIDEO = 2,
> +
> + /**
> + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> + *
> + * Video enhancement engines (also referred to as "vebox") support
> + * instructions related to image enhancement.
> + */
> I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
>
> - /* should be kept compact */
> + /**
> + * @I915_ENGINE_CLASS_COMPUTE:
> + *
> + * Compute engines support a subset of the instructions available
> + * on render engines: compute engines support Compute (GPGPU) and
> + * programmable media workloads, but do not support the 3D pipeline.
> + */
> + I915_ENGINE_CLASS_COMPUTE = 4,
> +
> + /* Values in this enum should be kept compact. */
>
> + /**
> + * @I915_ENGINE_CLASS_INVALID:
> + *
> + * Placeholder value to represent an invalid engine class assignment.
> + */
> I915_ENGINE_CLASS_INVALID = -1
> };
>
> --
> 2.35.1
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
(?)
@ 2022-04-25 14:48 ` Andi Shyti
-1 siblings, 0 replies; 27+ messages in thread
From: Andi Shyti @ 2022-04-25 14:48 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, dri-devel
On Fri, Apr 22, 2022 at 12:50:07PM -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-25 10:41 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-04-25 17:35 ` Matt Roper
-1 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-25 17:35 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: Szymon Morek, intel-gfx, dri-devel, Daniele Ceraolo Spurio,
Fei Yang, Jordan Justen, Vinay Belgaumkar, Prathap Kumar Valsan
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Szymon Morek <szymon.morek@intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> > UMD (compute): https://github.com/intel/compute-runtime/pull/451
>
> The compute one points to a commit named "Add compute engine class for xehp"
> but content of which seems more about engine query, including the yet
> non-existent distance query (and more)?! I certainly does not appear to be
> adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> > include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> > 5 files changed, 60 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > index 0f6cd96b459f..46a174f8aa00 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> > [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> > [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> > [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> > - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> > + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> > };
> > static int engine_cmp(void *priv, const struct list_head *A,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 92394f13b42f..c96e123496a5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>
> Do you know what 0xcf04 is?
>
> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might
> need adjusting to always select bit 0 for any compute engine instance. Not
> sure how hardware would behave if value other than '1' would be written into
> 0xced8.
I think Prathap and Fei have more familiarity with the MMIO TLB
invalidation; adding them for their thoughts.
Matt
>
> Regards,
>
> Tvrtko
>
> > };
> > struct drm_i915_private *i915 = gt->i915;
> > struct intel_uncore *uncore = gt->uncore;
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> > index 475a6f824cad..18d38cb59923 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.c
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> > @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> > [I915_ENGINE_CLASS_COPY] = "copy",
> > [I915_ENGINE_CLASS_VIDEO] = "video",
> > [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> > + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> > };
> > static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> > index 5f5b02b01ba0..f796c5e8e060 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.h
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> > @@ -13,7 +13,7 @@
> > #include "gt/intel_engine_types.h"
> > -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> > +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
> > struct drm_i915_private;
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 35ca528803fd..a2def7b27009 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> > I915_MOCS_CACHED,
> > };
> > -/*
> > +/**
> > + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> > + *
> > * Different engines serve different roles, and there may be more than one
> > - * engine serving each role. enum drm_i915_gem_engine_class provides a
> > - * classification of the role of the engine, which may be used when requesting
> > - * operations to be performed on a certain subset of engines, or for providing
> > - * information about that group.
> > + * engine serving each role. This enum provides a classification of the role
> > + * of the engine, which may be used when requesting operations to be performed
> > + * on a certain subset of engines, or for providing information about that
> > + * group.
> > */
> > enum drm_i915_gem_engine_class {
> > + /**
> > + * @I915_ENGINE_CLASS_RENDER:
> > + *
> > + * Render engines support instructions used for 3D, Compute (GPGPU),
> > + * and programmable media workloads. These instructions fetch data and
> > + * dispatch individual work items to threads that operate in parallel.
> > + * The threads run small programs (called "kernels" or "shaders") on
> > + * the GPU's execution units (EUs).
> > + */
> > I915_ENGINE_CLASS_RENDER = 0,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_COPY:
> > + *
> > + * Copy engines (also referred to as "blitters") support instructions
> > + * that move blocks of data from one location in memory to another,
> > + * or that fill a specified location of memory with fixed data.
> > + * Copy engines can perform pre-defined logical or bitwise operations
> > + * on the source, destination, or pattern data.
> > + */
> > I915_ENGINE_CLASS_COPY = 1,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO:
> > + *
> > + * Video engines (also referred to as "bit stream decode" (BSD) or
> > + * "vdbox") support instructions that perform fixed-function media
> > + * decode and encode.
> > + */
> > I915_ENGINE_CLASS_VIDEO = 2,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> > + *
> > + * Video enhancement engines (also referred to as "vebox") support
> > + * instructions related to image enhancement.
> > + */
> > I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> > - /* should be kept compact */
> > + /**
> > + * @I915_ENGINE_CLASS_COMPUTE:
> > + *
> > + * Compute engines support a subset of the instructions available
> > + * on render engines: compute engines support Compute (GPGPU) and
> > + * programmable media workloads, but do not support the 3D pipeline.
> > + */
> > + I915_ENGINE_CLASS_COMPUTE = 4,
> > +
> > + /* Values in this enum should be kept compact. */
> > + /**
> > + * @I915_ENGINE_CLASS_INVALID:
> > + *
> > + * Placeholder value to represent an invalid engine class assignment.
> > + */
> > I915_ENGINE_CLASS_INVALID = -1
> > };
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-25 17:35 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-25 17:35 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Szymon Morek, intel-gfx, dri-devel
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Szymon Morek <szymon.morek@intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> > UMD (compute): https://github.com/intel/compute-runtime/pull/451
>
> The compute one points to a commit named "Add compute engine class for xehp"
> but content of which seems more about engine query, including the yet
> non-existent distance query (and more)?! I certainly does not appear to be
> adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> > include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> > 5 files changed, 60 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > index 0f6cd96b459f..46a174f8aa00 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> > [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> > [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> > [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> > - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> > + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> > };
> > static int engine_cmp(void *priv, const struct list_head *A,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 92394f13b42f..c96e123496a5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>
> Do you know what 0xcf04 is?
>
> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might
> need adjusting to always select bit 0 for any compute engine instance. Not
> sure how hardware would behave if value other than '1' would be written into
> 0xced8.
I think Prathap and Fei have more familiarity with the MMIO TLB
invalidation; adding them for their thoughts.
Matt
>
> Regards,
>
> Tvrtko
>
> > };
> > struct drm_i915_private *i915 = gt->i915;
> > struct intel_uncore *uncore = gt->uncore;
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> > index 475a6f824cad..18d38cb59923 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.c
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> > @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> > [I915_ENGINE_CLASS_COPY] = "copy",
> > [I915_ENGINE_CLASS_VIDEO] = "video",
> > [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> > + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> > };
> > static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> > index 5f5b02b01ba0..f796c5e8e060 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.h
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> > @@ -13,7 +13,7 @@
> > #include "gt/intel_engine_types.h"
> > -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> > +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
> > struct drm_i915_private;
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 35ca528803fd..a2def7b27009 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> > I915_MOCS_CACHED,
> > };
> > -/*
> > +/**
> > + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> > + *
> > * Different engines serve different roles, and there may be more than one
> > - * engine serving each role. enum drm_i915_gem_engine_class provides a
> > - * classification of the role of the engine, which may be used when requesting
> > - * operations to be performed on a certain subset of engines, or for providing
> > - * information about that group.
> > + * engine serving each role. This enum provides a classification of the role
> > + * of the engine, which may be used when requesting operations to be performed
> > + * on a certain subset of engines, or for providing information about that
> > + * group.
> > */
> > enum drm_i915_gem_engine_class {
> > + /**
> > + * @I915_ENGINE_CLASS_RENDER:
> > + *
> > + * Render engines support instructions used for 3D, Compute (GPGPU),
> > + * and programmable media workloads. These instructions fetch data and
> > + * dispatch individual work items to threads that operate in parallel.
> > + * The threads run small programs (called "kernels" or "shaders") on
> > + * the GPU's execution units (EUs).
> > + */
> > I915_ENGINE_CLASS_RENDER = 0,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_COPY:
> > + *
> > + * Copy engines (also referred to as "blitters") support instructions
> > + * that move blocks of data from one location in memory to another,
> > + * or that fill a specified location of memory with fixed data.
> > + * Copy engines can perform pre-defined logical or bitwise operations
> > + * on the source, destination, or pattern data.
> > + */
> > I915_ENGINE_CLASS_COPY = 1,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO:
> > + *
> > + * Video engines (also referred to as "bit stream decode" (BSD) or
> > + * "vdbox") support instructions that perform fixed-function media
> > + * decode and encode.
> > + */
> > I915_ENGINE_CLASS_VIDEO = 2,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> > + *
> > + * Video enhancement engines (also referred to as "vebox") support
> > + * instructions related to image enhancement.
> > + */
> > I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> > - /* should be kept compact */
> > + /**
> > + * @I915_ENGINE_CLASS_COMPUTE:
> > + *
> > + * Compute engines support a subset of the instructions available
> > + * on render engines: compute engines support Compute (GPGPU) and
> > + * programmable media workloads, but do not support the 3D pipeline.
> > + */
> > + I915_ENGINE_CLASS_COMPUTE = 4,
> > +
> > + /* Values in this enum should be kept compact. */
> > + /**
> > + * @I915_ENGINE_CLASS_INVALID:
> > + *
> > + * Placeholder value to represent an invalid engine class assignment.
> > + */
> > I915_ENGINE_CLASS_INVALID = -1
> > };
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-25 17:35 ` [Intel-gfx] " Matt Roper
@ 2022-04-25 18:40 ` Yang, Fei
-1 siblings, 0 replies; 27+ messages in thread
From: Yang, Fei @ 2022-04-25 18:40 UTC (permalink / raw)
To: Roper, Matthew D, Tvrtko Ursulin
Cc: Morek, Szymon, intel-gfx, dri-devel, Ceraolo Spurio, Daniele,
Justen, Jordan L, Belgaumkar, Vinay, Kumar Valsan, Prathap
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
>> > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
>> > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
>> > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
>> > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>>
>> Do you know what 0xcf04 is?
Looks like that is the TLB invalidation register for each compute context.
>>
>> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
>> might need adjusting to always select bit 0 for any compute engine
>> instance. Not sure how hardware would behave if value other than '1'
>> would be written into 0xced8.
>
> I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine.
I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
> Matt
>>
>> Regards,
>>
>> Tvrtko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-25 18:40 ` Yang, Fei
0 siblings, 0 replies; 27+ messages in thread
From: Yang, Fei @ 2022-04-25 18:40 UTC (permalink / raw)
To: Roper, Matthew D, Tvrtko Ursulin; +Cc: Morek, Szymon, intel-gfx, dri-devel
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
>> > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
>> > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
>> > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
>> > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>>
>> Do you know what 0xcf04 is?
Looks like that is the TLB invalidation register for each compute context.
>>
>> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
>> might need adjusting to always select bit 0 for any compute engine
>> instance. Not sure how hardware would behave if value other than '1'
>> would be written into 0xced8.
>
> I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine.
I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
> Matt
>>
>> Regards,
>>
>> Tvrtko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-25 18:40 ` [Intel-gfx] " Yang, Fei
@ 2022-04-26 7:25 ` Tvrtko Ursulin
-1 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2022-04-26 7:25 UTC (permalink / raw)
To: Yang, Fei, Roper, Matthew D
Cc: Morek, Szymon, intel-gfx, dri-devel, Ceraolo Spurio, Daniele,
Justen, Jordan L, Belgaumkar, Vinay, Kumar Valsan, Prathap
On 25/04/2022 19:40, Yang, Fei wrote:
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
>>>> [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
>>>> [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
>>>> [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
>>>> + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>>>
>>> Do you know what 0xcf04 is?
>
> Looks like that is the TLB invalidation register for each compute context.
What does compute "context" stand for in this context, as used in bspec?
Not compute command streamer? Suspiciously individual bits (eight of
them) are reserved per context, just like for example in
GEN12_VD_TLB_INV_CR.
>>> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
>>> might need adjusting to always select bit 0 for any compute engine
>>> instance. Not sure how hardware would behave if value other than '1'
>>> would be written into 0xced8.
>>
>> I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
>
> I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine.
I don't understand this argument, I guess because I don't understand
0xcf04 still.
> I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
Or even correct if 0xcf04 is for compute command streamers? That's my
concern.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-26 7:25 ` Tvrtko Ursulin
0 siblings, 0 replies; 27+ messages in thread
From: Tvrtko Ursulin @ 2022-04-26 7:25 UTC (permalink / raw)
To: Yang, Fei, Roper, Matthew D; +Cc: Morek, Szymon, intel-gfx, dri-devel
On 25/04/2022 19:40, Yang, Fei wrote:
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
>>>> [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
>>>> [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
>>>> [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
>>>> + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>>>
>>> Do you know what 0xcf04 is?
>
> Looks like that is the TLB invalidation register for each compute context.
What does compute "context" stand for in this context, as used in bspec?
Not compute command streamer? Suspiciously individual bits (eight of
them) are reserved per context, just like for example in
GEN12_VD_TLB_INV_CR.
>>> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit()
>>> might need adjusting to always select bit 0 for any compute engine
>>> instance. Not sure how hardware would behave if value other than '1'
>>> would be written into 0xced8.
>>
>> I think Prathap and Fei have more familiarity with the MMIO TLB invalidation; adding them for their thoughts.
>
> I believe GEN12_GFX_TLB_INV_CR is the right one to use because we are invalidating the TLB for each engine.
I don't understand this argument, I guess because I don't understand
0xcf04 still.
> I'm not sure if we could narrow down to exact which compute context the TLB needs to be invalidated though. If that's possible it might be a bit more efficient.
Or even correct if 0xcf04 is for compute command streamers? That's my
concern.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-25 10:41 ` [Intel-gfx] " Tvrtko Ursulin
(?)
(?)
@ 2022-04-28 0:27 ` Kumar Valsan, Prathap
-1 siblings, 0 replies; 27+ messages in thread
From: Kumar Valsan, Prathap @ 2022-04-28 0:27 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Szymon Morek, intel-gfx, dri-devel
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Szymon Morek <szymon.morek@intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> > UMD (compute): https://github.com/intel/compute-runtime/pull/451
>
> The compute one points to a commit named "Add compute engine class for xehp"
> but content of which seems more about engine query, including the yet
> non-existent distance query (and more)?! I certainly does not appear to be
> adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.c | 1 +
> > drivers/gpu/drm/i915/i915_drm_client.h | 2 +-
> > include/uapi/drm/i915_drm.h | 62 +++++++++++++++++++--
> > 5 files changed, 60 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > index 0f6cd96b459f..46a174f8aa00 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > @@ -47,7 +47,7 @@ static const u8 uabi_classes[] = {
> > [COPY_ENGINE_CLASS] = I915_ENGINE_CLASS_COPY,
> > [VIDEO_DECODE_CLASS] = I915_ENGINE_CLASS_VIDEO,
> > [VIDEO_ENHANCEMENT_CLASS] = I915_ENGINE_CLASS_VIDEO_ENHANCE,
> > - /* TODO: Add COMPUTE_CLASS mapping once ABI is available */
> > + [COMPUTE_CLASS] = I915_ENGINE_CLASS_COMPUTE,
> > };
> > static int engine_cmp(void *priv, const struct list_head *A,
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > index 92394f13b42f..c96e123496a5 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > @@ -1175,6 +1175,7 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
> > [VIDEO_DECODE_CLASS] = GEN12_VD_TLB_INV_CR,
> > [VIDEO_ENHANCEMENT_CLASS] = GEN12_VE_TLB_INV_CR,
> > [COPY_ENGINE_CLASS] = GEN12_BLT_TLB_INV_CR,
> > + [COMPUTE_CLASS] = GEN12_GFX_TLB_INV_CR,
>
> Do you know what 0xcf04 is?
The mmio 0xcf04 is the one we should use for compute class.
And the context bit in 0xcf04 represents engine instance.
GEN12_GFX_TLB_INV_CR is for render class.
Thanks,
Prathap
>
> Or if GEN12_GFX_TLB_INV_CR is correct then I think get_reg_and_bit() might
> need adjusting to always select bit 0 for any compute engine instance. Not
> sure how hardware would behave if value other than '1' would be written into
> 0xced8.
>
> Regards,
>
> Tvrtko
>
> > };
> > struct drm_i915_private *i915 = gt->i915;
> > struct intel_uncore *uncore = gt->uncore;
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.c b/drivers/gpu/drm/i915/i915_drm_client.c
> > index 475a6f824cad..18d38cb59923 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.c
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.c
> > @@ -81,6 +81,7 @@ static const char * const uabi_class_names[] = {
> > [I915_ENGINE_CLASS_COPY] = "copy",
> > [I915_ENGINE_CLASS_VIDEO] = "video",
> > [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "video-enhance",
> > + [I915_ENGINE_CLASS_COMPUTE] = "compute",
> > };
> > static u64 busy_add(struct i915_gem_context *ctx, unsigned int class)
> > diff --git a/drivers/gpu/drm/i915/i915_drm_client.h b/drivers/gpu/drm/i915/i915_drm_client.h
> > index 5f5b02b01ba0..f796c5e8e060 100644
> > --- a/drivers/gpu/drm/i915/i915_drm_client.h
> > +++ b/drivers/gpu/drm/i915/i915_drm_client.h
> > @@ -13,7 +13,7 @@
> > #include "gt/intel_engine_types.h"
> > -#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_VIDEO_ENHANCE
> > +#define I915_LAST_UABI_ENGINE_CLASS I915_ENGINE_CLASS_COMPUTE
> > struct drm_i915_private;
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 35ca528803fd..a2def7b27009 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -154,21 +154,71 @@ enum i915_mocs_table_index {
> > I915_MOCS_CACHED,
> > };
> > -/*
> > +/**
> > + * enum drm_i915_gem_engine_class - uapi engine type enumeration
> > + *
> > * Different engines serve different roles, and there may be more than one
> > - * engine serving each role. enum drm_i915_gem_engine_class provides a
> > - * classification of the role of the engine, which may be used when requesting
> > - * operations to be performed on a certain subset of engines, or for providing
> > - * information about that group.
> > + * engine serving each role. This enum provides a classification of the role
> > + * of the engine, which may be used when requesting operations to be performed
> > + * on a certain subset of engines, or for providing information about that
> > + * group.
> > */
> > enum drm_i915_gem_engine_class {
> > + /**
> > + * @I915_ENGINE_CLASS_RENDER:
> > + *
> > + * Render engines support instructions used for 3D, Compute (GPGPU),
> > + * and programmable media workloads. These instructions fetch data and
> > + * dispatch individual work items to threads that operate in parallel.
> > + * The threads run small programs (called "kernels" or "shaders") on
> > + * the GPU's execution units (EUs).
> > + */
> > I915_ENGINE_CLASS_RENDER = 0,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_COPY:
> > + *
> > + * Copy engines (also referred to as "blitters") support instructions
> > + * that move blocks of data from one location in memory to another,
> > + * or that fill a specified location of memory with fixed data.
> > + * Copy engines can perform pre-defined logical or bitwise operations
> > + * on the source, destination, or pattern data.
> > + */
> > I915_ENGINE_CLASS_COPY = 1,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO:
> > + *
> > + * Video engines (also referred to as "bit stream decode" (BSD) or
> > + * "vdbox") support instructions that perform fixed-function media
> > + * decode and encode.
> > + */
> > I915_ENGINE_CLASS_VIDEO = 2,
> > +
> > + /**
> > + * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
> > + *
> > + * Video enhancement engines (also referred to as "vebox") support
> > + * instructions related to image enhancement.
> > + */
> > I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
> > - /* should be kept compact */
> > + /**
> > + * @I915_ENGINE_CLASS_COMPUTE:
> > + *
> > + * Compute engines support a subset of the instructions available
> > + * on render engines: compute engines support Compute (GPGPU) and
> > + * programmable media workloads, but do not support the 3D pipeline.
> > + */
> > + I915_ENGINE_CLASS_COMPUTE = 4,
> > +
> > + /* Values in this enum should be kept compact. */
> > + /**
> > + * @I915_ENGINE_CLASS_INVALID:
> > + *
> > + * Placeholder value to represent an invalid engine class assignment.
> > + */
> > I915_ENGINE_CLASS_INVALID = -1
> > };
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
2022-04-25 10:41 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-04-28 3:44 ` Matt Roper
-1 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-28 3:44 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: Szymon Morek, intel-gfx, dri-devel, Daniele Ceraolo Spurio,
Jordan Justen, Vinay Belgaumkar
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Szymon Morek <szymon.morek@intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> > UMD (compute): https://github.com/intel/compute-runtime/pull/451
>
> The compute one points to a commit named "Add compute engine class for xehp"
> but content of which seems more about engine query, including the yet
> non-existent distance query (and more)?! I certainly does not appear to be
> adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
>
Hi Syzmon, any updates on the compute UMD merge request here? Is there
a different merge request we should reference for now that just uses the
I915_ENGINE_CLASS_COMPUTE without also relying on the
DRM_I915_QUERY_DISTANCE_INFO that we aren't upstreaming just yet?
I believe distance info is only useful for multi-tile platforms and
isn't necessary for general use of compute engines on a single tile
platform.
Thanks.
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Add compute engine ABI
@ 2022-04-28 3:44 ` Matt Roper
0 siblings, 0 replies; 27+ messages in thread
From: Matt Roper @ 2022-04-28 3:44 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Szymon Morek, intel-gfx, dri-devel
On Mon, Apr 25, 2022 at 11:41:36AM +0100, Tvrtko Ursulin wrote:
>
> On 22/04/2022 20:50, Matt Roper wrote:
> > We're now ready to start exposing compute engines to userspace.
> >
> > While we're at it, let's extend the kerneldoc description for the other
> > engine types as well.
> >
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> > Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Szymon Morek <szymon.morek@intel.com>
> > UMD (mesa): https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14395
> > UMD (compute): https://github.com/intel/compute-runtime/pull/451
>
> The compute one points to a commit named "Add compute engine class for xehp"
> but content of which seems more about engine query, including the yet
> non-existent distance query (and more)?! I certainly does not appear to be
> adding a definition of I915_ENGINE_CLASS_COMPUTE. This needs clarifying.
>
Hi Syzmon, any updates on the compute UMD merge request here? Is there
a different merge request we should reference for now that just uses the
I915_ENGINE_CLASS_COMPUTE without also relying on the
DRM_I915_QUERY_DISTANCE_INFO that we aren't upstreaming just yet?
I believe distance info is only useful for multi-tile platforms and
isn't necessary for general use of compute engines on a single tile
platform.
Thanks.
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2022-04-28 3:44 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-22 19:50 [PATCH 0/2] i915: Turn on compute engine support Matt Roper
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
2022-04-22 19:50 ` [PATCH 1/2] drm/i915/xehp: Add compute engine ABI Matt Roper
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
2022-04-25 10:41 ` Tvrtko Ursulin
2022-04-25 10:41 ` [Intel-gfx] " Tvrtko Ursulin
2022-04-25 17:35 ` Matt Roper
2022-04-25 17:35 ` [Intel-gfx] " Matt Roper
2022-04-25 18:40 ` Yang, Fei
2022-04-25 18:40 ` [Intel-gfx] " Yang, Fei
2022-04-26 7:25 ` Tvrtko Ursulin
2022-04-26 7:25 ` [Intel-gfx] " Tvrtko Ursulin
2022-04-28 0:27 ` Kumar Valsan, Prathap
2022-04-28 3:44 ` Matt Roper
2022-04-28 3:44 ` [Intel-gfx] " Matt Roper
2022-04-25 14:48 ` Andi Shyti
2022-04-22 19:50 ` [PATCH 2/2] drm/i915: Xe_HP SDV and DG2 have up to 4 CCS engines Matt Roper
2022-04-22 19:50 ` [Intel-gfx] " Matt Roper
2022-04-25 14:48 ` Andi Shyti
2022-04-22 20:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support Patchwork
2022-04-22 20:47 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-22 21:32 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev2) Patchwork
2022-04-22 22:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-22 22:33 ` Matt Roper
2022-04-22 23:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: Turn on compute engine support (rev3) Patchwork
2022-04-22 23:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-04-23 1:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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