From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B0B2FC433EF for ; Mon, 25 Apr 2022 14:28:27 +0000 (UTC) Received: from localhost ([::1]:35662 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nizhS-000711-JT for qemu-devel@archiver.kernel.org; Mon, 25 Apr 2022 10:28:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY6-0007JS-5K; Mon, 25 Apr 2022 10:18:47 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY4-0003Q5-9V; Mon, 25 Apr 2022 10:18:45 -0400 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 4D2E511EF81; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) From: ~eopxd Date: Thu, 17 Mar 2022 01:46:28 -0700 Subject: [PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions Message-ID: <165089631935.4839.7564289944057093570-5@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tran= s/trans_rvv.c.inc index a085ef2c29..be08ec8a2e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1742,6 +1742,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 269e40c251..2b341d6679 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1401,12 +1401,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ @@ -1459,11 +1464,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ --=20 2.34.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1nizY8-0007QF-Sb for mharc-qemu-riscv@gnu.org; Mon, 25 Apr 2022 10:18:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY6-0007JS-5K; Mon, 25 Apr 2022 10:18:47 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:41756) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nizY4-0003Q5-9V; Mon, 25 Apr 2022 10:18:45 -0400 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 4D2E511EF81; Mon, 25 Apr 2022 14:18:40 +0000 (UTC) From: ~eopxd Subject: [PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions Message-ID: <165089631935.4839.7564289944057093570-5@git.sr.ht> X-Mailer: git.sr.ht Reply-to: ~eopxd In-Reply-To: <165089631935.4839.7564289944057093570-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , WeiWei Li , eop Chen Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Date: Mon, 25 Apr 2022 14:18:47 -0000 X-Original-Date: Thu, 17 Mar 2022 01:46:28 -0700 X-List-Received-Date: Mon, 25 Apr 2022 14:18:47 -0000 From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tran= s/trans_rvv.c.inc index a085ef2c29..be08ec8a2e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1742,6 +1742,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) = \ data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), cpu_env, \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 269e40c251..2b341d6679 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -1401,12 +1401,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s1 =3D *((ETYPE *)vs1 + H(i)); \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ @@ -1459,11 +1464,16 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1= , void *vs2, \ uint32_t esz =3D sizeof(ETYPE); \ uint32_t total_elems =3D vext_get_total_elems(desc, esz); \ uint32_t vta =3D vext_vta(desc); \ + uint32_t vma =3D vext_vma(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + if (vma) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ continue; \ } \ vext_set_elem_mask(vd, i, \ --=20 2.34.2