From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B21CC433F5 for ; Wed, 27 Apr 2022 10:12:21 +0000 (UTC) Received: from localhost ([::1]:55022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njeeh-0006NN-SN for qemu-devel@archiver.kernel.org; Wed, 27 Apr 2022 06:12:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njeXP-00055e-MZ; Wed, 27 Apr 2022 06:04:48 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:42136) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njeXN-0003X5-Gh; Wed, 27 Apr 2022 06:04:47 -0400 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 675AA11F00B; Wed, 27 Apr 2022 10:04:20 +0000 (UTC) From: ~eopxd Date: Mon, 07 Mar 2022 07:59:26 -0800 Subject: [PATCH qemu v9 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions Message-ID: <165105385811.8013.9841879319865783070-14@git.sr.ht> X-Mailer: git.sr.ht In-Reply-To: <165105385811.8013.9841879319865783070-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: ~eopxd Cc: WeiWei Li , Frank Chang , eop Chen , Bin Meng , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++ target/riscv/vector_helper.c | 40 +++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tran= s/trans_rvv.c.inc index ab9f876c28..2c9993844a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3744,6 +3744,16 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmr= r *a) } =20 if (a->vm && s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } int scale =3D s->lmul - (s->sew + 3); int vlmax =3D scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scal= e; @@ -3777,6 +3787,16 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmr= r *a) } =20 if (a->vm && s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } int scale =3D s->lmul - (s->sew + 3); int vlmax =3D scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scal= e; @@ -3829,6 +3849,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *= a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -3934,6 +3955,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uin= t8_t seq) } =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 20aa0aee2b..aa1623c52b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4911,6 +4911,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ target_ulong offset =3D s1, i_min, i; \ \ i_min =3D MAX(env->vstart, offset); \ @@ -4920,6 +4923,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); \ } \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] =3D vs2[i] */ @@ -4935,6 +4940,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ target_ulong i_max, i; \ \ i_max =3D MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \ @@ -4951,6 +4959,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+rs1] */ @@ -4966,6 +4976,9 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, ta= rget_ulong s1, \ typedef uint##BITWIDTH##_t ETYPE; \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ + uint32_t esz =3D sizeof(ETYPE); = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ @@ -4979,6 +4992,8 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, ta= rget_ulong s1, \ } \ } \ env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VSLIE1UP(8, H1) @@ -5006,6 +5021,9 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, = target_ulong s1, \ typedef uint##BITWIDTH##_t ETYPE; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ + uint32_t esz =3D sizeof(ETYPE); = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ @@ -5019,6 +5037,8 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, = target_ulong s1, \ } = \ } = \ env->vstart =3D 0; = \ + /* set tail elements to 1s */ = \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); = \ } =20 GEN_VEXT_VSLIDE1DOWN(8, H1) @@ -5072,6 +5092,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(TS2))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(TS2); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint64_t index; \ uint32_t i; \ \ @@ -5087,6 +5110,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ } \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vd[i] =3D (vs1[i] >=3D VLMAX) ? 0 : vs2[vs1[i]]; */ @@ -5107,6 +5132,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint64_t index =3D s1; \ uint32_t i; \ \ @@ -5121,6 +5149,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vd[i] =3D (x[rs1] >=3D VLMAX) ? 0 : vs2[rs1] */ @@ -5135,6 +5165,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t num =3D 0, i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -5145,6 +5178,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ num++; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* Compress into vd elements of vs2 where vs1 is enabled */ @@ -5181,6 +5216,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -5190,6 +5228,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ *((ETYPE *)vd + HD(i)) =3D *((DTYPE *)vs2 + HS1(i)); \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1) --=20 2.34.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1njeYG-0005Pc-Vd for mharc-qemu-riscv@gnu.org; Wed, 27 Apr 2022 06:05:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njeXP-00055e-MZ; Wed, 27 Apr 2022 06:04:48 -0400 Received: from mail-b.sr.ht ([173.195.146.151]:42136) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njeXN-0003X5-Gh; Wed, 27 Apr 2022 06:04:47 -0400 Authentication-Results: mail-b.sr.ht; dkim=none Received: from git.sr.ht (unknown [173.195.146.142]) by mail-b.sr.ht (Postfix) with ESMTPSA id 675AA11F00B; Wed, 27 Apr 2022 10:04:20 +0000 (UTC) From: ~eopxd Subject: [PATCH qemu v9 14/14] target/riscv: rvv: Add tail agnostic for vector permutation instructions Message-ID: <165105385811.8013.9841879319865783070-14@git.sr.ht> X-Mailer: git.sr.ht Reply-to: ~eopxd In-Reply-To: <165105385811.8013.9841879319865783070-0@git.sr.ht> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , WeiWei Li , eop Chen Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Received-SPF: pass client-ip=173.195.146.151; envelope-from=outgoing@sr.ht; helo=mail-b.sr.ht X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_96_XX=3.405, FREEMAIL_FORGED_REPLYTO=2.095, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Date: Wed, 27 Apr 2022 10:04:49 -0000 X-Original-Date: Mon, 07 Mar 2022 07:59:26 -0800 X-List-Received-Date: Wed, 27 Apr 2022 10:04:49 -0000 From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++ target/riscv/vector_helper.c | 40 +++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tran= s/trans_rvv.c.inc index ab9f876c28..2c9993844a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3744,6 +3744,16 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmr= r *a) } =20 if (a->vm && s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } int scale =3D s->lmul - (s->sew + 3); int vlmax =3D scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scal= e; @@ -3777,6 +3787,16 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmr= r *a) } =20 if (a->vm && s->vl_eq_vlmax) { + if (s->vta && s->lmul < 0) { + /* + * tail elements may pass vlmax when lmul < 0 + * set tail elements to 1s + */ + uint32_t vlenb =3D s->cfg_ptr->vlen >> 3; + tcg_gen_gvec_ori(s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rd), -1, + vlenb, vlenb); + } int scale =3D s->lmul - (s->sew + 3); int vlmax =3D scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scal= e; @@ -3829,6 +3849,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *= a) tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); =20 data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs1), vreg_ofs(s, a->rs2), cpu_env, s->cfg_ptr->vlen / 8, @@ -3934,6 +3955,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uin= t8_t seq) } =20 data =3D FIELD_DP32(data, VDATA, VM, a->vm); + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); =20 tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), vreg_ofs(s, a->rs2), cpu_env, diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 20aa0aee2b..aa1623c52b 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4911,6 +4911,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ { \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ target_ulong offset =3D s1, i_min, i; \ \ i_min =3D MAX(env->vstart, offset); \ @@ -4920,6 +4923,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ *((ETYPE *)vd + H(i)) =3D *((ETYPE *)vs2 + H(i - offset)); \ } \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] =3D vs2[i] */ @@ -4935,6 +4940,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ target_ulong i_max, i; \ \ i_max =3D MAX(MIN(s1 < vlmax ? vlmax - s1 : 0, vl), env->vstart); \ @@ -4951,6 +4959,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] =3D vs2[i+rs1] */ @@ -4966,6 +4976,9 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, ta= rget_ulong s1, \ typedef uint##BITWIDTH##_t ETYPE; \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ + uint32_t esz =3D sizeof(ETYPE); = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { = \ @@ -4979,6 +4992,8 @@ static void vslide1up_##BITWIDTH(void *vd, void *v0, ta= rget_ulong s1, \ } \ } \ env->vstart =3D 0; = \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_VSLIE1UP(8, H1) @@ -5006,6 +5021,9 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, = target_ulong s1, \ typedef uint##BITWIDTH##_t ETYPE; = \ uint32_t vm =3D vext_vm(desc); = \ uint32_t vl =3D env->vl; = \ + uint32_t esz =3D sizeof(ETYPE); = \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); = \ + uint32_t vta =3D vext_vta(desc); = \ uint32_t i; = \ = \ for (i =3D env->vstart; i < vl; i++) { = \ @@ -5019,6 +5037,8 @@ static void vslide1down_##BITWIDTH(void *vd, void *v0, = target_ulong s1, \ } = \ } = \ env->vstart =3D 0; = \ + /* set tail elements to 1s */ = \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); = \ } =20 GEN_VEXT_VSLIDE1DOWN(8, H1) @@ -5072,6 +5092,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(TS2))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(TS2); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint64_t index; \ uint32_t i; \ \ @@ -5087,6 +5110,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ } \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vd[i] =3D (vs1[i] >=3D VLMAX) ? 0 : vs2[vs1[i]]; */ @@ -5107,6 +5132,9 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ uint32_t vlmax =3D vext_max_elems(desc, ctzl(sizeof(ETYPE))); \ uint32_t vm =3D vext_vm(desc); \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint64_t index =3D s1; \ uint32_t i; \ \ @@ -5121,6 +5149,8 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, = void *vs2, \ } \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* vd[i] =3D (x[rs1] >=3D VLMAX) ? 0 : vs2[rs1] */ @@ -5135,6 +5165,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t num =3D 0, i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -5145,6 +5178,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *= vs2, \ num++; \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 /* Compress into vd elements of vs2 where vs1 is enabled */ @@ -5181,6 +5216,9 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ { \ uint32_t vl =3D env->vl; \ uint32_t vm =3D vext_vm(desc); \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t total_elems =3D vext_get_total_elems(env, desc, esz); \ + uint32_t vta =3D vext_vta(desc); \ uint32_t i; \ \ for (i =3D env->vstart; i < vl; i++) { \ @@ -5190,6 +5228,8 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, = \ *((ETYPE *)vd + HD(i)) =3D *((DTYPE *)vs2 + HS1(i)); \ } \ env->vstart =3D 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \ } =20 GEN_VEXT_INT_EXT(vzext_vf2_h, uint16_t, uint8_t, H2, H1) --=20 2.34.2