From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D296CC433EF for ; Wed, 4 May 2022 19:57:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377785AbiEDUBd (ORCPT ); Wed, 4 May 2022 16:01:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232347AbiEDUBa (ORCPT ); Wed, 4 May 2022 16:01:30 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31630DF26 for ; Wed, 4 May 2022 12:57:54 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BAC2860F38 for ; Wed, 4 May 2022 19:57:53 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFA25C385A5; Wed, 4 May 2022 19:57:51 +0000 (UTC) From: Catalin Marinas To: Michal Orzel , Will Deacon Cc: bertrand.marquis@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK Date: Wed, 4 May 2022 20:57:49 +0100 Message-Id: <165169425294.2576066.15457281640319913128.b4-ty@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220426070603.56031-1-michal.orzel@arm.com> References: <20220426070603.56031-1-michal.orzel@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 26 Apr 2022 09:06:03 +0200, Michal Orzel wrote: > Value of macro MIDR_IMPLEMENTOR_MASK exceeds the range of integer > and can lead to overflow. Currently there is no issue as it is used > in expressions implicitly casting it to u32. To avoid possible > problems, fix the macro. > > Applied to arm64 (for-next/misc), thanks! [1/1] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK https://git.kernel.org/arm64/c/48e6f22e25a4 -- Catalin From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD9D7C433F5 for ; Wed, 4 May 2022 19:59:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HrC3jBnx7IoeWG56TccjYVKO+tblMtzFuh3FpcSArI0=; b=D4H/vhMl1plg8H onhEaB34jUv0RAXSQ4qMR2i4IbDIYqVX8KyKguqKWcUCbgohyvokUvHdf0hE1t0BcCC0p6OrGGUFO NMKyofTMMYQTjJucbtMRiDUXCPhd/QsOF17gz4Ys7E3V/wVq8jYw7dEuxP4yC5idAUcSl/tgEw/pd bE8mz/vLYRJEg7h0kGIZSdlm+GXNRI/au6WdwFQbCZTD1uuWmC6UoIEDDUzGU/xw9XY0sSMbpfRnY WoGC7SQVeLqS1dtuB0N95MTDT1xWkryFFukVyKIez/W8EFYGsTf6IPWLX6PEzqW6W9h4+fto0FhWG MoDtyWOk3veBUGk/EpAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmL8K-00CRrA-Lr; Wed, 04 May 2022 19:58:00 +0000 Received: from ams.source.kernel.org ([145.40.68.75]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nmL8F-00CRpD-Nv for linux-arm-kernel@lists.infradead.org; Wed, 04 May 2022 19:57:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 5A3E5B828AA; Wed, 4 May 2022 19:57:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EFA25C385A5; Wed, 4 May 2022 19:57:51 +0000 (UTC) From: Catalin Marinas To: Michal Orzel , Will Deacon Cc: bertrand.marquis@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK Date: Wed, 4 May 2022 20:57:49 +0100 Message-Id: <165169425294.2576066.15457281640319913128.b4-ty@arm.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220426070603.56031-1-michal.orzel@arm.com> References: <20220426070603.56031-1-michal.orzel@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220504_125755_952608_155A50D8 X-CRM114-Status: GOOD ( 10.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 26 Apr 2022 09:06:03 +0200, Michal Orzel wrote: > Value of macro MIDR_IMPLEMENTOR_MASK exceeds the range of integer > and can lead to overflow. Currently there is no issue as it is used > in expressions implicitly casting it to u32. To avoid possible > problems, fix the macro. > > Applied to arm64 (for-next/misc), thanks! [1/1] arm64: cputype: Avoid overflow using MIDR_IMPLEMENTOR_MASK https://git.kernel.org/arm64/c/48e6f22e25a4 -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel